Merge branch 'master' of git://www.denx.de/git/u-boot-coldfire

85 files changed, 14531 insertions, 1440 deletions

diff --git a/CREDITS b/CREDITS
index edf825c..57a82d2 100644
--- a/CREDITS
+++ b/CREDITS
@@ -290,7 +290,7 @@ W: http://www.leox.org
 
 N: TsiChung Liew
 E: Tsi-Chung.Liew@freescale.com
-D: Support for ColdFire MCF523x, MCF532x, MCF5445x
+D: Support for ColdFire MCF523x, MCF532x, MCF5445x, MCF547x_8x
 W: www.freescale.com
 
 N: Leif Lindholm
diff --git a/MAINTAINERS b/MAINTAINERS
index ef16d68..74cbaa9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -648,9 +648,13 @@ Zachary P. Landau <zachary.landau@labxtechnologies.com>
 
 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 
+	M52277EVB		mcf5227x
 	M5235EVB		mcf52x2
 	M5329EVB		mcf532x
+	M5373EVB		mcf532x
 	M54455EVB		mcf5445x
+	M5475EVB		mcf547x_8x
+	M5485EVB		mcf547x_8x
 
 Hayden Fraser <Hayden.Fraser@freescale.com>
 
diff --git a/MAKEALL b/MAKEALL
index 5e37e73..fabf319 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -644,14 +644,18 @@ LIST_coldfire="			\
 	EB+MCF-EV123		\
 	EB+MCF-EV123_internal	\
 	idmr			\
+	M52277EVB		\
 	M5235EVB		\
 	M5249EVB		\
 	M5253EVB		\
 	M5271EVB		\
 	M5272C3			\
 	M5282EVB		\
-	M5329EVB		\
+	M5329AFEE		\
+	M5373EVB		\
 	M54455EVB		\
+	M5475AFE		\
+	M5485AFE		\
 	r5200			\
 	TASREG			\
 "
diff --git a/Makefile b/Makefile
index 86c2ba0..382eab6 100644
--- a/Makefile
+++ b/Makefile
@@ -218,6 +218,7 @@ LIBS += net/libnet.a
 LIBS += disk/libdisk.a
 LIBS += drivers/bios_emulator/libatibiosemu.a
 LIBS += drivers/block/libblock.a
+LIBS += drivers/dma/libdma.a
 LIBS += drivers/hwmon/libhwmon.a
 LIBS += drivers/i2c/libi2c.a
 LIBS += drivers/input/libinput.a
@@ -1744,6 +1745,9 @@ ZPC1900_config: unconfig
 ## Coldfire
 #########################################################################
 
+M52277EVB_config:	unconfig
+	@$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale
+
 M5235EVB_config \
 M5235EVB_Flash16_config \
 M5235EVB_Flash32_config:	unconfig
@@ -1816,6 +1820,16 @@ M5329BFEE_config :	unconfig
 	fi
 	@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
 
+M5373EVB_config :	unconfig
+	@case "$@" in \
+	M5373EVB_config)	NAND=16;; \
+	esac; \
+	>include/config.h ; \
+	if [ "$${NAND}" != "0" ] ; then \
+		echo "#define NANDFLASH_SIZE	$${NAND}" > $(obj)include/config.h ; \
+	fi
+	@$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
+
 M54455EVB_config \
 M54455EVB_atmel_config \
 M54455EVB_intel_config \
@@ -1848,6 +1862,76 @@ M54455EVB_i66_config :	unconfig
 	$(XECHO) "... with $${FREQ}Hz input clock"
 	@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
 
+M5475AFE_config \
+M5475BFE_config \
+M5475CFE_config \
+M5475DFE_config \
+M5475EFE_config \
+M5475FFE_config \
+M5475GFE_config :	unconfig
+	@case "$@" in \
+	M5475AFE_config)	BOOT=2;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
+	M5475BFE_config)	BOOT=2;CODE=16;VID=0;USB=0;RAM=64;RAM1=0;; \
+	M5475CFE_config)	BOOT=2;CODE=16;VID=1;USB=1;RAM=64;RAM1=0;; \
+	M5475DFE_config)	BOOT=2;CODE=0;VID=0;USB=1;RAM=64;RAM1=0;; \
+	M5475EFE_config)	BOOT=2;CODE=0;VID=1;USB=1;RAM=64;RAM1=0;; \
+	M5475FFE_config)	BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
+	M5475GFE_config)	BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
+	esac; \
+	>include/config.h ; \
+	echo "#define CFG_BUSCLK	133333333" > $(obj)include/config.h ; \
+	echo "#define CFG_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
+	echo "#define CFG_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
+	if [ "$${RAM1}" != "0" ] ; then \
+		echo "#define CFG_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
+	fi; \
+	if [ "$${CODE}" != "0" ] ; then \
+		echo "#define CFG_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
+	fi; \
+	if [ "$${VID}" == "1" ] ; then \
+		echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
+	fi; \
+	if [ "$${USB}" == "1" ] ; then \
+		echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
+	fi
+	@$(MKCONFIG) -a M5475EVB m68k mcf547x_8x m547xevb freescale
+
+M5485AFE_config \
+M5485BFE_config \
+M5485CFE_config \
+M5485DFE_config \
+M5485EFE_config \
+M5485FFE_config \
+M5485GFE_config \
+M5485HFE_config :	unconfig
+	@case "$@" in \
+	M5485AFE_config)	BOOT=2;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
+	M5485BFE_config)	BOOT=2;CODE=16;VID=0;USB=0;RAM=64;RAM1=0;; \
+	M5485CFE_config)	BOOT=2;CODE=16;VID=1;USB=1;RAM=64;RAM1=0;; \
+	M5485DFE_config)	BOOT=2;CODE=0;VID=0;USB=1;RAM=64;RAM1=0;; \
+	M5485EFE_config)	BOOT=2;CODE=0;VID=1;USB=1;RAM=64;RAM1=0;; \
+	M5485FFE_config)	BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
+	M5485GFE_config)	BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
+	M5485HFE_config)	BOOT=2;CODE=;VID=1;USB=0;RAM=64;RAM1=0;; \
+	esac; \
+	>include/config.h ; \
+	echo "#define CFG_BUSCLK	100000000" > $(obj)include/config.h ; \
+	echo "#define CFG_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
+	echo "#define CFG_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
+	if [ "$${RAM1}" != "0" ] ; then \
+		echo "#define CFG_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
+	fi; \
+	if [ "$${CODE}" != "0" ] ; then \
+		echo "#define CFG_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
+	fi; \
+	if [ "$${VID}" == "1" ] ; then \
+		echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
+	fi; \
+	if [ "$${USB}" == "1" ] ; then \
+		echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
+	fi
+	@$(MKCONFIG) -a M5485EVB m68k mcf547x_8x m548xevb freescale
+
 #########################################################################
 ## MPC83xx Systems
 #########################################################################
diff --git a/README b/README
index 1f92047..463bbd0 100644
--- a/README
+++ b/README
@@ -136,8 +136,10 @@ Directory Hierarchy:
   - i386	Files specific to i386 CPUs
   - ixp		Files specific to Intel XScale IXP CPUs
   - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
+  - mcf5227x	Files specific to Freescale ColdFire MCF5227x CPUs
   - mcf532x	Files specific to Freescale ColdFire MCF5329 CPUs
   - mcf5445x	Files specific to Freescale ColdFire MCF5445x CPUs
+  - mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
   - mips	Files specific to MIPS CPUs
   - mpc5xx	Files specific to Freescale MPC5xx  CPUs
   - mpc5xxx	Files specific to Freescale MPC5xxx CPUs
diff --git a/board/freescale/m52277evb/Makefile b/board/freescale/m52277evb/Makefile
new file mode 100644
index 0000000..981763d
--- /dev/null
+++ b/board/freescale/m52277evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk
new file mode 100644
index 0000000..ce014ed
--- /dev/null
+++ b/board/freescale/m52277evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
new file mode 100644
index 0000000..98424c8
--- /dev/null
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M52277 EVB\n");
+	return 0;
+};
+
+long int initdram(int board_type)
+{
+	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CFG_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	sdram->sdcs0 = (CFG_SDRAM_BASE | i);
+
+	sdram->sdcfg1 = CFG_SDRAM_CFG1;
+	sdram->sdcfg2 = CFG_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->sdcr = CFG_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	/*sdram->sdmr = CFG_SDRAM_EMOD; */
+	sdram->sdmr = CFG_SDRAM_MODE;
+
+	udelay(1000);
+
+	/* Issue PALL */
+	sdram->sdcr = CFG_SDRAM_CTRL | 2;
+
+	/* Perform two refresh cycles */
+	sdram->sdcr = CFG_SDRAM_CTRL | 4;
+	sdram->sdcr = CFG_SDRAM_CTRL | 4;
+
+	sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+
+	udelay(100);
+
+	return (dramsize);
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds
new file mode 100644
index 0000000..9125bfc
--- /dev/null
+++ b/board/freescale/m52277evb/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf5227x/start.o	(.text)
+    cpu/mcf5227x/libmcf5227x.a	(.text)
+    lib_m68k/libm68k.a		(.text)
+    lib_generic/libgeneric.a	(.text)
+    common/cmd_mem.o		(.text)
+    common/main.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index fefb42e..344a614 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -63,10 +63,10 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
 		nand_baseaddr |= CLR_ALE;
 		break;
 	case NAND_CTL_SETWP:
-		fbcs->csmr2 |= CSMR_WP;
+		fbcs->csmr2 |= FBCS_CSMR_WP;
 		break;
 	case NAND_CTL_CLRWP:
-		fbcs->csmr2 &= ~CSMR_WP;
+		fbcs->csmr2 &= ~FBCS_CSMR_WP;
 		break;
 	}
 	this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
diff --git a/board/freescale/m5373evb/Makefile b/board/freescale/m5373evb/Makefile
new file mode 100644
index 0000000..ab0f11e
--- /dev/null
+++ b/board/freescale/m5373evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o mii.o nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/m5373evb/config.mk b/board/freescale/m5373evb/config.mk
new file mode 100644
index 0000000..ce014ed
--- /dev/null
+++ b/board/freescale/m5373evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
new file mode 100644
index 0000000..26b87b9
--- /dev/null
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5373 EVB\n");
+	return 0;
+};
+
+long int initdram(int board_type)
+{
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CFG_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	sdram->cs0 = (CFG_SDRAM_BASE | i);
+	sdram->cfg1 = CFG_SDRAM_CFG1;
+	sdram->cfg2 = CFG_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->ctrl = CFG_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	sdram->mode = CFG_SDRAM_EMOD;
+	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+
+	sdram->mode = CFG_SDRAM_MODE;
+
+	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/board/freescale/m5373evb/mii.c b/board/freescale/m5373evb/mii.c
new file mode 100644
index 0000000..8f6abf3
--- /dev/null
+++ b/board/freescale/m5373evb/mii.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+		gpio->par_feci2c |=
+		    GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
+	} else {
+		gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		gpio->par_feci2c &=
+		    ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+	}
+	return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970		0x78100000	/* LXT970 */
+#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
+#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
+#define PHY_ID_QS6612		0x01814400	/* QS6612 */
+#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
+#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
+#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
+#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
+#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */
+
+#define STR_ID_LXT970		"LXT970"
+#define STR_ID_LXT971		"LXT971"
+#define STR_ID_82555		"Intel82555"
+#define STR_ID_QS6612		"QS6612"
+#define STR_ID_AMD79C784	"AMD79C784"
+#define STR_ID_LSI80225		"LSI80225"
+#define STR_ID_LSI80225B	"LSI80225/B"
+#define STR_ID_DP83848VV	"N83848"
+#define STR_ID_DP83849		"N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+	volatile fec_t *fecp = (fec_t *) (info->miibase);
+	int i;
+
+	fecp->ecr = FEC_ECR_RESET;
+	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+		udelay(1);
+	}
+	if (i == FEC_RESET_DELAY) {
+		printf("FEC_RESET_DELAY timeout\n");
+	}
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+	struct fec_info_s *info;
+	struct eth_device *dev;
+	volatile fec_t *ep;
+	uint mii_reply;
+	int j = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	ep = (fec_t *) info->miibase;
+
+	ep->mmfr = mii_cmd;	/* command to phy */
+
+	/* wait for mii complete */
+	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+		udelay(1);
+		j++;
+	}
+	if (j >= MCFFEC_TOUT_LOOP) {
+		printf("MII not complete\n");
+		return -1;
+	}
+
+	mii_reply = ep->mmfr;	/* result from phy */
+	ep->eir = FEC_EIR_MII;	/* clear MII complete */
+#ifdef ET_DEBUG
+	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+	return (mii_reply & 0xffff);	/* data read from phy */
+}
+#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+	struct fec_info_s *info = dev->priv;
+	int phyaddr, pass;
+	uint phyno, phytype;
+
+	if (info->phyname_init)
+		return info->phy_addr;
+
+	phyaddr = -1;		/* didn't find a PHY yet */
+	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+		if (pass > 1) {
+			/* PHY may need more time to recover from reset.
+			 * The LXT970 needs 50ms typical, no maximum is
+			 * specified, so wait 10ms before try again.
+			 * With 11 passes this gives it 100ms to wake up.
+			 */
+			udelay(10000);	/* wait 10ms */
+		}
+
+		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+			printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+			if (phytype != 0xffff) {
+				phyaddr = phyno;
+				phytype <<= 16;
+				phytype |=
+				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_DP83848VV:
+					strcpy(info->phy_name,
+					       STR_ID_DP83848VV);
+					info->phyname_init = 1;
+					break;
+				default:
+					strcpy(info->phy_name, "unknown");
+					info->phyname_init = 1;
+					break;
+				}
+
+#ifdef ET_DEBUG
+				printf("PHY @ 0x%x pass %d type ", phyno, pass);
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_DP83848VV:
+					printf(STR_ID_DP83848VV);
+					break;
+				default:
+					printf("0x%08x\n", phytype);
+					break;
+				}
+#endif
+			}
+		}
+	}
+	if (phyaddr < 0)
+		printf("No PHY device found.\n");
+
+	return phyaddr;
+}
+#endif				/* CFG_DISCOVER_PHY */
+
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+	volatile fec_t *fecp;
+	struct fec_info_s *info;
+	struct eth_device *dev;
+	int miispd = 0, i = 0;
+	u16 autoneg = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	fecp = (fec_t *) info->miibase;
+
+	fecpin_setclear(dev, 1);
+
+	mii_reset(info);
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	/* Set MII speed */
+	miispd = (gd->bus_clk / 1000000) / 5;
+	fecp->mscr = miispd << 1;
+
+	info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+	while (i < MCFFEC_TOUT_LOOP) {
+		autoneg = 0;
+		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+		i++;
+
+		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+			break;
+
+		udelay(500);
+	}
+	if (i >= MCFFEC_TOUT_LOOP) {
+		printf("Auto Negotiation not complete\n");
+	}
+
+	/* adapt to the half/full speed settings */
+	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ *	  no PHY connected...
+ *	  For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ *	  Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+		       unsigned short *value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+	rdreg = mii_send(mk_mii_read(addr, reg));
+
+	*value = rdreg;
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", *value);
+#endif
+
+	return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+			unsigned short value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+	rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", value);
+#endif
+
+	return 0;
+}
+
+#endif				/* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
new file mode 100644
index 0000000..344a614
--- /dev/null
+++ b/board/freescale/m5373evb/nand.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+#define SET_CLE		0x10
+#define CLR_CLE		~SET_CLE
+#define SET_ALE		0x08
+#define CLR_ALE		~SET_ALE
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	u32 nand_baseaddr = (u32) this->IO_ADDR_W;
+
+	switch (cmd) {
+	case NAND_CTL_SETNCE:
+	case NAND_CTL_CLRNCE:
+		break;
+	case NAND_CTL_SETCLE:
+		nand_baseaddr |= SET_CLE;
+		break;
+	case NAND_CTL_CLRCLE:
+		nand_baseaddr &= CLR_CLE;
+		break;
+	case NAND_CTL_SETALE:
+		nand_baseaddr |= SET_ALE;
+		break;
+	case NAND_CTL_CLRALE:
+		nand_baseaddr |= CLR_ALE;
+		break;
+	case NAND_CTL_SETWP:
+		fbcs->csmr2 |= FBCS_CSMR_WP;
+		break;
+	case NAND_CTL_CLRWP:
+		fbcs->csmr2 &= ~FBCS_CSMR_WP;
+		break;
+	}
+	this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
+}
+
+static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	*((volatile u8 *)(this->IO_ADDR_W)) = byte;
+}
+
+static u8 nand_read_byte(struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	return (u8) (*((volatile u8 *)this->IO_ADDR_R));
+}
+
+static int nand_dev_ready(struct mtd_info *mtdinfo)
+{
+	return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
+
+	/* set up pin configuration */
+	gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
+	gpio->pddr_timer |= 0x08;
+	gpio->ppd_timer |= 0x08;
+	gpio->pclrr_timer = 0;
+	gpio->podr_timer = 0;
+
+	nand->chip_delay = 50;
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->hwcontrol = nand_hwcontrol;
+	nand->read_byte = nand_read_byte;
+	nand->write_byte = nand_write_byte;
+	nand->dev_ready = nand_dev_ready;
+
+	return 0;
+}
+#endif
diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds
new file mode 100644
index 0000000..9b994a0
--- /dev/null
+++ b/board/freescale/m5373evb/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf532x/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    lib_m68k/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/freescale/m547xevb/Makefile b/board/freescale/m547xevb/Makefile
new file mode 100644
index 0000000..74c2528
--- /dev/null
+++ b/board/freescale/m547xevb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o mii.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/m547xevb/config.mk b/board/freescale/m547xevb/config.mk
new file mode 100644
index 0000000..fa66b75
--- /dev/null
+++ b/board/freescale/m547xevb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFF800000
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
new file mode 100644
index 0000000..0286084
--- /dev/null
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <pci.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5475 EVB\n");
+	return 0;
+};
+
+long int initdram(int board_type)
+{
+	volatile siu_t *siu = (siu_t *) (MMAP_SIU);
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	siu->drv = CFG_SDRAM_DRVSTRENGTH;
+
+	dramsize = CFG_DRAMSZ * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+	siu->cs0cfg = (CFG_SDRAM_BASE | i);
+
+#ifdef CFG_DRAMSZ1
+	temp = CFG_DRAMSZ1 * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (temp == (1 << i))
+			break;
+	}
+	i--;
+	dramsize += temp;
+	siu->cs1cfg = ((CFG_SDRAM_BASE + temp) | i);
+#endif
+
+	sdram->cfg1 = CFG_SDRAM_CFG1;
+	sdram->cfg2 = CFG_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->ctrl = CFG_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	sdram->mode = CFG_SDRAM_EMOD;
+	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+
+	sdram->mode = CFG_SDRAM_MODE;
+
+	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf547x_8x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+	pci_mcf547x_8x_init(&hose);
+}
+#endif				/* CONFIG_PCI */
diff --git a/board/freescale/m547xevb/mii.c b/board/freescale/m547xevb/mii.c
new file mode 100644
index 0000000..5b2683b
--- /dev/null
+++ b/board/freescale/m547xevb/mii.c
@@ -0,0 +1,322 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+
+#include <asm/immap.h>
+#include <asm/fec.h>
+#include <asm/fsl_mcdmafec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
+
+	if (setclear) {
+		if (info->iobase == CFG_FEC0_IOBASE)
+			gpio->par_feci2cirq |= 0xF000;
+		else
+			gpio->par_feci2cirq |= 0x0FC0;
+	} else {
+		if (info->iobase == CFG_FEC0_IOBASE)
+			gpio->par_feci2cirq &= 0x0FFF;
+		else
+			gpio->par_feci2cirq &= 0xF03F;
+	}
+	return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970		0x78100000	/* LXT970 */
+#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
+#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
+#define PHY_ID_QS6612		0x01814400	/* QS6612 */
+#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
+#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
+#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
+#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
+#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */
+#define PHY_ID_BCM5222		0x00406322	/* Broadcom 5222 */
+
+#define STR_ID_LXT970		"LXT970"
+#define STR_ID_LXT971		"LXT971"
+#define STR_ID_82555		"Intel82555"
+#define STR_ID_QS6612		"QS6612"
+#define STR_ID_AMD79C784	"AMD79C784"
+#define STR_ID_LSI80225		"LSI80225"
+#define STR_ID_LSI80225B	"LSI80225/B"
+#define STR_ID_DP83848VV	"N83848"
+#define STR_ID_DP83849		"N83849"
+#define STR_ID_BCM5222		"BCM5222"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_dma *info)
+{
+	volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
+	int i;
+
+	fecp->ecr = FEC_ECR_RESET;
+	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+		udelay(1);
+	}
+	if (i == FEC_RESET_DELAY) {
+		printf("FEC_RESET_DELAY timeout\n");
+	}
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+	struct fec_info_dma *info;
+	struct eth_device *dev;
+	volatile fecdma_t *ep;
+	uint mii_reply;
+	int j = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	ep = (fecdma_t *) info->miibase;
+
+	ep->mmfr = mii_cmd;	/* command to phy */
+
+	/* wait for mii complete */
+	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+		udelay(1);
+		j++;
+	}
+	if (j >= MCFFEC_TOUT_LOOP) {
+		printf("MII not complete\n");
+		return -1;
+	}
+
+	mii_reply = ep->mmfr;	/* result from phy */
+	ep->eir = FEC_EIR_MII;	/* clear MII complete */
+#ifdef ET_DEBUG
+	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+	return (mii_reply & 0xffff);	/* data read from phy */
+}
+#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+	struct fec_info_dma *info = dev->priv;
+	int phyaddr, pass, temp;
+	uint phyno, phytype;
+
+	if (info->phyname_init) {
+		return info->phy_addr;
+	}
+
+	phyaddr = -1;		/* didn't find a PHY yet */
+	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+		if (pass > 1) {
+			/* PHY may need more time to recover from reset.
+			 * The LXT970 needs 50ms typical, no maximum is
+			 * specified, so wait 10ms before try again.
+			 * With 11 passes this gives it 100ms to wake up.
+			 */
+			udelay(10000);	/* wait 10ms */
+		}
+
+		temp = 0;
+		if (info->index > 0) {
+			/* Some phy have multiple address, to solve the issue
+			   where phyno keeps starting from 0, check the
+			   previous phy address if both miibase are the same. */
+			if (info->miibase == (info->next)->miibase) {
+				temp = (info->next)->phy_addr + 1;
+			}
+		}
+
+		for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
+
+			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+			printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+			if (phytype != 0xffff) {
+				phyaddr = phyno;
+				phytype <<= 16;
+				phytype |=
+				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_BCM5222:
+					strcpy(info->phy_name, STR_ID_BCM5222);
+					info->phyname_init = 1;
+					break;
+				default:
+					strcpy(info->phy_name, "unknown");
+					info->phyname_init = 1;
+					break;
+				}
+
+#ifdef ET_DEBUG
+				printf("PHY @ 0x%x pass %d type ", phyno, pass);
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_BCM5222:
+					printf(STR_ID_BCM5222);
+					break;
+				default:
+					printf("0x%08x\n", phytype);
+					break;
+				}
+#endif
+			}
+		}
+	}
+	if (phyaddr < 0)
+		printf("No PHY device found.\n");
+
+	return phyaddr;
+}
+#endif				/* CFG_DISCOVER_PHY */
+
+void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
+
+void __mii_init(void)
+{
+	volatile fecdma_t *fecp;
+	struct fec_info_dma *info;
+	struct eth_device *dev;
+	int miispd = 0, i = 0;
+	u16 autoneg = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	fecp = (fecdma_t *) info->miibase;
+
+	fecpin_setclear(dev, 1);
+
+	mii_reset(info);
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	/* Set MII speed */
+	miispd = (gd->bus_clk / 1000000) / 5;
+	fecp->mscr = miispd << 1;
+
+	info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+	while (i < MCFFEC_TOUT_LOOP) {
+		autoneg = 0;
+		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+		i++;
+
+		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+			break;
+
+		udelay(500);
+	}
+	if (i >= MCFFEC_TOUT_LOOP) {
+		printf("Auto Negotiation not complete\n");
+	}
+
+	/* adapt to the half/full speed settings */
+	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ *	  no PHY connected...
+ *	  For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ *	  Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+		       unsigned short *value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+	rdreg = mii_send(mk_mii_read(addr, reg));
+
+	*value = rdreg;
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", *value);
+#endif
+
+	return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+			unsigned short value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+	rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", value);
+#endif
+
+	return 0;
+}
+
+#endif				/* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds
new file mode 100644
index 0000000..c10472a
--- /dev/null
+++ b/board/freescale/m547xevb/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf547x_8x/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    lib_m68k/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/freescale/m548xevb/Makefile b/board/freescale/m548xevb/Makefile
new file mode 100644
index 0000000..74c2528
--- /dev/null
+++ b/board/freescale/m548xevb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o mii.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/m548xevb/config.mk b/board/freescale/m548xevb/config.mk
new file mode 100644
index 0000000..fa66b75
--- /dev/null
+++ b/board/freescale/m548xevb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFF800000
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
new file mode 100644
index 0000000..0372807
--- /dev/null
+++ b/board/freescale/m548xevb/m548xevb.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <pci.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5485 EVB\n");
+	return 0;
+};
+
+long int initdram(int board_type)
+{
+	volatile siu_t *siu = (siu_t *) (MMAP_SIU);
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	siu->drv = CFG_SDRAM_DRVSTRENGTH;
+
+	dramsize = CFG_DRAMSZ * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+	siu->cs0cfg = (CFG_SDRAM_BASE | i);
+
+#ifdef CFG_DRAMSZ1
+	temp = CFG_DRAMSZ1 * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (temp == (1 << i))
+			break;
+	}
+	i--;
+	dramsize += temp;
+	siu->cs1cfg = ((CFG_SDRAM_BASE + temp) | i);
+#endif
+
+	sdram->cfg1 = CFG_SDRAM_CFG1;
+	sdram->cfg2 = CFG_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->ctrl = CFG_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	sdram->mode = CFG_SDRAM_EMOD;
+	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+
+	sdram->mode = CFG_SDRAM_MODE;
+
+	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf547x_8x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+	pci_mcf547x_8x_init(&hose);
+}
+#endif				/* CONFIG_PCI */
diff --git a/board/freescale/m548xevb/mii.c b/board/freescale/m548xevb/mii.c
new file mode 100644
index 0000000..5b2683b
--- /dev/null
+++ b/board/freescale/m548xevb/mii.c
@@ -0,0 +1,322 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+
+#include <asm/immap.h>
+#include <asm/fec.h>
+#include <asm/fsl_mcdmafec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
+
+	if (setclear) {
+		if (info->iobase == CFG_FEC0_IOBASE)
+			gpio->par_feci2cirq |= 0xF000;
+		else
+			gpio->par_feci2cirq |= 0x0FC0;
+	} else {
+		if (info->iobase == CFG_FEC0_IOBASE)
+			gpio->par_feci2cirq &= 0x0FFF;
+		else
+			gpio->par_feci2cirq &= 0xF03F;
+	}
+	return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970		0x78100000	/* LXT970 */
+#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
+#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
+#define PHY_ID_QS6612		0x01814400	/* QS6612 */
+#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
+#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
+#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
+#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
+#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */
+#define PHY_ID_BCM5222		0x00406322	/* Broadcom 5222 */
+
+#define STR_ID_LXT970		"LXT970"
+#define STR_ID_LXT971		"LXT971"
+#define STR_ID_82555		"Intel82555"
+#define STR_ID_QS6612		"QS6612"
+#define STR_ID_AMD79C784	"AMD79C784"
+#define STR_ID_LSI80225		"LSI80225"
+#define STR_ID_LSI80225B	"LSI80225/B"
+#define STR_ID_DP83848VV	"N83848"
+#define STR_ID_DP83849		"N83849"
+#define STR_ID_BCM5222		"BCM5222"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_dma *info)
+{
+	volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
+	int i;
+
+	fecp->ecr = FEC_ECR_RESET;
+	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+		udelay(1);
+	}
+	if (i == FEC_RESET_DELAY) {
+		printf("FEC_RESET_DELAY timeout\n");
+	}
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+	struct fec_info_dma *info;
+	struct eth_device *dev;
+	volatile fecdma_t *ep;
+	uint mii_reply;
+	int j = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	ep = (fecdma_t *) info->miibase;
+
+	ep->mmfr = mii_cmd;	/* command to phy */
+
+	/* wait for mii complete */
+	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+		udelay(1);
+		j++;
+	}
+	if (j >= MCFFEC_TOUT_LOOP) {
+		printf("MII not complete\n");
+		return -1;
+	}
+
+	mii_reply = ep->mmfr;	/* result from phy */
+	ep->eir = FEC_EIR_MII;	/* clear MII complete */
+#ifdef ET_DEBUG
+	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+	return (mii_reply & 0xffff);	/* data read from phy */
+}
+#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+	struct fec_info_dma *info = dev->priv;
+	int phyaddr, pass, temp;
+	uint phyno, phytype;
+
+	if (info->phyname_init) {
+		return info->phy_addr;
+	}
+
+	phyaddr = -1;		/* didn't find a PHY yet */
+	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+		if (pass > 1) {
+			/* PHY may need more time to recover from reset.
+			 * The LXT970 needs 50ms typical, no maximum is
+			 * specified, so wait 10ms before try again.
+			 * With 11 passes this gives it 100ms to wake up.
+			 */
+			udelay(10000);	/* wait 10ms */
+		}
+
+		temp = 0;
+		if (info->index > 0) {
+			/* Some phy have multiple address, to solve the issue
+			   where phyno keeps starting from 0, check the
+			   previous phy address if both miibase are the same. */
+			if (info->miibase == (info->next)->miibase) {
+				temp = (info->next)->phy_addr + 1;
+			}
+		}
+
+		for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
+
+			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+			printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+			if (phytype != 0xffff) {
+				phyaddr = phyno;
+				phytype <<= 16;
+				phytype |=
+				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_BCM5222:
+					strcpy(info->phy_name, STR_ID_BCM5222);
+					info->phyname_init = 1;
+					break;
+				default:
+					strcpy(info->phy_name, "unknown");
+					info->phyname_init = 1;
+					break;
+				}
+
+#ifdef ET_DEBUG
+				printf("PHY @ 0x%x pass %d type ", phyno, pass);
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_BCM5222:
+					printf(STR_ID_BCM5222);
+					break;
+				default:
+					printf("0x%08x\n", phytype);
+					break;
+				}
+#endif
+			}
+		}
+	}
+	if (phyaddr < 0)
+		printf("No PHY device found.\n");
+
+	return phyaddr;
+}
+#endif				/* CFG_DISCOVER_PHY */
+
+void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
+
+void __mii_init(void)
+{
+	volatile fecdma_t *fecp;
+	struct fec_info_dma *info;
+	struct eth_device *dev;
+	int miispd = 0, i = 0;
+	u16 autoneg = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	fecp = (fecdma_t *) info->miibase;
+
+	fecpin_setclear(dev, 1);
+
+	mii_reset(info);
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	/* Set MII speed */
+	miispd = (gd->bus_clk / 1000000) / 5;
+	fecp->mscr = miispd << 1;
+
+	info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+	while (i < MCFFEC_TOUT_LOOP) {
+		autoneg = 0;
+		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+		i++;
+
+		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+			break;
+
+		udelay(500);
+	}
+	if (i >= MCFFEC_TOUT_LOOP) {
+		printf("Auto Negotiation not complete\n");
+	}
+
+	/* adapt to the half/full speed settings */
+	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ *	  no PHY connected...
+ *	  For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ *	  Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+		       unsigned short *value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+	rdreg = mii_send(mk_mii_read(addr, reg));
+
+	*value = rdreg;
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", *value);
+#endif
+
+	return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+			unsigned short value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+	rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", value);
+#endif
+
+	return 0;
+}
+
+#endif				/* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds
new file mode 100644
index 0000000..c10472a
--- /dev/null
+++ b/board/freescale/m548xevb/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf547x_8x/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    lib_m68k/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile
new file mode 100644
index 0000000..d0e9b45
--- /dev/null
+++ b/cpu/mcf5227x/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# CFLAGS += -DET_DEBUG
+
+LIB	= lib$(CPU).a
+
+START	= start.o
+COBJS	= cpu.o speed.o cpu_init.o interrupts.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/mcf5227x/config.mk b/cpu/mcf5227x/config.mk
new file mode 100644
index 0000000..8d60fd6
--- /dev/null
+++ b/cpu/mcf5227x/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+PLATFORM_CPPFLAGS += -mcpu=5208 -fPIC
+else
+PLATFORM_CPPFLAGS += -m5307 -fPIC
+endif
diff --git a/cpu/mcf5227x/cpu.c b/cpu/mcf5227x/cpu.c
new file mode 100644
index 0000000..5792a1c
--- /dev/null
+++ b/cpu/mcf5227x/cpu.c
@@ -0,0 +1,75 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+	volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+	udelay(1000);
+	rcm->rcr |= RCM_RCR_SOFTRST;
+
+	/* we don't return! */
+	return 0;
+};
+
+int checkcpu(void)
+{
+	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	u16 msk;
+	u16 id = 0;
+	u8 ver;
+
+	puts("CPU:   ");
+	msk = (ccm->cir >> 6);
+	ver = (ccm->cir & 0x003f);
+	switch (msk) {
+	case 0x6c:
+		id = 52277;
+		break;
+	}
+
+	if (id) {
+		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
+		       ver);
+		printf("       CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n",
+		       (int)(gd->cpu_clk / 1000000),
+		       (int)(gd->bus_clk / 1000000),
+		       (int)(gd->flb_clk / 1000000));
+		printf("       INP CLK %d Mhz VCO CLK %d Mhz\n",
+		       (int)(gd->inp_clk / 1000000),
+		       (int)(gd->vco_clk / 1000000));
+	}
+
+	return 0;
+}
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
new file mode 100644
index 0000000..71b053d
--- /dev/null
+++ b/cpu/mcf5227x/cpu_init.c
@@ -0,0 +1,146 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+
+#include <asm/immap.h>
+#include <asm/rtc.h>
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+
+	/* Workaround, must place before fbcs */
+	pll->psr = 0x12;
+
+	scm1->mpr = 0x77777777;
+	scm1->pacra = 0;
+	scm1->pacrb = 0;
+	scm1->pacrc = 0;
+	scm1->pacrd = 0;
+	scm1->pacre = 0;
+	scm1->pacrf = 0;
+	scm1->pacrg = 0;
+	scm1->pacri = 0;
+
+#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
+	fbcs->csar0 = CFG_CS0_BASE;
+	fbcs->cscr0 = CFG_CS0_CTRL;
+	fbcs->csmr0 = CFG_CS0_MASK;
+#endif
+
+#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+	fbcs->csar1 = CFG_CS1_BASE;
+	fbcs->cscr1 = CFG_CS1_CTRL;
+	fbcs->csmr1 = CFG_CS1_MASK;
+#endif
+
+#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
+	fbcs->csar2 = CFG_CS2_BASE;
+	fbcs->cscr2 = CFG_CS2_CTRL;
+	fbcs->csmr2 = CFG_CS2_MASK;
+#endif
+
+#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
+	fbcs->csar3 = CFG_CS3_BASE;
+	fbcs->cscr3 = CFG_CS3_CTRL;
+	fbcs->csmr3 = CFG_CS3_MASK;
+#endif
+
+#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
+	fbcs->csar4 = CFG_CS4_BASE;
+	fbcs->cscr4 = CFG_CS4_CTRL;
+	fbcs->csmr4 = CFG_CS4_MASK;
+#endif
+
+#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
+	fbcs->csar5 = CFG_CS5_BASE;
+	fbcs->cscr5 = CFG_CS5_CTRL;
+	fbcs->csmr5 = CFG_CS5_MASK;
+#endif
+
+#ifdef CONFIG_FSL_I2C
+	gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
+#endif
+
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+#ifdef CONFIG_MCFTMR
+	volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
+	volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+	u32 oscillator = CFG_RTC_OSCILLATOR;
+
+	rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
+	rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
+#endif
+
+	return (0);
+}
+
+void uart_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (CFG_UART_PORT) {
+	case 0:
+		gpio->par_uart &=
+		    (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);
+		gpio->par_uart |=
+		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		break;
+	case 1:
+		gpio->par_uart &=
+		    (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK);
+		gpio->par_uart |=
+		    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+		break;
+	case 2:
+		gpio->par_dspi &=
+		    (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK);
+		gpio->par_dspi =
+		    (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
+		break;
+	}
+}
diff --git a/cpu/mcf5227x/interrupts.c b/cpu/mcf5227x/interrupts.c
new file mode 100644
index 0000000..9572a7b
--- /dev/null
+++ b/cpu/mcf5227x/interrupts.c
@@ -0,0 +1,52 @@
+/*
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <asm/immap.h>
+
+int interrupt_init(void)
+{
+	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+	/* Make sure all interrupts are disabled */
+	intp->imrh0 |= 0xFFFFFFFF;
+	intp->imrl0 |= 0xFFFFFFFF;
+
+	enable_interrupts();
+	return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+	intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+	intp->imrh0 &= ~CFG_TMRINTR_MASK;
+}
+#endif
diff --git a/cpu/mcf5227x/speed.c b/cpu/mcf5227x/speed.c
new file mode 100644
index 0000000..78c946f
--- /dev/null
+++ b/cpu/mcf5227x/speed.c
@@ -0,0 +1,120 @@
+/*
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Low Power Divider specifications
+ */
+#define CLOCK_LPD_MIN		(1 << 0)	/* Divider (decoded) */
+#define CLOCK_LPD_MAX		(1 << 15)	/* Divider (decoded) */
+
+#define CLOCK_PLL_FVCO_MAX	540000000
+#define CLOCK_PLL_FVCO_MIN	300000000
+
+#define CLOCK_PLL_FSYS_MAX	266666666
+#define CLOCK_PLL_FSYS_MIN	100000000
+#define MHZ			1000000
+
+void clock_enter_limp(int lpdiv)
+{
+	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+	int i, j;
+
+	/* Check bounds of divider */
+	if (lpdiv < CLOCK_LPD_MIN)
+		lpdiv = CLOCK_LPD_MIN;
+	if (lpdiv > CLOCK_LPD_MAX)
+		lpdiv = CLOCK_LPD_MAX;
+
+	/* Round divider down to nearest power of two */
+	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
+
+	/* Apply the divider to the system clock */
+	ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+
+	/* Enable Limp Mode */
+	ccm->misccr |= CCM_MISCCR_LIMP;
+}
+
+/*
+ * brief   Exit Limp mode
+ * warning The PLL should be set and locked prior to exiting Limp mode
+ */
+void clock_exit_limp(void)
+{
+	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+
+	/* Exit Limp mode */
+	ccm->misccr &= ~CCM_MISCCR_LIMP;
+
+	/* Wait for the PLL to lock */
+	while (!(pll->psr & PLL_PSR_LOCK)) ;
+}
+
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+
+	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+	int vco, temp, pcrvalue, pfdr;
+	u8 bootmode;
+
+	bootmode = (ccm->ccr & 0x000C) >> 2;
+
+	pcrvalue = pll->pcr & 0xFF0F0FFF;
+	pfdr = pcrvalue >> 24;
+
+	if (pfdr != 0x1E) {
+		/* serial mode */
+	} else {
+		/* Normal Mode */
+		vco = pfdr * CFG_INPUT_CLKSRC;
+		gd->vco_clk = vco;
+	}
+
+	if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+		/* Limp mode */
+	} else {
+		gd->inp_clk = CFG_INPUT_CLKSRC;	/* Input clock */
+
+		temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
+		gd->cpu_clk = vco / temp;	/* cpu clock */
+
+		temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+		gd->flb_clk = vco / temp;	/* flexbus clock */
+		gd->bus_clk = gd->flb_clk;
+	}
+
+	return (0);
+}
diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
new file mode 100644
index 0000000..0e2db12
--- /dev/null
+++ b/cpu/mcf5227x/start.S
@@ -0,0 +1,356 @@
+/*
+ * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include "version.h"
+
+#ifndef	 CONFIG_IDENT_STRING
+#define	 CONFIG_IDENT_STRING ""
+#endif
+
+/* last three long word reserved for cache status */
+#define ICACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
+#define DCACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
+#define CACR_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
+
+#define _START	_start
+#define _FAULT	_fault
+
+#define SAVE_ALL						\
+	move.w	#0x2700,%sr;		/* disable intrs */	\
+	subl	#60,%sp;		/* space for 15 regs */ \
+	moveml	%d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL						\
+	moveml	%sp@,%d0-%d7/%a0-%a6;				\
+	addl	#60,%sp;		/* space for 15 regs */ \
+	rte;
+
+.text
+/*
+ *	Vector table. This is used for initial platform startup.
+ *	These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+INITSP:		.long	0x00000000	/* Initial SP	*/
+INITPC:		.long	_START	/* Initial PC		*/
+vector02:	.long	_FAULT	/* Access Error		*/
+vector03:	.long	_FAULT	/* Address Error	*/
+vector04:	.long	_FAULT	/* Illegal Instruction	*/
+vector05:	.long	_FAULT	/* Reserved		*/
+vector06:	.long	_FAULT	/* Reserved		*/
+vector07:	.long	_FAULT	/* Reserved		*/
+vector08:	.long	_FAULT	/* Privilege Violation	*/
+vector09:	.long	_FAULT	/* Trace		*/
+vector0A:	.long	_FAULT	/* Unimplemented A-Line	*/
+vector0B:	.long	_FAULT	/* Unimplemented F-Line	*/
+vector0C:	.long	_FAULT	/* Debug Interrupt	*/
+vector0D:	.long	_FAULT	/* Reserved		*/
+vector0E:	.long	_FAULT	/* Format Error		*/
+vector0F:	.long	_FAULT	/* Unitialized Int.	*/
+
+/* Reserved */
+vector10_17:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18:	.long	_FAULT	/* Spurious Interrupt	*/
+vector19:	.long	_FAULT	/* Autovector Level 1	*/
+vector1A:	.long	_FAULT	/* Autovector Level 2	*/
+vector1B:	.long	_FAULT	/* Autovector Level 3	*/
+vector1C:	.long	_FAULT	/* Autovector Level 4	*/
+vector1D:	.long	_FAULT	/* Autovector Level 5	*/
+vector1E:	.long	_FAULT	/* Autovector Level 6	*/
+vector1F:	.long	_FAULT	/* Autovector Level 7	*/
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved	*/
+vector30_3F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+	.text
+
+	.globl	_start
+_start:
+	nop
+	nop
+	move.w #0x2700,%sr		/* Mask off Interrupt */
+
+	/* Set vector base register at the beginning of the Flash */
+	move.l	#CFG_FLASH_BASE, %d0
+	movec	%d0, %VBR
+
+	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	/* initialize general use internal ram */
+	move.l #0, %d0
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* icache */
+	move.l #(CACR_STATUS), %a3	/* CACR */
+	move.l %d0, (%a1)
+	move.l %d0, (%a2)
+	move.l %d0, (%a3)
+
+	/* invalidate and disable cache */
+	move.l	#0x01000000, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+
+	/* set stackpointer to end of internal ram to get some stackspace for
+	   the first c-code */
+	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+	clr.l %sp@-
+
+	move.l #__got_start, %a5	/* put relocation table address to a5 */
+
+	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
+	bsr board_init_f		/* run low-level board init code (from flash) */
+
+	/* board_init_f() does not return */
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+	link.w %a6,#0
+	move.l 8(%a6), %sp		/* set new stack pointer */
+
+	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l 16(%a6), %a0		/* Save copy of Destination Address */
+
+	move.l #CFG_MONITOR_BASE, %a1
+	move.l #__init_end, %a2
+	move.l %a0, %a3
+
+	/* copy the code to RAM */
+1:
+	move.l (%a1)+, (%a3)+
+	cmp.l  %a1,%a2
+	bgt.s	 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CFG_MONITOR_BASE),%a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CFG_MONITOR_BASE),%d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CFG_MONITOR_BASE),%a1
+	move.l	%a1,%a5			/* * fix got pointer register a5 */
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CFG_MONITOR_BASE),%a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start,%d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l %a0, %a1
+	add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l %a0,-(%sp)		/* dest_addr */
+	move.l %d0,-(%sp)		/* gd */
+	jsr	(%a1)
+
+/*------------------------------------------------------------------------------*/
+/* exception code */
+	.globl _fault
+_fault:
+	jmp _fault
+	.globl	_exc_handler
+
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+	.globl	_int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/*------------------------------------------------------------------------------*/
+/* cache functions */
+	.globl	icache_enable
+icache_enable:
+	move.l	#0x01200000, %d0	/* Invalid cache */
+	movec	%d0, %CACR
+
+	move.l	#(CFG_SDRAM_BASE + 0x1c000), %d0
+	movec	%d0, %ACR0
+
+	move.l	#0x81600610, %d0	/* Enable cache */
+	movec	%d0, %CACR
+
+	move.l	#(ICACHE_STATUS), %a1
+	moveq	#1, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	icache_disable
+icache_disable:
+	move.l	#0x01F00000, %d0	/* Setup cache mask */
+	movec	%d0, %CACR		/* Invalidate icache */
+	clr.l	%d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+
+	move.l	#(ICACHE_STATUS), %a1
+	moveq	#0, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	icache_status
+icache_status:
+	move.l	#(ICACHE_STATUS), %a1
+	move.l	(%a1), %d0
+	rts
+
+	.globl	icache_invalid
+icache_invalid:
+	move.l	#0x80600610, %d0	/* Invalidate icache */
+	movec	%d0, %CACR		/* Enable and invalidate cache */
+	rts
+
+	.globl	dcache_enable
+dcache_enable:
+	move.l	#0x01200000, %d0	/* Invalid cache */
+	movec	%d0, %CACR
+
+	move.l	#0x81300610, %d0
+	movec	%d0, %CACR
+
+	move.l	#(DCACHE_STATUS), %a1
+	moveq	#1, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	dcache_disable
+dcache_disable:
+	move.l	#0x81600610, %d0	/* Setup cache mask */
+	movec	%d0, %CACR		/* Invalidate icache */
+
+	move.l	#(DCACHE_STATUS), %a1
+	moveq	#0, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	dcache_invalid
+dcache_invalid:
+	move.l	#0x81100610, %d0	/* Setup cache mask */
+	movec	%d0, %CACR		/* Enable and invalidate cache */
+	rts
+
+	.globl	dcache_status
+dcache_status:
+	move.l	#(DCACHE_STATUS), %a1
+	move.l	(%a1), %d0
+	rts
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION
+	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii CONFIG_IDENT_STRING, "\0"
diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c
index 89cc8ad..61541ab 100644
--- a/cpu/mcf532x/cpu.c
+++ b/cpu/mcf532x/cpu.c
@@ -64,6 +64,18 @@ int checkcpu(void)
 	case 0x61:
 		id = 5327;
 		break;
+	case 0x65:
+		id = 5373;
+		break;
+	case 0x68:
+		id = 53721;
+		break;
+	case 0x69:
+		id = 5372;
+		break;
+	case 0x6B:
+		id = 5372;
+		break;
 	}
 
 	if (id) {
@@ -84,6 +96,7 @@ void watchdog_reset(void)
 	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
 	wdp->sr = 0x5555;	/* Count register */
+	wdp->sr = 0xAAAA;	/* Count register */
 }
 
 int watchdog_disable(void)
@@ -104,8 +117,11 @@ int watchdog_init(void)
 
 	/* set timeout and enable watchdog */
 	wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
-	wdog_module |= (wdog_module / 8192);
-	wdp->mr = wdog_module;
+#ifdef CONFIG_M5329
+	wdp->mr = (wdog_module / 8192);
+#else
+	wdp->mr = (wdog_module / 4096);
+#endif
 
 	wdp->cr = WTM_WCR_EN;
 	puts("WATCHDOG:enabled\n");
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 6622eee..585216d 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -113,7 +113,6 @@ int cpu_init_r(void)
 #ifdef CONFIG_MCFTMR
 	volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
 	volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
-	u32 oscillator = CFG_RTC_OSCILLATOR;
 
 	rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
 	rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c
index 8ace536..0398469 100644
--- a/cpu/mcf5445x/pci.c
+++ b/cpu/mcf5445x/pci.c
@@ -46,48 +46,18 @@ int pci_##rw##_cfg_##size(struct pci_controller *hose,			\
 	u16 cfg_type = 0;						\
 	addr = ((offset & 0xfc) | cfg_type | (dev)  | 0x80000000);	\
 	out_be32(hose->cfg_addr, addr);					\
-	__asm__ __volatile__("nop");					\
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	\
 	out_be32(hose->cfg_addr, addr & 0x7fffffff);			\
-	__asm__ __volatile__("nop");					\
 	return 0;							\
 }
 
 PCI_OP(read, byte, u8 *, in_8, 3)
 PCI_OP(read, word, u16 *, in_le16, 2)
+PCI_OP(read, dword, u32 *, in_le32, 0)
 PCI_OP(write, byte, u8, out_8, 3)
 PCI_OP(write, word, u16, out_le16, 2)
 PCI_OP(write, dword, u32, out_le32, 0)
 
-int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
-		       int offset, u32 * val)
-{
-	u32 addr;
-	u32 tmpv;
-	u32 mask = 2;		/* word access */
-	/* Read lower 16 bits */
-	addr = ((offset & 0xfc) | (dev) | 0x80000000);
-	out_be32(hose->cfg_addr, addr);
-	__asm__ __volatile__("nop");
-	*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
-	out_be32(hose->cfg_addr, addr & 0x7fffffff);
-	__asm__ __volatile__("nop");
-
-	/* Read upper 16 bits */
-	offset += 2;
-	addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
-	out_be32(hose->cfg_addr, addr);
-	__asm__ __volatile__("nop");
-	tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
-	out_be32(hose->cfg_addr, addr & 0x7fffffff);
-	__asm__ __volatile__("nop");
-
-	/* combine results into dword value */
-	*val = (tmpv << 16) | *val;
-
-	return 0;
-}
-
 void pci_mcf5445x_init(struct pci_controller *hose)
 {
 	volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
@@ -95,7 +65,7 @@ void pci_mcf5445x_init(struct pci_controller *hose)
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	u32 barEn = 0;
 
-	pciarb->acr = 0x001f001f;
+	pciarb->acr = 0x001F001F;
 
 	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
 	   PCIREQ2, PCIGNT2 */
@@ -104,53 +74,58 @@ void pci_mcf5445x_init(struct pci_controller *hose)
 	    GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
 	    GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
 
+	/* Assert reset bit */
+	pci->gscr |= PCI_GSCR_PR;
+
 	pci->tcr1 |= PCI_TCR1_P;
 
 	/* Initiator windows */
-	pci->iw0btar = CFG_PCI_MEM_PHYS;
-	pci->iw1btar = CFG_PCI_IO_PHYS;
-	pci->iw2btar = CFG_PCI_CFG_PHYS;
+	pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
+	pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
+	pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
 
 	pci->iwcr =
 	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
 	    PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
 
+	pci->icr = 0;
+
 	/* Enable bus master and mem access */
-	pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M;
+	pci->scr = PCI_SCR_B | PCI_SCR_M;
 
 	/* Cache line size and master latency */
-	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF);
+	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
 	pci->cr2 = 0;
 
 #ifdef CFG_PCI_BAR0
 	pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
 	pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
-	barEn |= PCI_TCR1_B0E;
+	barEn |= PCI_TCR2_B0E;
 #endif
 #ifdef CFG_PCI_BAR1
 	pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
 	pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
-	barEn |= PCI_TCR1_B1E;
+	barEn |= PCI_TCR2_B1E;
 #endif
 #ifdef CFG_PCI_BAR2
 	pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
 	pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
-	barEn |= PCI_TCR1_B2E;
+	barEn |= PCI_TCR2_B2E;
 #endif
 #ifdef CFG_PCI_BAR3
 	pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
 	pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
-	barEn |= PCI_TCR1_B3E;
+	barEn |= PCI_TCR2_B3E;
 #endif
 #ifdef CFG_PCI_BAR4
 	pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
 	pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
-	barEn |= PCI_TCR1_B4E;
+	barEn |= PCI_TCR2_B4E;
 #endif
 #ifdef CFG_PCI_BAR5
 	pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
 	pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
-	barEn |= PCI_TCR1_B5E;
+	barEn |= PCI_TCR2_B5E;
 #endif
 
 	pci->tcr2 = barEn;
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index 423583d..d64c5af 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -279,14 +279,13 @@ icache_enable:
 	move.l	(%a1), %d1
 
 	move.l	#0x00040100, %d0	/* Invalidate icache */
-	or.l	%d1, %d0
 	movec	%d0, %CACR
 
-	move.l	#(CFG_SDRAM_BASE + 0xc000), %d0	/* Setup icache */
+	move.l	#(CFG_SDRAM_BASE + 0x1c000), %d0	/* Setup icache */
 	movec	%d0, %ACR2
 
-	or.l	#0x00088400, %d1	/* Enable bcache and icache */
-	movec	%d1, %CACR
+	move.l	#0x04088020, %d0	/* Enable bcache and icache */
+	movec	%d0, %CACR
 
 	move.l #(ICACHE_STATUS), %a1
 	moveq	#1, %d0
@@ -298,7 +297,7 @@ icache_disable:
 	move.l #(CACR_STATUS), %a1	/* read CACR Status */
 	move.l	(%a1), %d0
 
-	and.l	#0xFFF77BFF, %d0
+	move.l	#0xFFF77BFF, %d0
 	or.l	#0x00040100, %d0	/* Setup cache mask */
 	movec	%d0, %CACR		/* Invalidate icache */
 	clr.l	%d0
@@ -321,7 +320,7 @@ icache_invalid:
 	move.l #(CACR_STATUS), %a1	/* read CACR Status */
 	move.l	(%a1), %d0
 
-	or.l	#0x00040100, %d0	/* Invalidate icache */
+	move.l	#0x00040100, %d0	/* Invalidate icache */
 	movec	%d0, %CACR		/* Enable and invalidate cache */
 	rts
 
@@ -330,17 +329,11 @@ dcache_enable:
 	move.l #(CACR_STATUS), %a1	/* read CACR Status */
 	move.l	(%a1), %d1
 
-	move.l	#0x01000000, %d0
-	or.l	%d1, %d0
+	move.l	#0x01040100, %d0
 	movec	%d0, %CACR		/* Invalidate dcache */
 
-	move.l  #(CFG_SDRAM_BASE + 0xc000), %d0
-	movec	%d0, %ACR0
-	move.l  #0, %d0
-	movec	%d0, %ACR1
-
-	or.l	#0x80000000, %d1	/* Enable bcache and icache */
-	movec	%d1, %CACR
+	move.l	#0x80088020, %d0	/* Enable bcache and icache */
+	movec	%d0, %CACR
 
 	move.l #(DCACHE_STATUS), %a1
 	moveq	#1, %d0
@@ -369,7 +362,7 @@ dcache_invalid:
 	move.l #(CACR_STATUS), %a1	/* read CACR Status */
 	move.l	(%a1), %d0
 
-	or.l	#0x01000000, %d0	/* Setup cache mask */
+	move.l	#0x81088020, %d0	/* Setup cache mask */
 	movec	%d0, %CACR		/* Enable and invalidate cache */
 	rts
 
diff --git a/cpu/mcf547x_8x/Makefile b/cpu/mcf547x_8x/Makefile
new file mode 100644
index 0000000..e12bef1
--- /dev/null
+++ b/cpu/mcf547x_8x/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# CFLAGS += -DET_DEBUG
+
+LIB	= lib$(CPU).a
+
+START	=
+COBJS	= cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/mcf547x_8x/config.mk b/cpu/mcf547x_8x/config.mk
new file mode 100644
index 0000000..e5f4385
--- /dev/null
+++ b/cpu/mcf547x_8x/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
+PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
+else
+PLATFORM_CPPFLAGS += -m5407 -fPIC
+endif
diff --git a/cpu/mcf547x_8x/cpu.c b/cpu/mcf547x_8x/cpu.c
new file mode 100644
index 0000000..528bca6
--- /dev/null
+++ b/cpu/mcf547x_8x/cpu.c
@@ -0,0 +1,143 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+
+	gptmr->pre = 10;
+	gptmr->cnt = 1;
+
+	/* enable watchdog, set timeout to 0 and wait */
+	gptmr->mode = GPT_TMS_SGPIO;
+	gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE;
+
+	/* we don't return! */
+	return 1;
+};
+
+int checkcpu(void)
+{
+	volatile siu_t *siu = (siu_t *) MMAP_SIU;
+	u16 id = 0;
+
+	puts("CPU:   ");
+
+	switch ((siu->jtagid & 0x000FF000) >> 12) {
+	case 0x0C:
+		id = 5485;
+		break;
+	case 0x0D:
+		id = 5484;
+		break;
+	case 0x0E:
+		id = 5483;
+		break;
+	case 0x0F:
+		id = 5482;
+		break;
+	case 0x10:
+		id = 5481;
+		break;
+	case 0x11:
+		id = 5480;
+		break;
+	case 0x12:
+		id = 5475;
+		break;
+	case 0x13:
+		id = 5474;
+		break;
+	case 0x14:
+		id = 5473;
+		break;
+	case 0x15:
+		id = 5472;
+		break;
+	case 0x16:
+		id = 5471;
+		break;
+	case 0x17:
+		id = 5470;
+		break;
+	}
+
+	if (id) {
+		printf("Freescale MCF%d\n", id);
+		printf("       CPU CLK %d Mhz BUS CLK %d Mhz\n",
+		       (int)(gd->cpu_clk / 1000000),
+		       (int)(gd->bus_clk / 1000000));
+	}
+
+	return 0;
+};
+
+#if defined(CONFIG_HW_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void hw_watchdog_reset(void)
+{
+	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+
+	gptmr->ocpw = 0xa5;
+}
+
+int watchdog_disable(void)
+{
+	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+
+	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
+	gptmr->mode = 0;
+	gptmr->ctrl = 0;
+
+	puts("WATCHDOG:disabled\n");
+
+	return (0);
+}
+
+int watchdog_init(void)
+{
+
+	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+
+	gptmr->pre = CONFIG_WATCHDOG_TIMEOUT;
+	gptmr->cnt = CFG_TIMER_PRESCALER * 1000;
+
+	gptmr->mode = GPT_TMS_SGPIO;
+	gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN;
+	puts("WATCHDOG:enabled\n");
+
+	return (0);
+}
+#endif				/* CONFIG_HW_WATCHDOG */
diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c
new file mode 100644
index 0000000..11154c6
--- /dev/null
+++ b/cpu/mcf547x_8x/cpu_init.c
@@ -0,0 +1,132 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <MCD_dma.h>
+#include <asm/immap.h>
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB;
+
+	xlbarb->adrto = 0x2000;
+	xlbarb->datto = 0x2000;
+	xlbarb->busto = 0x3000;
+
+	xlbarb->cfg = XARB_SR_AT | XARB_SR_DT;
+
+	/* Master Priority Enable */
+	xlbarb->pri = 0;
+	xlbarb->prien = 0xff;
+
+#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
+	fbcs->csar0 = CFG_CS0_BASE;
+	fbcs->cscr0 = CFG_CS0_CTRL;
+	fbcs->csmr0 = CFG_CS0_MASK;
+#endif
+
+#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+	fbcs->csar1 = CFG_CS1_BASE;
+	fbcs->cscr1 = CFG_CS1_CTRL;
+	fbcs->csmr1 = CFG_CS1_MASK;
+#endif
+
+#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
+	fbcs->csar2 = CFG_CS2_BASE;
+	fbcs->cscr2 = CFG_CS2_CTRL;
+	fbcs->csmr2 = CFG_CS2_MASK;
+#endif
+
+#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
+	fbcs->csar3 = CFG_CS3_BASE;
+	fbcs->cscr3 = CFG_CS3_CTRL;
+	fbcs->csmr3 = CFG_CS3_MASK;
+#endif
+
+#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
+	fbcs->csar4 = CFG_CS4_BASE;
+	fbcs->cscr4 = CFG_CS4_CTRL;
+	fbcs->csmr4 = CFG_CS4_MASK;
+#endif
+
+#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
+	fbcs->csar5 = CFG_CS5_BASE;
+	fbcs->cscr5 = CFG_CS5_CTRL;
+	fbcs->csmr5 = CFG_CS5_MASK;
+#endif
+
+#ifdef CONFIG_FSL_I2C
+	gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA;
+#endif
+
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
+	MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
+		    MCD_RELOC_TASKS);
+#endif
+	return (0);
+}
+
+void uart_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile u8 *pscsicr = (u8 *) (CFG_UART_BASE + 0x40);
+
+	/* Setup Ports: */
+	switch (CFG_UART_PORT) {
+	case 0:
+		gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
+		break;
+	case 1:
+		gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
+		break;
+	case 2:
+		gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
+		break;
+	case 3:
+		gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
+		break;
+	}
+
+	*pscsicr &= 0xF8;
+}
diff --git a/cpu/mcf547x_8x/interrupts.c b/cpu/mcf547x_8x/interrupts.c
new file mode 100644
index 0000000..d684ffe
--- /dev/null
+++ b/cpu/mcf547x_8x/interrupts.c
@@ -0,0 +1,50 @@
+/*
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <asm/immap.h>
+
+int interrupt_init(void)
+{
+	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+	/* Make sure all interrupts are disabled */
+	intp->imrh0 |= 0xFFFFFFFF;
+	intp->imrl0 |= 0xFFFFFFFF;
+
+	enable_interrupts();
+
+	return 0;
+}
+
+#if defined(CONFIG_SLTTMR)
+void dtimer_intr_setup(void)
+{
+	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+	intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+	intp->imrh0 &= ~CFG_TMRINTR_MASK;
+}
+#endif
diff --git a/cpu/mcf547x_8x/pci.c b/cpu/mcf547x_8x/pci.c
new file mode 100644
index 0000000..70378b0
--- /dev/null
+++ b/cpu/mcf547x_8x/pci.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI Configuration space access support
+ */
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+#if defined(CONFIG_PCI)
+/* System RAM mapped over PCI */
+#define CFG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CFG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CFG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define cfg_read(val, addr, type, op)		*val = op((type)(addr));
+#define cfg_write(val, addr, type, op)		op((type *)(addr), (val));
+
+#define PCI_OP(rw, size, type, op, mask)				\
+int pci_##rw##_cfg_##size(struct pci_controller *hose,			\
+	pci_dev_t dev, int offset, type val)				\
+{									\
+	u32 addr = 0;							\
+	u16 cfg_type = 0;						\
+	addr = ((offset & 0xfc) | cfg_type | (dev)  | 0x80000000);	\
+	out_be32(hose->cfg_addr, addr);					\
+	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	\
+	__asm__ __volatile__("nop");					\
+	__asm__ __volatile__("nop");					\
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);			\
+	return 0;							\
+}
+
+PCI_OP(read, byte, u8 *, in_8, 3)
+PCI_OP(read, word, u16 *, in_le16, 2)
+PCI_OP(write, byte, u8, out_8, 3)
+PCI_OP(write, word, u16, out_le16, 2)
+PCI_OP(write, dword, u32, out_le32, 0)
+
+int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
+		       int offset, u32 * val)
+{
+	u32 addr;
+	u32 tmpv;
+	u32 mask = 2;		/* word access */
+	/* Read lower 16 bits */
+	addr = ((offset & 0xfc) | (dev) | 0x80000000);
+	out_be32(hose->cfg_addr, addr);
+	*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+	__asm__ __volatile__("nop");
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);
+
+	/* Read upper 16 bits */
+	offset += 2;
+	addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
+	out_be32(hose->cfg_addr, addr);
+	tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+	__asm__ __volatile__("nop");
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);
+
+	/* combine results into dword value */
+	*val = (tmpv << 16) | *val;
+
+	return 0;
+}
+
+void pci_mcf547x_8x_init(struct pci_controller *hose)
+{
+	volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Port configuration */
+	gpio->par_pcibg =
+	    GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
+	    GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
+	    GPIO_PAR_PCIBG_PCIBG4(3);
+	gpio->par_pcibr =
+	    GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
+	    GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
+	    GPIO_PAR_PCIBR_PCIBR4(3);
+
+	/* Assert reset bit */
+	pci->gscr |= PCI_GSCR_PR;
+
+	pci->tcr1 = PCI_TCR1_P;
+
+	/* Initiator windows */
+	pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
+	pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
+	pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
+
+	pci->iwcr =
+	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+	    PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+
+	pci->icr = 0;
+
+	/* Enable bus master and mem access */
+	pci->scr = PCI_SCR_B | PCI_SCR_M;
+
+	/* Cache line size and master latency */
+	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
+	pci->cr2 = 0;
+
+#ifdef CFG_PCI_BAR0
+	pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
+	pci->tbatr0a = CFG_PCI_TBATR0 | PCI_TBATR_EN;
+#endif
+#ifdef CFG_PCI_BAR1
+	pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
+	pci->tbatr1a = CFG_PCI_TBATR1 | PCI_TBATR_EN;
+#endif
+
+	/* Deassert reset bit */
+	pci->gscr &= ~PCI_GSCR_PR;
+	udelay(1000);
+
+	/* Enable PCI bus master support */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
+		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
+
+	pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
+		       CFG_PCI_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
+		       CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 3;
+
+	hose->cfg_addr = &(pci->car);
+	hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
+
+	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
+		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
+		    pci_write_cfg_dword);
+
+	/* Hose scan */
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
+}
+#endif				/* CONFIG_PCI */
diff --git a/cpu/mcf547x_8x/slicetimer.c b/cpu/mcf547x_8x/slicetimer.c
new file mode 100644
index 0000000..494f98f
--- /dev/null
+++ b/cpu/mcf547x_8x/slicetimer.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/timer.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong timestamp;
+
+#if defined(CONFIG_SLTTMR)
+#ifndef CFG_UDELAY_BASE
+#	error	"uDelay base not defined!"
+#endif
+
+#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK)
+#	error	"TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
+#endif
+extern void dtimer_intr_setup(void);
+
+void udelay(unsigned long usec)
+{
+	volatile slt_t *timerp = (slt_t *) (CFG_UDELAY_BASE);
+	u32 now, freq;
+
+	/* 1 us period */
+	freq = CFG_TIMER_PRESCALER;
+
+	timerp->cr = 0;		/* Disable */
+	timerp->tcnt = usec * freq;
+	timerp->cr = SLT_CR_TEN;
+
+	now = timerp->cnt;
+	while (now != 0)
+		now = timerp->cnt;
+
+	timerp->sr |= SLT_SR_ST;
+	timerp->cr = 0;
+}
+
+void dtimer_interrupt(void *not_used)
+{
+	volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE);
+
+	/* check for timer interrupt asserted */
+	if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) {
+		timerp->sr |= SLT_SR_ST;
+		timestamp++;
+		return;
+	}
+}
+
+void timer_init(void)
+{
+	volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE);
+
+	timestamp = 0;
+
+	timerp->cr = 0;		/* disable timer */
+	timerp->tcnt = 0;
+	timerp->sr = SLT_SR_BE | SLT_SR_ST;	/* clear status */
+
+	/* initialize and enable timer interrupt */
+	irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0);
+
+	/* Interrupt every ms */
+	timerp->tcnt = 1000 * CFG_TIMER_PRESCALER;
+
+	dtimer_intr_setup();
+
+	/* set a period of 1us, set timer mode to restart and
+	   enable timer and interrupt */
+	timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN;
+}
+
+void reset_timer(void)
+{
+	timestamp = 0;
+}
+
+ulong get_timer(ulong base)
+{
+	return (timestamp - base);
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+#endif				/* CONFIG_SLTTMR */
diff --git a/cpu/mcf547x_8x/speed.c b/cpu/mcf547x_8x/speed.c
new file mode 100644
index 0000000..389e7c9
--- /dev/null
+++ b/cpu/mcf547x_8x/speed.c
@@ -0,0 +1,43 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bus_clk = CFG_CLK;
+	gd->cpu_clk = (gd->bus_clk * 2);
+	return (0);
+}
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
new file mode 100644
index 0000000..442665f
--- /dev/null
+++ b/cpu/mcf547x_8x/start.S
@@ -0,0 +1,361 @@
+/*
+ * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include "version.h"
+
+#ifndef	 CONFIG_IDENT_STRING
+#define	 CONFIG_IDENT_STRING ""
+#endif
+
+/* last three long word reserved for cache status */
+#define ICACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
+#define DCACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
+#define CACR_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
+
+#define _START	_start
+#define _FAULT	_fault
+
+#define SAVE_ALL						\
+	move.w	#0x2700,%sr;		/* disable intrs */	\
+	subl	#60,%sp;		/* space for 15 regs */ \
+	moveml	%d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL						\
+	moveml	%sp@,%d0-%d7/%a0-%a6;				\
+	addl	#60,%sp;		/* space for 15 regs */ \
+	rte;
+
+.text
+/*
+ *	Vector table. This is used for initial platform startup.
+ *	These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+INITSP:		.long	0x00000000	/* Initial SP	*/
+INITPC:		.long	_START	/* Initial PC 		*/
+vector02:	.long	_FAULT	/* Access Error		*/
+vector03:	.long	_FAULT	/* Address Error	*/
+vector04:	.long	_FAULT	/* Illegal Instruction	*/
+vector05:	.long	_FAULT	/* Reserved		*/
+vector06:	.long	_FAULT	/* Reserved		*/
+vector07:	.long	_FAULT	/* Reserved		*/
+vector08:	.long	_FAULT	/* Privilege Violation	*/
+vector09:	.long	_FAULT	/* Trace		*/
+vector0A:	.long	_FAULT	/* Unimplemented A-Line	*/
+vector0B:	.long	_FAULT	/* Unimplemented F-Line	*/
+vector0C:	.long	_FAULT	/* Debug Interrupt	*/
+vector0D:	.long	_FAULT	/* Reserved		*/
+vector0E:	.long	_FAULT	/* Format Error		*/
+vector0F:	.long	_FAULT	/* Unitialized Int.	*/
+
+/* Reserved */
+vector10_17:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18:	.long	_FAULT	/* Spurious Interrupt	*/
+vector19:	.long	_FAULT	/* Autovector Level 1	*/
+vector1A:	.long	_FAULT	/* Autovector Level 2	*/
+vector1B:	.long	_FAULT	/* Autovector Level 3	*/
+vector1C:	.long	_FAULT	/* Autovector Level 4	*/
+vector1D:	.long	_FAULT	/* Autovector Level 5	*/
+vector1E:	.long	_FAULT	/* Autovector Level 6	*/
+vector1F:	.long	_FAULT	/* Autovector Level 7	*/
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved	*/
+vector30_3F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+	.text
+
+	.globl	_start
+_start:
+	nop
+	nop
+	move.w #0x2700,%sr		/* Mask off Interrupt */
+
+	/* Set vector base register at the beginning of the Flash */
+	move.l	#CFG_FLASH_BASE, %d0
+	movec	%d0, %VBR
+
+	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR0
+
+	move.l	#(CFG_INIT_RAM1_ADDR + CFG_INIT_RAM1_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	move.l	#CFG_MBAR, %d0		/* set MBAR address */
+	move.c	%d0, %MBAR
+
+	/* invalidate and disable cache */
+	move.l	#0x01040100, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+
+	/* initialize general use internal ram */
+	move.l #0, %d0
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* icache */
+	move.l #(CACR_STATUS), %a3	/* CACR */
+	move.l %d0, (%a1)
+	move.l %d0, (%a2)
+	move.l %d0, (%a3)
+
+	/* set stackpointer to end of internal ram to get some stackspace for the
+	   first c-code */
+	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+	clr.l %sp@-
+
+	move.l #__got_start, %a5	/* put relocation table address to a5 */
+
+	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
+	bsr board_init_f		/* run low-level board init code (from flash) */
+
+	/* board_init_f() does not return */
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+	link.w %a6,#0
+	move.l 8(%a6), %sp		/* set new stack pointer */
+
+	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l 16(%a6), %a0		/* Save copy of Destination Address */
+
+	move.l #CFG_MONITOR_BASE, %a1
+	move.l #__init_end, %a2
+	move.l %a0, %a3
+
+	/* copy the code to RAM */
+1:
+	move.l (%a1)+, (%a3)+
+	cmp.l  %a1,%a2
+	bgt.s	 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CFG_MONITOR_BASE),%a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CFG_MONITOR_BASE),%d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CFG_MONITOR_BASE),%a1
+	move.l	%a1,%a5		/* * fix got pointer register a5 */
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CFG_MONITOR_BASE),%a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start,%d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l %a0, %a1
+	add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l %a0,-(%sp)		/* dest_addr */
+	move.l %d0,-(%sp)		/* gd */
+	jsr	(%a1)
+
+/*------------------------------------------------------------------------------*/
+/* exception code */
+	.globl _fault
+_fault:
+	jmp _fault
+	.globl	_exc_handler
+
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+	.globl	_int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/*------------------------------------------------------------------------------*/
+/* cache functions */
+	.globl	icache_enable
+icache_enable:
+	move.l	#(CFG_SDRAM_BASE + 0x1c000), %d0
+	movec	%d0, %ACR2			/* Enable cache */
+
+	move.l	#0x020C8100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	nop
+
+	move.l #(ICACHE_STATUS), %a1
+	moveq	#1, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	icache_disable
+icache_disable:
+	move.l	#0x000C8100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Disable cache */
+	clr.l	%d0				/* Setup cache mask */
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+
+	move.l #(ICACHE_STATUS), %a1
+	moveq	#0, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	icache_invalid
+icache_invalid:
+	move.l	#0x000C8100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	rts
+
+	.globl	icache_status
+icache_status:
+	move.l #(ICACHE_STATUS), %a1
+	move.l	(%a1), %d0
+	rts
+
+	.globl	dcache_enable
+dcache_enable:
+	bsr	icache_disable
+
+	move.l	#(CFG_SDRAM_BASE + 0xc000), %d0
+	movec	%d0, %ACR0			/* Enable cache */
+
+	move.l	#0xA30C8100, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+
+	move.l #(DCACHE_STATUS), %a1
+	moveq	#1, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	dcache_disable
+dcache_disable:
+	move.l	#0xA30C8100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Disable cache */
+	clr.l	%d0				/* Setup cache mask */
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+
+	move.l #(DCACHE_STATUS), %a1
+	moveq	#0, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	dcache_status
+dcache_status:
+	move.l #(DCACHE_STATUS), %a1
+	move.l	(%a1), %d0
+	rts
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION
+	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii CONFIG_IDENT_STRING, "\0"
diff --git a/doc/README.m52277evb b/doc/README.m52277evb
new file mode 100644
index 0000000..de1daba
--- /dev/null
+++ b/doc/README.m52277evb
@@ -0,0 +1,237 @@
+Freescale MCF52277EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Jan 8, 2008
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m52277evb/m52277evb.c	Dram setup
+- board/freescale/m52277evb/Makefile	Makefile
+- board/freescale/m52277evb/config.mk	config make
+- board/freescale/m52277evb/u-boot.lds	Linker description
+
+- cpu/mcf5227x/cpu.c		cpu specific code
+- cpu/mcf5227x/cpu_init.c	FBCS, Mux pins, icache and RTC extra regs
+- cpu/mcf5227x/interrupts.c	cpu specific interrupt support
+- cpu/mcf5227x/speed.c		system, flexbus, and cpu clock
+- cpu/mcf5227x/Makefile		Makefile
+- cpu/mcf5227x/config.mk	config make
+- cpu/mcf5227x/start.S		start up assembly code
+
+- doc/README.m52277evb		This readme file
+
+- drivers/serial/mcfuart.c	ColdFire common UART driver
+- drivers/rtc/mcfrtc.c		Realtime clock Driver
+
+- include/asm-m68k/bitops.h		Bit operation function export
+- include/asm-m68k/byteorder.h		Byte order functions
+- include/asm-m68k/crossbar.h		CrossBar structure and definition
+- include/asm-m68k/dspi.h		DSPI structure and definition
+- include/asm-m68k/edma.h		eDMA structure and definition
+- include/asm-m68k/flexbus.h		FlexBus structure and definition
+- include/asm-m68k/fsl_i2c.h		I2C structure and definition
+- include/asm-m68k/global_data.h	Global data structure
+- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5227x.h	mcf5227x specific header file
+- include/asm-m68k/io.h			io functions
+- include/asm-m68k/lcd.h		LCD structure and definition
+- include/asm-m68k/m5227x.h		mcf5227x specific header file
+- include/asm-m68k/posix_types.h	Posix
+- include/asm-m68k/processor.h		header file
+- include/asm-m68k/ptrace.h		Exception structure
+- include/asm-m68k/rtc.h		Realtime clock header file
+- include/asm-m68k/ssi.h		SSI structure and definition
+- include/asm-m68k/string.h		String function export
+- include/asm-m68k/timer.h		Timer structure and definition
+- include/asm-m68k/types.h		Data types definition
+- include/asm-m68k/uart.h		Uart structure and definition
+- include/asm-m68k/u-boot.h		u-boot structure
+
+- include/configs/M52277EVB.h		Board specific configuration file
+
+- lib_m68k/board.c			board init function
+- lib_m68k/cache.c
+- lib_m68k/interrupts			Coldfire common interrupt functions
+- lib_m68k/m68k_linux.c
+- lib_m68k/time.c			Timer functions (Dma timer and PIT)
+- lib_m68k/traps.c			Exception init code
+
+1 MCF52277 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in this coldfire family
+
+1.2 Configuration settings for M52277EVB Development Board
+CONFIG_MCF5227x		-- define for all MCF5227x CPUs
+CONFIG_M52277		-- define for all Freescale MCF52277 CPUs
+CONFIG_M52277EVB	-- define for M52277EVB board
+
+CONFIG_MCFUART		-- define to use common CF Uart driver
+CFG_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE		-- define UART baudrate
+
+CONFIG_MCFRTC		-- define to use common CF RTC driver
+CFG_MCFRTC_BASE		-- provide base address for RTC in immap.h
+CFG_RTC_OSCILLATOR	-- define RTC clock frequency
+RTC_DEBUG		-- define to show RTC debug message
+CONFIG_CMD_DATE		-- enable to use date feature in u-boot
+
+CONFIG_MCFTMR		-- define to use DMA timer
+CONFIG_MCFPIT		-- define to use PIT timer
+
+CONFIG_FSL_I2C		-- define to use FSL common I2C driver
+CONFIG_HARD_I2C		-- define for I2C hardware support
+CONFIG_SOFT_I2C		-- define for I2C bit-banged
+CFG_I2C_SPEED		-- define for I2C speed
+CFG_I2C_SLAVE		-- define for I2C slave address
+CFG_I2C_OFFSET		-- define for I2C base address offset
+CFG_IMMR		-- define for MBAR offset
+
+CFG_MBAR		-- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CFG_INIT_RAM_ADDR	-- defines the base address of the MCF52277 internal SRAM
+
+CFG_CSn_BASE	-- defines the Chip Select Base register
+CFG_CSn_MASK	-- defines the Chip Select Mask register
+CFG_CSn_CTRL	-- defines the Chip Select Control register
+
+CFG_SDRAM_BASE	-- defines the DRAM Base
+
+CONFIG_LCD and CONFIG_CMD_USB are not supported in this current u-boot,
+update will be provided at later time
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	Flash:		0x00000000-0x3FFFFFFF (1024MB)
+	DDR:		0x40000000-0x7FFFFFFF (1024MB)
+	SRAM:		0x80000000-0x8FFFFFFF (256MB)
+	IP:		0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+	linux kernel, you can customize it based on your system requirements:
+	Flash0:		0x00000000-0x00FFFFFF (16MB)
+
+	DDR:		0x40000000-0x4FFFFFFF (64MB)
+	SRAM:		0x80000000-0x80007FFF (32KB)
+	IP:		0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1	To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot-1.x.x
+   make distclean
+   make M52277EVB_config
+   make
+
+4. SCREEN DUMP
+==============
+4.1 M52277EVB Development board
+    (NOTE: May not show exactly the same)
+
+U-Boot 1.3.1 (Jan 8 2008 - 12:44:08)
+
+CPU:   Freescale MCF52277 (Mask:6c Version:0)
+       CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ
+       INP CLK 16 Mhz VCO CLK 480 Mhz
+Board: Freescale 52277 EVB
+I2C:   ready
+DRAM:  64 MB
+FLASH: 16 MB
+In:    serial
+Out:   serial
+Err:   serial
+-> print
+baudrate=115200
+hostname=M52277EVB
+inpclk=16000000
+loadaddr=(0x40000000 + 0x10000)
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
+u-boot=u-boot.bin
+stdin=serial
+stdout=serial
+stderr=serial
+mem=65024k
+
+Environment size: 280/32764 bytes
+-> bdinfo
+memstart    = 0x40000000
+memsize     = 0x04000000
+flashstart  = 0x00000000
+flashsize   = 0x01000000
+flashoffset = 0x00000000
+sramstart   = 0x80000000
+sramsize    = 0x00008000
+mbar        = 0xFC000000
+busfreq     =     80 MHz
+flbfreq     =     80 Mhz
+inpfreq     =     16 Mhz
+vcofreq     =    480 Mhz
+
+baudrate    = 115200 bps
+->
+-> help
+?       - alias for 'help'
+autoscr - run script from memory
+base    - print or set address offset
+bdinfo  - print Board Info structure
+boot    - boot default, i.e., run 'bootcmd'
+bootd   - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm   - boot application image from memory
+bootp	- boot image via network using BootP/TFTP protocol
+bootvx  - Boot vxWorks from an ELF image
+cmp     - memory compare
+coninfo - print console devices and information
+cp      - memory copy
+crc32   - checksum calculation
+date    - get/set/reset date & time
+dcache  - enable or disable data cache
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+icache  - enable or disable instruction cache
+icrc32  - checksum calculation
+iloop   - infinite loop on address range
+imd     - i2c memory display
+iminfo  - print header information for application image
+imls    - list all images found in flash
+imm     - i2c memory modify (auto-incrementing)
+imw     - memory write (fill)
+inm     - memory modify (constant address)
+iprobe  - probe to discover valid I2C chip addresses
+itest	- return true/false on integer compare
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loady   - load binary file over serial line (ymodem mode)
+loop    - infinite loop on address range
+ls	- list files in a directory (default /)
+md      - memory display
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nm      - memory modify (constant address)
+ping	- send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+version - print monitor version
+->
diff --git a/doc/README.m5373evb b/doc/README.m5373evb
new file mode 100644
index 0000000..4f33b7d
--- /dev/null
+++ b/doc/README.m5373evb
@@ -0,0 +1,333 @@
+Freescale MCF5373EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 11/08/07
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m5373evb/m5373evb.c	Dram setup
+- board/freescale/m5373evb/mii.c	Mii access
+- board/freescale/m5373evb/Makefile	Makefile
+- board/freescale/m5373evb/config.mk	config make
+- board/freescale/m5373evb/u-boot.lds	Linker description
+
+- cpu/mcf532x/cpu.c		cpu specific code
+- cpu/mcf532x/cpu_init.c	FBCS, Mux pins, icache and RTC extra regs
+- cpu/mcf532x/interrupts.c	cpu specific interrupt support
+- cpu/mcf532x/speed.c		system, pci, flexbus, and cpu clock
+- cpu/mcf532x/Makefile		Makefile
+- cpu/mcf532x/config.mk		config make
+- cpu/mcf532x/start.S		start up assembly code
+
+- doc/README.m5373evb		This readme file
+
+- drivers/net/mcffec.c		ColdFire common FEC driver
+- drivers/serial/mcfuart.c	ColdFire common UART driver
+- drivers/rtc/mcfrtc.c		Realtime clock Driver
+
+- include/asm-m68k/bitops.h		Bit operation function export
+- include/asm-m68k/byteorder.h		Byte order functions
+- include/asm-m68k/fec.h		FEC structure and definition
+- include/asm-m68k/fsl_i2c.h		I2C structure and definition
+- include/asm-m68k/global_data.h	Global data structure
+- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
+- include/asm-m68k/immap_532x.h		mcf532x specific header file
+- include/asm-m68k/io.h			io functions
+- include/asm-m68k/m532x.h		mcf532x specific header file
+- include/asm-m68k/posix_types.h	Posix
+- include/asm-m68k/processor.h		header file
+- include/asm-m68k/ptrace.h		Exception structure
+- include/asm-m68k/rtc.h		Realtime clock header file
+- include/asm-m68k/string.h		String function export
+- include/asm-m68k/timer.h		Timer structure and definition
+- include/asm-m68k/types.h		Data types definition
+- include/asm-m68k/uart.h		Uart structure and definition
+- include/asm-m68k/u-boot.h		u-boot structure
+
+- include/configs/M5373EVB.h		Board specific configuration file
+
+- lib_m68k/board.c			board init function
+- lib_m68k/cache.c
+- lib_m68k/interrupts			Coldfire common interrupt functions
+- lib_m68k/m68k_linux.c
+- lib_m68k/time.c			Timer functions (Dma timer and PIT)
+- lib_m68k/traps.c			Exception init code
+
+1 MCF5373 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M5373EVB Development Board
+CONFIG_MCF532x		-- define for all MCF532x CPUs
+CONFIG_M5373		-- define for all Freescale MCF5373 CPUs
+CONFIG_M5373EVB		-- define for M5373EVB board
+
+CONFIG_MCFUART		-- define to use common CF Uart driver
+CFG_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE		-- define UART baudrate
+
+CONFIG_MCFRTC		-- define to use common CF RTC driver
+CFG_MCFRTC_BASE		-- provide base address for RTC in immap.h
+CFG_RTC_OSCILLATOR	-- define RTC clock frequency
+RTC_DEBUG		-- define to show RTC debug message
+CONFIG_CMD_DATE		-- enable to use date feature in u-boot
+
+CONFIG_MCFFEC		-- define to use common CF FEC driver
+CONFIG_NET_MULTI	-- define to use multi FEC in u-boot
+CONFIG_MII		-- enable to use MII driver
+CONFIG_CF_DOMII		-- enable to use MII feature in cmd_mii.c
+CFG_DISCOVER_PHY	-- enable PHY discovery
+CFG_RX_ETH_BUFFER	-- Set FEC Receive buffer
+CFG_FAULT_ECHO_LINK_DOWN--
+CFG_FEC0_PINMUX		-- Set FEC0 Pin configuration
+CFG_FEC0_MIIBASE	-- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP	-- set FEC timeout loop
+
+CONFIG_MCFTMR		-- define to use DMA timer
+CONFIG_MCFPIT		-- define to use PIT timer
+
+CONFIG_FSL_I2C		-- define to use FSL common I2C driver
+CONFIG_HARD_I2C		-- define for I2C hardware support
+CONFIG_SOFT_I2C		-- define for I2C bit-banged
+CFG_I2C_SPEED		-- define for I2C speed
+CFG_I2C_SLAVE		-- define for I2C slave address
+CFG_I2C_OFFSET		-- define for I2C base address offset
+CFG_IMMR		-- define for MBAR offset
+
+CFG_MBAR		-- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CFG_INIT_RAM_ADDR	-- defines the base address of the MCF5373 internal SRAM
+
+CFG_CSn_BASE	-- defines the Chip Select Base register
+CFG_CSn_MASK	-- defines the Chip Select Mask register
+CFG_CSn_CTRL	-- defines the Chip Select Control register
+
+CFG_SDRAM_BASE	-- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	Flash:		0x00000000-0x3FFFFFFF (1024MB)
+	DDR:		0x40000000-0x7FFFFFFF (1024MB)
+	SRAM:		0x80000000-0x8FFFFFFF (256MB)
+	IP:		0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+	linux kernel, you can customize it based on your system requirements:
+	Flash0:		0x00000000-0x00FFFFFF (16MB)
+
+	DDR:		0x40000000-0x4FFFFFFF (256MB)
+	SRAM:		0x80000000-0x80007FFF (32KB)
+	IP:		0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1	To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot-1.x.x
+   make distclean
+   make M5373EVB_config
+   make
+
+4. SCREEN DUMP
+==============
+4.1 M5373EVB Development board
+    (NOTE: May not show exactly the same)
+
+U-Boot 1.3.0 (Nov 8 2007 - 12:44:08)
+
+CPU:   Freescale MCF5373 (Mask:65 Version:1)
+       CPU CLK 240 Mhz BUS CLK 80 Mhz
+Board: Freescale FireEngine 5373 EVB
+I2C:   ready
+DRAM:  32 MB
+FLASH: 2 MB
+In:    serial
+Out:   serial
+Err:   serial
+NAND:  16 MiB
+Net:   FEC0
+-> print
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+hostname=M5373EVB
+netdev=eth0
+loadaddr=40010000
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+u-boot=u-boot.bin
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+
+Environment size: 401/8188 bytes
+-> bdinfo
+memstart    = 0x40000000
+memsize     = 0x02000000
+flashstart  = 0x00000000
+flashsize   = 0x00200000
+flashoffset = 0x00000000
+sramstart   = 0x80000000
+sramsize    = 0x00008000
+mbar        = 0xFC000000
+busfreq     =     80 MHz
+ethaddr     = 00:E0:0C:BC:E5:60
+ip_addr     = 192.168.1.3
+baudrate    = 115200 bps
+->
+-> help
+?       - alias for 'help'
+autoscr - run script from memory
+base    - print or set address offset
+bdinfo  - print Board Info structure
+boot    - boot default, i.e., run 'bootcmd'
+bootd   - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm   - boot application image from memory
+bootp	- boot image via network using BootP/TFTP protocol
+bootvx  - Boot vxWorks from an ELF image
+cmp     - memory compare
+coninfo - print console devices and information
+cp      - memory copy
+crc32   - checksum calculation
+date    - get/set/reset date & time
+dcache  - enable or disable data cache
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+icache  - enable or disable instruction cache
+icrc32  - checksum calculation
+iloop   - infinite loop on address range
+imd     - i2c memory display
+iminfo  - print header information for application image
+imls    - list all images found in flash
+imm     - i2c memory modify (auto-incrementing)
+imw     - memory write (fill)
+inm     - memory modify (constant address)
+iprobe  - probe to discover valid I2C chip addresses
+itest	- return true/false on integer compare
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loady   - load binary file over serial line (ymodem mode)
+loop    - infinite loop on address range
+ls	- list files in a directory (default /)
+md      - memory display
+mii     - MII utility commands
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nand	- NAND sub-system
+nboot	- boot from NAND device
+nfs	- boot image via network using NFS protocol
+nm      - memory modify (constant address)
+ping	- send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+-> tftp 0x40800000 uImage
+Using FEC0 device
+TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'.
+Load address: 0x40800000
+Loading: #################################################################
+          #################################################################
+          ##########
+done
+Bytes transferred = 2053270 (1f5496 hex)
+-> bootm 0x40800000
+## Booting image at 40800000 ...
+    Image Name:   Linux Kernel Image
+    Created:      2007-11-07  20:33:08 UTC
+    Image Type:   M68K Linux Kernel Image (gzip compressed)
+    Data Size:    2053206 Bytes =  2 MB
+    Load Address: 40020000
+    Entry Point:  40020000
+    Verifying Checksum ... OK
+    Uncompressing Kernel Image ... OK
+Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7
+
+
+uClinux/COLDFIRE(m537x)
+COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists.  Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512
+NET: Registered protocol family 16
+USB-MCF537x: (HOST module) EHCI device is registered
+USB-MCF537x: (OTG module) EHCI device is registered
+USB-MCF537x: (OTG module) UDC device is registered
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+NET: Registered protocol family 2
+IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
+TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered
+JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
+io scheduler noop registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+nbd: registered device at major 43
+usbcore: registered new interface driver ub FEC ENET Version 0.2
+fec: PHY @ 0x1, ID 0x20005c90 -- DP83848
+eth0: ethernet 00:e0:0c:bc:e5:60
+uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM":
+0x00000000-0x0022b000 : "ROMfs"
+uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit":
+0x00000000-0x01000000 : "M53xx flash partition 1"
+QSPI: spi->max_speed_hz 300000
+QSPI: Baud set to 255
+SPI: Coldfire master initialized
+M537x - Disable UART1 when using Audio
+udc: Freescale MCF53xx UDC driver version 27 October 2006 init
+udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+VFS: Mounted root (romfs filesystem) readonly.
+Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started:  BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems
+mount: Mounting devpts on /dev/pts failed: No such device
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device:
+Setting up networking on eth0:
+info, udhcpc (v0.9.9-pre) started
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+debug, Sending discover...
+debug, Sending discover...
+debug, Sending select for 172.27.0.130...
+info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers
+route: SIOC[ADD|DEL]RT: No such process
+adding dns 172.27.0.1
+Starting the boa webserver:
+Setting time from ntp server: ntp.cs.strath.ac.uk
+ntp.cs.strath.ac.uk: Unknown host
+
+
+BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands.
+
+#
diff --git a/doc/README.m5475evb b/doc/README.m5475evb
new file mode 100644
index 0000000..cec4fd0
--- /dev/null
+++ b/doc/README.m5475evb
@@ -0,0 +1,279 @@
+Freescale MCF5475EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Jan 08, 2008
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m547xevb/m547xevb.c	Dram setup, IDE pre init, and PCI init
+- board/freescale/m547xevb/mii.c	MII init
+- board/freescale/m547xevb/Makefile	Makefile
+- board/freescale/m547xevb/config.mk	config make
+- board/freescale/m547xevb/u-boot.lds	Linker description
+
+- cpu/mcf547x_8x/cpu.c			cpu specific code
+- cpu/mcf547x_8x/cpu_init.c		Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- cpu/mcf547x_8x/interrupts.c		cpu specific interrupt support
+- cpu/mcf547x_8x/slicetimer.c		Timer support
+- cpu/mcf547x_8x/speed.c		system, pci, flexbus, and cpu clock
+- cpu/mcf547x_8x/Makefile		Makefile
+- cpu/mcf547x_8x/config.mk		config make
+- cpu/mcf547x_8x/start.S		start up assembly code
+
+- doc/README.m5475evb			This readme file
+
+- drivers/dma/MCD_dmaApi.c		DMA API functions
+- drivers/dma/MCD_tasks.c		DMA Tasks
+- drivers/dma/MCD_tasksInit.c		DMA Tasks Init
+- drivers/net/fsl_mcdmafec.c		ColdFire common DMA FEC driver
+- drivers/serial/mcfuart.c		ColdFire common UART driver
+
+- include/MCD_dma.h			DMA header file
+- include/MCD_progCheck.h		DMA header file
+- include/MCD_tasksInit.h		DMA header file
+- include/asm-m68k/bitops.h		Bit operation function export
+- include/asm-m68k/byteorder.h		Byte order functions
+- include/asm-m68k/errno.h		Error Number definition
+- include/asm-m68k/fec.h		FEC structure and definition
+- include/asm-m68k/fsl_i2c.h		I2C structure and definition
+- include/asm-m68k/fsl_mcddmafec.h	DMA FEC structure and definition
+- include/asm-m68k/global_data.h	Global data structure
+- include/asm-m68k/immap.h		ColdFire specific header file and driver macros
+- include/asm-m68k/immap_547x_8x.h	mcf547x_8x specific header file
+- include/asm-m68k/io.h			io functions
+- include/asm-m68k/m547x_8x.h		mcf547x_8x specific header file
+- include/asm-m68k/posix_types.h	Posix
+- include/asm-m68k/processor.h		header file
+- include/asm-m68k/ptrace.h		Exception structure
+- include/asm-m68k/rtc.h		Realtime clock header file
+- include/asm-m68k/string.h		String function export
+- include/asm-m68k/timer.h		Timer structure and definition
+- include/asm-m68k/types.h		Data types definition
+- include/asm-m68k/uart.h		Uart structure and definition
+- include/asm-m68k/u-boot.h		u-boot structure
+
+- include/configs/M5475EVB.h		Board specific configuration file
+
+- lib_m68k/board.c			board init function
+- lib_m68k/cache.c
+- lib_m68k/interrupts			Coldfire common interrupt functions
+- lib_m68k/m68k_linux.c
+- lib_m68k/traps.c			Exception init code
+
+1 MCF547x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M5475EVB Development Board
+CONFIG_MCF547x_8x	-- define for all MCF547x_8x CPUs
+CONFIG_M547x		-- define for all Freescale MCF547x CPUs
+CONFIG_M5475		-- define for M5475EVB board
+
+CONFIG_MCFUART		-- define to use common CF Uart driver
+CFG_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE		-- define UART baudrate
+
+CONFIG_FSLDMAFEC	-- define to use common dma FEC driver
+CONFIG_NET_MULTI	-- define to use multi FEC in u-boot
+CONFIG_MII		-- enable to use MII driver
+CONFIG_CF_DOMII		-- enable to use MII feature in cmd_mii.c
+CFG_DISCOVER_PHY	-- enable PHY discovery
+CFG_RX_ETH_BUFFER	-- Set FEC Receive buffer
+CFG_FAULT_ECHO_LINK_DOWN--
+CFG_FEC0_PINMUX		-- Set FEC0 Pin configuration
+CFG_FEC1_PINMUX		-- Set FEC1 Pin configuration
+CFG_FEC0_MIIBASE	-- Set FEC0 MII base register
+CFG_FEC1_MIIBASE	-- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP	-- set FEC timeout loop
+CONFIG_HAS_ETH1		-- define to enable second FEC in u-boot
+
+CONFIG_CMD_USB		-- enable USB commands
+CONFIG_USB_OHCI_NEW	-- enable USB OHCI driver
+CONFIG_USB_STORAGE	-- enable USB Storage device
+CONFIG_DOS_PARTITION	-- enable DOS read/write
+
+CONFIG_SLTTMR		-- define to use SLT timer
+
+CONFIG_FSL_I2C		-- define to use FSL common I2C driver
+CONFIG_HARD_I2C		-- define for I2C hardware support
+CONFIG_SOFT_I2C		-- define for I2C bit-banged
+CFG_I2C_SPEED		-- define for I2C speed
+CFG_I2C_SLAVE		-- define for I2C slave address
+CFG_I2C_OFFSET		-- define for I2C base address offset
+CFG_IMMR		-- define for MBAR offset
+
+CONFIG_PCI              -- define for PCI support
+CONFIG_PCI_PNP          -- define for Plug n play support
+CONFIG_SKIPPCI_HOSTBRIDGE	-- SKIP PCI Host bridge
+CFG_PCI_MEM_BUS		-- PCI memory logical offset
+CFG_PCI_MEM_PHYS	-- PCI memory physical offset
+CFG_PCI_MEM_SIZE	-- PCI memory size
+CFG_PCI_IO_BUS		-- PCI IO logical offset
+CFG_PCI_IO_PHYS		-- PCI IO physical offset
+CFG_PCI_IO_SIZE		-- PCI IO size
+CFG_PCI_CFG_BUS		-- PCI Configuration logical offset
+CFG_PCI_CFG_PHYS	-- PCI Configuration physical offset
+CFG_PCI_CFG_SIZE	-- PCI Configuration size
+
+CFG_MBAR		-- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CFG_INIT_RAM_ADDR	-- defines the base address of the MCF547x internal SRAM
+
+CFG_CSn_BASE	-- defines the Chip Select Base register
+CFG_CSn_MASK	-- defines the Chip Select Mask register
+CFG_CSn_CTRL	-- defines the Chip Select Control register
+
+CFG_SDRAM_BASE	-- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	Flash:		0xFF800000-0xFFFFFFFF (8MB)
+	DDR:		0x00000000-0x3FFFFFFF (1024MB)
+	SRAM:		0xF2000000-0xF2000FFF (4KB)
+	PCI:		0x70000000-0x8FFFFFFF (512MB)
+	IP:		0xF0000000-0xFFFFFFFF (256MB)
+
+3. COMPILATION
+==============
+3.1	To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux
+        version) from codesourcery.com was used. Download it from:
+	http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot-1.x.x
+   make distclean
+   make M5475AFE_config, or	- boot 2MB, RAM 64MB
+   make M5475BFE_config, or	- boot 2MB, code 16MB, RAM 64MB
+   make M5475CFE_config, or	- boot 2MB, code 16MB, Video, USB, RAM 64MB
+   make M5475DFE_config, or	- boot 2MB, USB, RAM 64MB
+   make M5475EFE_config, or	- boot 2MB, Video, USB, RAM 64MB
+   make M5475FFE_config, or	- boot 2MB, code 32MB, Video, USB, RAM 128MB
+   make M5475GFE_config, or	- boot 2MB, RAM 64MB
+   make
+
+5. SCREEN DUMP
+==============
+5.1
+
+U-Boot 1.3.1 (Jan  8 2008 - 12:47:44)
+
+CPU:   Freescale MCF5475
+       CPU CLK 266 Mhz BUS CLK 133 Mhz
+Board: Freescale FireEngine 5475 EVB
+I2C:   ready
+DRAM:  64 MB
+FLASH: 18 MB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   FEC0, FEC1
+-> pri
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+ipaddr=192.162.1.2
+serverip=192.162.1.1
+gatewayip=192.162.1.1
+netmask=255.255.255.0
+hostname=M547xEVB
+netdev=eth0
+loadaddr=10000
+u-boot=u-boot.bin
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save
+stdin=serial
+stdout=serial
+stderr=serial
+ethact=FEC0
+mem=65024k
+
+Environment size: 433/8188 bytes
+-> bdin
+memstart    = 0x00000000
+memsize     = 0x04000000
+flashstart  = 0xFF800000
+flashsize   = 0x01200000
+flashoffset = 0x00000000
+sramstart   = 0xF2000000
+sramsize    = 0x00001000
+mbar        = 0xF0000000
+busfreq     = 133.333 MHz
+pcifreq     =      0 MHz
+ethaddr     = 00:E0:0C:BC:E5:60
+eth1addr    = 00:E0:0C:BC:E5:61
+ip_addr     = 192.162.1.2
+baudrate    = 115200 bps
+-> ?
+?       - alias for 'help'
+autoscr - run script from memory
+base    - print or set address offset
+bdinfo  - print Board Info structure
+boot    - boot default, i.e., run 'bootcmd'
+bootd   - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm   - boot application image from memory
+bootp	- boot image via network using BootP/TFTP protocol
+bootvx  - Boot vxWorks from an ELF image
+cmp     - memory compare
+coninfo - print console devices and information
+cp      - memory copy
+crc32   - checksum calculation
+dcache  - enable or disable data cache
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+icache  - enable or disable instruction cache
+icrc32  - checksum calculation
+iloop   - infinite loop on address range
+imd     - i2c memory display
+iminfo  - print header information for application image
+imls    - list all images found in flash
+imm     - i2c memory modify (auto-incrementing)
+imw     - memory write (fill)
+inm     - memory modify (constant address)
+iprobe  - probe to discover valid I2C chip addresses
+itest	- return true/false on integer compare
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loady   - load binary file over serial line (ymodem mode)
+loop    - infinite loop on address range
+md      - memory display
+mii     - MII utility commands
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nfs	- boot image via network using NFS protocol
+nm      - memory modify (constant address)
+pci     - list and access PCI Configuration Space
+ping	- send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+tftpboot- boot image via network using TFTP protocol
+usb     - USB sub-system
+usbboot - boot from USB device
+version - print monitor version
+-> usb start
+(Re)start USB...
+USB:   OHCI pci controller (1131, 1561) found @(0:17:0)
+OHCI regs address 0x80000000
+scanning bus for devices... 2 USB Device(s) found
+       scanning bus for storage devices... 1 Storage Device(s) found
+->
diff --git a/drivers/dma/MCD_dmaApi.c b/drivers/dma/MCD_dmaApi.c
new file mode 100644
index 0000000..b0062b7
--- /dev/null
+++ b/drivers/dma/MCD_dmaApi.c
@@ -0,0 +1,1026 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*Main C file for multi-channel DMA API. */
+
+#include <common.h>
+
+#ifdef CONFIG_FSLDMAFEC
+
+#include <MCD_dma.h>
+#include <MCD_tasksInit.h>
+#include <MCD_progCheck.h>
+
+/********************************************************************/
+/* This is an API-internal pointer to the DMA's registers */
+dmaRegs *MCD_dmaBar;
+
+/*
+ * These are the real and model task tables as generated by the
+ * build process
+ */
+extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
+extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
+
+/*
+ * However, this (usually) gets relocated to on-chip SRAM, at which
+ * point we access them as these tables
+ */
+volatile TaskTableEntry *MCD_taskTable;
+TaskTableEntry *MCD_modelTaskTable;
+
+/*
+ * MCD_chStatus[] is an array of status indicators for remembering
+ * whether a DMA has ever been attempted on each channel, pausing
+ * status, etc.
+ */
+static int MCD_chStatus[NCHANNELS] = {
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
+};
+
+/* Prototypes for local functions */
+static void MCD_memcpy(int *dest, int *src, u32 size);
+static void MCD_resmActions(int channel);
+
+/*
+ * Buffer descriptors used for storage of progress info for single Dmas
+ * Also used as storage for the DMA for CRCs for single DMAs
+ * Otherwise, the DMA does not parse these buffer descriptors
+ */
+#ifdef MCD_INCLUDE_EU
+extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
+#else
+MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
+#endif
+MCD_bufDesc *MCD_relocBuffDesc;
+
+/* Defines for the debug control register's functions */
+#define DBG_CTL_COMP1_TASK	(0x00002000)
+#define DBG_CTL_ENABLE		(DBG_CTL_AUTO_ARM	| \
+				 DBG_CTL_BREAK		| \
+				 DBG_CTL_INT_BREAK	| \
+				 DBG_CTL_COMP1_TASK)
+#define DBG_CTL_DISABLE		(DBG_CTL_AUTO_ARM	| \
+				 DBG_CTL_INT_BREAK	| \
+				 DBG_CTL_COMP1_TASK)
+#define DBG_KILL_ALL_STAT	(0xFFFFFFFF)
+
+/* Offset to context save area where progress info is stored */
+#define CSAVE_OFFSET		10
+
+/* Defines for Byte Swapping */
+#define MCD_BYTE_SWAP_KILLER	0xFFF8888F
+#define MCD_NO_BYTE_SWAP_ATALL	0x00040000
+
+/* Execution Unit Identifiers */
+#define MAC			0	/* legacy - not used */
+#define LUAC			1	/* legacy - not used */
+#define CRC			2	/* legacy - not used */
+#define LURC			3	/* Logic Unit with CRC */
+
+/* Task Identifiers */
+#define TASK_CHAINNOEU		0
+#define TASK_SINGLENOEU		1
+#ifdef MCD_INCLUDE_EU
+#define TASK_CHAINEU		2
+#define TASK_SINGLEEU		3
+#define TASK_FECRX		4
+#define TASK_FECTX		5
+#else
+#define TASK_CHAINEU		0
+#define TASK_SINGLEEU		1
+#define TASK_FECRX		2
+#define TASK_FECTX		3
+#endif
+
+/*
+ * Structure to remember which variant is on which channel
+ * TBD- need this?
+ */
+typedef struct MCD_remVariants_struct MCD_remVariant;
+struct MCD_remVariants_struct {
+	int remDestRsdIncr[NCHANNELS];	/* -1,0,1 */
+	int remSrcRsdIncr[NCHANNELS];	/* -1,0,1 */
+	s16 remDestIncr[NCHANNELS];	/* DestIncr */
+	s16 remSrcIncr[NCHANNELS];	/* srcIncr */
+	u32 remXferSize[NCHANNELS];	/* xferSize */
+};
+
+/* Structure to remember the startDma parameters for each channel */
+MCD_remVariant MCD_remVariants;
+/********************************************************************/
+/* Function: MCD_initDma
+ * Purpose:  Initializes the DMA API by setting up a pointer to the DMA
+ *           registers, relocating and creating the appropriate task
+ *           structures, and setting up some global settings
+ * Arguments:
+ *  dmaBarAddr    - pointer to the multichannel DMA registers
+ *  taskTableDest - location to move DMA task code and structs to
+ *  flags         - operational parameters
+ * Return Value:
+ *  MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
+ *  MCD_OK otherwise
+ */
+extern u32 MCD_funcDescTab0[];
+
+int MCD_initDma(dmaRegs * dmaBarAddr, void *taskTableDest, u32 flags)
+{
+	int i;
+	TaskTableEntry *entryPtr;
+
+	/* setup the local pointer to register set */
+	MCD_dmaBar = dmaBarAddr;
+
+	/* do we need to move/create a task table */
+	if ((flags & MCD_RELOC_TASKS) != 0) {
+		int fixedSize;
+		u32 *fixedPtr;
+		/*int *tablePtr = taskTableDest;TBD */
+		int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
+		int taskDescTabsOffset;
+		int taskTableSize, varTabsSize, funcDescTabsSize,
+		    contextSavesSize;
+		int taskDescTabSize;
+
+		int i;
+
+		/* check if physical address is aligned on 512 byte boundary */
+		if (((u32) taskTableDest & 0x000001ff) != 0)
+			return (MCD_TABLE_UNALIGNED);
+
+		/* set up local pointer to task Table */
+		MCD_taskTable = taskTableDest;
+
+		/*
+		 * Create a task table:
+		 * - compute aligned base offsets for variable tables and
+		 *   function descriptor tables, then
+		 * - loop through the task table and setup the pointers
+		 * - copy over model task table with the the actual task
+		 *   descriptor tables
+		 */
+
+		taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
+		/* align variable tables to size */
+		varTabsOffset = taskTableSize + (u32) taskTableDest;
+		if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
+			varTabsOffset =
+			    (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
+		/* align function descriptor tables */
+		varTabsSize = NCHANNELS * VAR_TAB_SIZE;
+		funcDescTabsOffset = varTabsOffset + varTabsSize;
+
+		if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
+			funcDescTabsOffset =
+			    (funcDescTabsOffset +
+			     FUNCDESC_TAB_SIZE) & (~FUNCDESC_TAB_SIZE);
+
+		funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
+		contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
+		contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
+		fixedSize =
+		    taskTableSize + varTabsSize + funcDescTabsSize +
+		    contextSavesSize;
+
+		/* zero the thing out */
+		fixedPtr = (u32 *) taskTableDest;
+		for (i = 0; i < (fixedSize / 4); i++)
+			fixedPtr[i] = 0;
+
+		entryPtr = (TaskTableEntry *) MCD_taskTable;
+		/* set up fixed pointers */
+		for (i = 0; i < NCHANNELS; i++) {
+			/* update ptr to local value */
+			entryPtr[i].varTab = (u32) varTabsOffset;
+			entryPtr[i].FDTandFlags =
+			    (u32) funcDescTabsOffset | MCD_TT_FLAGS_DEF;
+			entryPtr[i].contextSaveSpace = (u32) contextSavesOffset;
+			varTabsOffset += VAR_TAB_SIZE;
+#ifdef MCD_INCLUDE_EU
+			/* if not there is only one, just point to the
+			   same one */
+			funcDescTabsOffset += FUNCDESC_TAB_SIZE;
+#endif
+			contextSavesOffset += CONTEXT_SAVE_SIZE;
+		}
+		/* copy over the function descriptor table */
+		for (i = 0; i < FUNCDESC_TAB_NUM; i++) {
+			MCD_memcpy((void *)(entryPtr[i].
+					    FDTandFlags & ~MCD_TT_FLAGS_MASK),
+				   (void *)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
+		}
+
+		/* copy model task table to where the context saves stuff
+		   leaves off */
+		MCD_modelTaskTable = (TaskTableEntry *) contextSavesOffset;
+
+		MCD_memcpy((void *)MCD_modelTaskTable,
+			   (void *)MCD_modelTaskTableSrc,
+			   NUMOFVARIANTS * sizeof(TaskTableEntry));
+
+		/* point to local version of model task table */
+		entryPtr = MCD_modelTaskTable;
+		taskDescTabsOffset = (u32) MCD_modelTaskTable +
+		    (NUMOFVARIANTS * sizeof(TaskTableEntry));
+
+		/* copy actual task code and update TDT ptrs in local
+		   model task table */
+		for (i = 0; i < NUMOFVARIANTS; i++) {
+			taskDescTabSize =
+			    entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
+			MCD_memcpy((void *)taskDescTabsOffset,
+				   (void *)entryPtr[i].TDTstart,
+				   taskDescTabSize);
+			entryPtr[i].TDTstart = (u32) taskDescTabsOffset;
+			taskDescTabsOffset += taskDescTabSize;
+			entryPtr[i].TDTend = (u32) taskDescTabsOffset - 4;
+		}
+#ifdef MCD_INCLUDE_EU
+		/* Tack single DMA BDs onto end of code so API controls
+		   where they are since DMA might write to them */
+		MCD_relocBuffDesc =
+		    (MCD_bufDesc *) (entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
+#else
+		/* DMA does not touch them so they can be wherever and we
+		   don't need to waste SRAM on them */
+		MCD_relocBuffDesc = MCD_singleBufDescs;
+#endif
+	} else {
+		/* point the would-be relocated task tables and the
+		   buffer descriptors to the ones the linker generated */
+
+		if (((u32) MCD_realTaskTableSrc & 0x000001ff) != 0)
+			return (MCD_TABLE_UNALIGNED);
+
+		/* need to add code to make sure that every thing else is
+		   aligned properly TBD. this is problematic if we init
+		   more than once or after running tasks, need to add
+		   variable to see if we have aleady init'd */
+		entryPtr = MCD_realTaskTableSrc;
+		for (i = 0; i < NCHANNELS; i++) {
+			if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
+			    ((entryPtr[i].
+			      FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
+				return (MCD_TABLE_UNALIGNED);
+		}
+
+		MCD_taskTable = MCD_realTaskTableSrc;
+		MCD_modelTaskTable = MCD_modelTaskTableSrc;
+		MCD_relocBuffDesc = MCD_singleBufDescs;
+	}
+
+	/* Make all channels as totally inactive, and remember them as such: */
+
+	MCD_dmaBar->taskbar = (u32) MCD_taskTable;
+	for (i = 0; i < NCHANNELS; i++) {
+		MCD_dmaBar->taskControl[i] = 0x0;
+		MCD_chStatus[i] = MCD_NO_DMA;
+	}
+
+	/* Set up pausing mechanism to inactive state: */
+	/* no particular values yet for either comparator registers */
+	MCD_dmaBar->debugComp1 = 0;
+	MCD_dmaBar->debugComp2 = 0;
+	MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
+	MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
+
+	/* enable or disable commbus prefetch, really need an ifdef or
+	   something to keep from trying to set this in the 8220 */
+	if ((flags & MCD_COMM_PREFETCH_EN) != 0)
+		MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
+	else
+		MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
+
+	return (MCD_OK);
+}
+
+/*********************** End of MCD_initDma() ***********************/
+
+/********************************************************************/
+/* Function:   MCD_dmaStatus
+ * Purpose:    Returns the status of the DMA on the requested channel
+ * Arguments:  channel - channel number
+ * Returns:    Predefined status indicators
+ */
+int MCD_dmaStatus(int channel)
+{
+	u16 tcrValue;
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	tcrValue = MCD_dmaBar->taskControl[channel];
+	if ((tcrValue & TASK_CTL_EN) == 0) {	/* nothing running */
+		/* if last reported with task enabled */
+		if (MCD_chStatus[channel] == MCD_RUNNING
+		    || MCD_chStatus[channel] == MCD_IDLE)
+			MCD_chStatus[channel] = MCD_DONE;
+	} else {		/* something is running */
+
+		/* There are three possibilities: paused, running or idle. */
+		if (MCD_chStatus[channel] == MCD_RUNNING
+		    || MCD_chStatus[channel] == MCD_IDLE) {
+			MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
+			/* This register is selected to know which initiator is
+			   actually asserted. */
+			if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
+				MCD_chStatus[channel] = MCD_RUNNING;
+			else
+				MCD_chStatus[channel] = MCD_IDLE;
+			/* do not change the status if it is already paused. */
+		}
+	}
+	return MCD_chStatus[channel];
+}
+
+/******************** End of MCD_dmaStatus() ************************/
+
+/********************************************************************/
+/* Function:    MCD_startDma
+ * Ppurpose:    Starts a particular kind of DMA
+ * Arguments:
+ * srcAddr	- the channel on which to run the DMA
+ * srcIncr	- the address to move data from, or buffer-descriptor address
+ * destAddr	- the amount to increment the source address per transfer
+ * destIncr	- the address to move data to
+ * dmaSize	- the amount to increment the destination address per transfer
+ * xferSize	- the number bytes in of each data movement (1, 2, or 4)
+ * initiator	- what device initiates the DMA
+ * priority	- priority of the DMA
+ * flags	- flags describing the DMA
+ * funcDesc	- description of byte swapping, bit swapping, and CRC actions
+ * srcAddrVirt	- virtual buffer descriptor address TBD
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ */
+
+int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
+		 s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
+		 int priority, u32 flags, u32 funcDesc
+#ifdef MCD_NEED_ADDR_TRANS
+		 s8 * srcAddrVirt
+#endif
+    )
+{
+	int srcRsdIncr, destRsdIncr;
+	int *cSave;
+	short xferSizeIncr;
+	int tcrCount = 0;
+#ifdef MCD_INCLUDE_EU
+	u32 *realFuncArray;
+#endif
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	/* tbd - need to determine the proper response to a bad funcDesc when
+	   not including EU functions, for now, assign a benign funcDesc, but
+	   maybe should return an error */
+#ifndef MCD_INCLUDE_EU
+	funcDesc = MCD_FUNC_NOEU1;
+#endif
+
+#ifdef MCD_DEBUG
+	printf("startDma:Setting up params\n");
+#endif
+	/* Set us up for task-wise priority.  We don't technically need to do
+	   this on every start, but since the register involved is in the same
+	   longword as other registers that users are in control of, setting
+	   it more than once is probably preferable.  That since the
+	   documentation doesn't seem to be completely consistent about the
+	   nature of the PTD control register. */
+	MCD_dmaBar->ptdControl |= (u16) 0x8000;
+
+	/* Not sure what we need to keep here rtm TBD */
+#if 1
+	/* Calculate additional parameters to the regular DMA calls. */
+	srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
+	destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
+
+	xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
+
+	/* Remember for each channel which variant is running. */
+	MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
+	MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
+	MCD_remVariants.remDestIncr[channel] = destIncr;
+	MCD_remVariants.remSrcIncr[channel] = srcIncr;
+	MCD_remVariants.remXferSize[channel] = xferSize;
+#endif
+
+	cSave =
+	    (int *)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET +
+	    CURRBD;
+
+#ifdef MCD_INCLUDE_EU
+	/* may move this to EU specific calls */
+	realFuncArray =
+	    (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
+	/* Modify the LURC's normal and byte-residue-loop functions according
+	   to parameter. */
+	realFuncArray[(LURC * 16)] = xferSize == 4 ?
+	    funcDesc : xferSize == 2 ?
+	    funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
+	realFuncArray[(LURC * 16 + 1)] =
+	    (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
+#endif
+	/* Write the initiator field in the TCR, and also set the
+	   initiator-hold bit. Note that,due to a hardware quirk, this could
+	   collide with an MDE access to the initiator-register file, so we
+	   have to verify that the write reads back correctly. */
+
+	MCD_dmaBar->taskControl[channel] =
+	    (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
+
+	while (((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
+		((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM))
+	       && (tcrCount < 1000)) {
+		tcrCount++;
+		/*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020; */
+		MCD_dmaBar->taskControl[channel] =
+		    (initiator << 8) | TASK_CTL_HIPRITSKEN |
+		    TASK_CTL_HLDINITNUM;
+	}
+
+	MCD_dmaBar->priority[channel] = (u8) priority & PRIORITY_PRI_MASK;
+	/* should be albe to handle this stuff with only one write to ts reg
+	   - tbd */
+	if (channel < 8 && channel >= 0) {
+		MCD_dmaBar->taskSize0 &= ~(0xf << (7 - channel) * 4);
+		MCD_dmaBar->taskSize0 |=
+		    (xferSize & 3) << (((7 - channel) * 4) + 2);
+		MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel) * 4);
+	} else {
+		MCD_dmaBar->taskSize1 &= ~(0xf << (15 - channel) * 4);
+		MCD_dmaBar->taskSize1 |=
+		    (xferSize & 3) << (((15 - channel) * 4) + 2);
+		MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel) * 4);
+	}
+
+	/* setup task table flags/options which mostly control the line
+	   buffers */
+	MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
+	MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
+
+	if (flags & MCD_FECTX_DMA) {
+		/* TDTStart and TDTEnd */
+		MCD_taskTable[channel].TDTstart =
+		    MCD_modelTaskTable[TASK_FECTX].TDTstart;
+		MCD_taskTable[channel].TDTend =
+		    MCD_modelTaskTable[TASK_FECTX].TDTend;
+		MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable,
+				     channel);
+	} else if (flags & MCD_FECRX_DMA) {
+		/* TDTStart and TDTEnd */
+		MCD_taskTable[channel].TDTstart =
+		    MCD_modelTaskTable[TASK_FECRX].TDTstart;
+		MCD_taskTable[channel].TDTend =
+		    MCD_modelTaskTable[TASK_FECRX].TDTend;
+		MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable,
+				    channel);
+	} else if (flags & MCD_SINGLE_DMA) {
+		/* this buffer descriptor is used for storing off initial
+		   parameters for later progress query calculation and for the
+		   DMA to write the resulting checksum. The DMA does not use
+		   this to determine how to operate, that info is passed with
+		   the init routine */
+		MCD_relocBuffDesc[channel].srcAddr = srcAddr;
+		MCD_relocBuffDesc[channel].destAddr = destAddr;
+
+		/* definitely not its final value */
+		MCD_relocBuffDesc[channel].lastDestAddr = destAddr;
+
+		MCD_relocBuffDesc[channel].dmaSize = dmaSize;
+		MCD_relocBuffDesc[channel].flags = 0;	/* not used */
+		MCD_relocBuffDesc[channel].csumResult = 0;	/* not used */
+		MCD_relocBuffDesc[channel].next = 0;	/* not used */
+
+		/* Initialize the progress-querying stuff to show no
+		   progress: */
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
+(u32) & (MCD_relocBuffDesc[channel]);
+		/* tbd - need to keep the user from trying to call the EU
+		   routine when MCD_INCLUDE_EU is not defined */
+		if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
+			/* TDTStart and TDTEnd */
+			MCD_taskTable[channel].TDTstart =
+			    MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
+			MCD_taskTable[channel].TDTend =
+			    MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
+			MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr,
+					       destIncr, dmaSize, xferSizeIncr,
+					       flags, (int *)
+					       &(MCD_relocBuffDesc[channel]),
+					       cSave, MCD_taskTable, channel);
+		} else {
+			/* TDTStart and TDTEnd */
+			MCD_taskTable[channel].TDTstart =
+			    MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
+			MCD_taskTable[channel].TDTend =
+			    MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
+			MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr,
+					     destIncr, dmaSize, xferSizeIncr,
+					     flags, (int *)
+					     &(MCD_relocBuffDesc[channel]),
+					     cSave, MCD_taskTable, channel);
+		}
+	} else {		/* chained DMAS */
+		/* Initialize the progress-querying stuff to show no
+		   progress: */
+#if 1
+		/* (!defined(MCD_NEED_ADDR_TRANS)) */
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
+		    = (int)((MCD_bufDesc *) srcAddr)->srcAddr;
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
+		    = (int)((MCD_bufDesc *) srcAddr)->destAddr;
+#else
+		/* if using address translation, need the virtual addr of the
+		   first buffdesc */
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
+		    = (int)((MCD_bufDesc *) srcAddrVirt)->srcAddr;
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
+		    = (int)((MCD_bufDesc *) srcAddrVirt)->destAddr;
+#endif
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
+		((volatile int *)MCD_taskTable[channel].
+		 contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
+
+		if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
+			/*TDTStart and TDTEnd */
+			MCD_taskTable[channel].TDTstart =
+			    MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
+			MCD_taskTable[channel].TDTend =
+			    MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
+			MCD_startDmaChainNoEu((int *)srcAddr, srcIncr,
+					      destIncr, xferSize,
+					      xferSizeIncr, cSave,
+					      MCD_taskTable, channel);
+		} else {
+			/*TDTStart and TDTEnd */
+			MCD_taskTable[channel].TDTstart =
+			    MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
+			MCD_taskTable[channel].TDTend =
+			    MCD_modelTaskTable[TASK_CHAINEU].TDTend;
+			MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr,
+					    xferSize, xferSizeIncr, cSave,
+					    MCD_taskTable, channel);
+		}
+	}
+	MCD_chStatus[channel] = MCD_IDLE;
+	return (MCD_OK);
+}
+
+/************************ End of MCD_startDma() *********************/
+
+/********************************************************************/
+/* Function:    MCD_XferProgrQuery
+ * Purpose:     Returns progress of DMA on requested channel
+ * Arguments:   channel - channel to retrieve progress for
+ *              progRep - pointer to user supplied MCD_XferProg struct
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *  MCD_XferProgrQuery() upon completing or after aborting a DMA, or
+ *  while the DMA is in progress, this function returns the first
+ *  DMA-destination address not (or not yet) used in the DMA. When
+ *  encountering a non-ready buffer descriptor, the information for
+ *  the last completed descriptor is returned.
+ *
+ *  MCD_XferProgQuery() has to avoid the possibility of getting
+ *  partially-updated information in the event that we should happen
+ *  to query DMA progress just as the DMA is updating it. It does that
+ *  by taking advantage of the fact context is not saved frequently for
+ *  the most part. We therefore read it at least twice until we get the
+ *  same information twice in a row.
+ *
+ *  Because a small, but not insignificant, amount of time is required
+ *  to write out the progress-query information, especially upon
+ *  completion of the DMA, it would be wise to guarantee some time lag
+ *  between successive readings of the progress-query information.
+ */
+
+/* How many iterations of the loop below to execute to stabilize values */
+#define STABTIME 0
+
+int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep)
+{
+	MCD_XferProg prevRep;
+	int again;		/* true if we are to try again to ge
+				   consistent results */
+	int i;			/* used as a time-waste counter */
+	int destDiffBytes;	/* Total no of bytes that we think actually
+				   got xfered. */
+	int numIterations;	/* number of iterations */
+	int bytesNotXfered;	/* bytes that did not get xfered. */
+	s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
+	int subModVal, addModVal;	/* Mode values to added and subtracted
+					   from the final destAddr */
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	/* Read a trial value for the progress-reporting values */
+	prevRep.lastSrcAddr =
+	    (s8 *) ((volatile int *)MCD_taskTable[channel].
+		    contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
+	prevRep.lastDestAddr =
+	    (s8 *) ((volatile int *)MCD_taskTable[channel].
+		    contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
+	prevRep.dmaSize =
+	    ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT +
+								      CSAVE_OFFSET];
+	prevRep.currBufDesc =
+	    (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
+			     contextSaveSpace)[CURRBD + CSAVE_OFFSET];
+	/* Repeatedly reread those values until they match previous values: */
+	do {
+		/* Waste a little bit of time to ensure stability: */
+		for (i = 0; i < STABTIME; i++) {
+			/* make sure this loop does something so that it
+			   doesn't get optimized out */
+			i += i >> 2;
+		}
+		/* Check them again: */
+		progRep->lastSrcAddr =
+		    (s8 *) ((volatile int *)MCD_taskTable[channel].
+			    contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
+		progRep->lastDestAddr =
+		    (s8 *) ((volatile int *)MCD_taskTable[channel].
+			    contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
+		progRep->dmaSize =
+		    ((volatile int *)MCD_taskTable[channel].
+		     contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
+		progRep->currBufDesc =
+		    (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
+				     contextSaveSpace)[CURRBD + CSAVE_OFFSET];
+		/* See if they match: */
+		if (prevRep.lastSrcAddr != progRep->lastSrcAddr
+		    || prevRep.lastDestAddr != progRep->lastDestAddr
+		    || prevRep.dmaSize != progRep->dmaSize
+		    || prevRep.currBufDesc != progRep->currBufDesc) {
+			/* If they don't match, remember previous values and
+			   try again: */
+			prevRep.lastSrcAddr = progRep->lastSrcAddr;
+			prevRep.lastDestAddr = progRep->lastDestAddr;
+			prevRep.dmaSize = progRep->dmaSize;
+			prevRep.currBufDesc = progRep->currBufDesc;
+			again = MCD_TRUE;
+		} else
+			again = MCD_FALSE;
+	} while (again == MCD_TRUE);
+
+	/* Update the dCount, srcAddr and destAddr */
+	/* To calculate dmaCount, we consider destination address. C
+	   overs M1,P1,Z for destination */
+	switch (MCD_remVariants.remDestRsdIncr[channel]) {
+	case MINUS1:
+		subModVal =
+		    ((int)progRep->
+		     lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
+				      1);
+		addModVal =
+		    ((int)progRep->currBufDesc->
+		     destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
+		LWAlignedInitDestAddr =
+		    (progRep->currBufDesc->destAddr) - addModVal;
+		LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
+		destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
+		bytesNotXfered =
+		    (destDiffBytes / MCD_remVariants.remDestIncr[channel]) *
+		    (MCD_remVariants.remDestIncr[channel]
+		     + MCD_remVariants.remXferSize[channel]);
+		progRep->dmaSize =
+		    destDiffBytes - bytesNotXfered + addModVal - subModVal;
+		break;
+	case ZERO:
+		progRep->lastDestAddr = progRep->currBufDesc->destAddr;
+		break;
+	case PLUS1:
+		/* This value has to be subtracted from the final
+		   calculated dCount. */
+		subModVal =
+		    ((int)progRep->currBufDesc->
+		     destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
+		/* These bytes are already in lastDestAddr. */
+		addModVal =
+		    ((int)progRep->
+		     lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
+				      1);
+		LWAlignedInitDestAddr =
+		    (progRep->currBufDesc->destAddr) - subModVal;
+		LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
+		destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
+		numIterations =
+		    (LWAlignedCurrDestAddr -
+		     LWAlignedInitDestAddr) /
+		    MCD_remVariants.remDestIncr[channel];
+		bytesNotXfered =
+		    numIterations * (MCD_remVariants.remDestIncr[channel]
+				     - MCD_remVariants.remXferSize[channel]);
+		progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
+		break;
+	default:
+		break;
+	}
+
+	/* This covers M1,P1,Z for source */
+	switch (MCD_remVariants.remSrcRsdIncr[channel]) {
+	case MINUS1:
+		progRep->lastSrcAddr =
+		    progRep->currBufDesc->srcAddr +
+		    (MCD_remVariants.remSrcIncr[channel] *
+		     (progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
+		break;
+	case ZERO:
+		progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
+		break;
+	case PLUS1:
+		progRep->lastSrcAddr =
+		    progRep->currBufDesc->srcAddr +
+		    (MCD_remVariants.remSrcIncr[channel] *
+		     (progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
+		break;
+	default:
+		break;
+	}
+
+	return (MCD_OK);
+}
+
+/******************* End of MCD_XferProgrQuery() ********************/
+
+/********************************************************************/
+/* MCD_resmActions() does the majority of the actions of a DMA resume.
+ * It is called from MCD_killDma() and MCD_resumeDma().  It has to be
+ * a separate function because the kill function has to negate the task
+ * enable before resuming it, but the resume function has to do nothing
+ * if there is no DMA on that channel (i.e., if the enable bit is 0).
+ */
+static void MCD_resmActions(int channel)
+{
+	MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
+	MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
+	/* This register is selected to know which initiator is
+	   actually asserted. */
+	MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
+
+	if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
+		MCD_chStatus[channel] = MCD_RUNNING;
+	else
+		MCD_chStatus[channel] = MCD_IDLE;
+}
+
+/********************* End of MCD_resmActions() *********************/
+
+/********************************************************************/
+/* Function:    MCD_killDma
+ * Purpose:     Halt the DMA on the requested channel, without any
+ *              intention of resuming the DMA.
+ * Arguments:   channel - requested channel
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *  A DMA may be killed from any state, including paused state, and it
+ *  always goes to the MCD_HALTED state even if it is killed while in
+ *  the MCD_NO_DMA or MCD_IDLE states.
+ */
+int MCD_killDma(int channel)
+{
+	/* MCD_XferProg progRep; */
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	MCD_dmaBar->taskControl[channel] = 0x0;
+	MCD_resumeDma(channel);
+	/*
+	 * This must be after the write to the TCR so that the task doesn't
+	 * start up again momentarily, and before the status assignment so
+	 * as to override whatever MCD_resumeDma() may do to the channel
+	 * status.
+	 */
+	MCD_chStatus[channel] = MCD_HALTED;
+
+	/*
+	 * Update the current buffer descriptor's lastDestAddr field
+	 *
+	 * MCD_XferProgrQuery (channel, &progRep);
+	 * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
+	 */
+	return (MCD_OK);
+}
+
+/************************ End of MCD_killDma() **********************/
+
+/********************************************************************/
+/* Function:    MCD_continDma
+ * Purpose:     Continue a DMA which as stopped due to encountering an
+ *              unready buffer descriptor.
+ * Arguments:   channel - channel to continue the DMA on
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *  This routine does not check to see if there is a task which can
+ *  be continued. Also this routine should not be used with single DMAs.
+ */
+int MCD_continDma(int channel)
+{
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
+	MCD_chStatus[channel] = MCD_RUNNING;
+
+	return (MCD_OK);
+}
+
+/********************** End of MCD_continDma() **********************/
+
+/*********************************************************************
+ * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
+ * to freeze a task and resume it.  We freeze a task by breakpointing
+ * on the stated task.  That is, not any specific place in the task,
+ * but any time that task executes.  In particular, when that task
+ * executes, we want to freeze that task and only that task.
+ *
+ * The bits of the debug control register influence interrupts vs.
+ * breakpoints as follows:
+ * - Bits 14 and 0 enable or disable debug functions.  If enabled, you
+ *   will get the interrupt but you may or may not get a breakpoint.
+ * - Bits 2 and 1 decide whether you also get a breakpoint in addition
+ *   to an interrupt.
+ *
+ * The debug unit can do these actions in response to either internally
+ * detected breakpoint conditions from the comparators, or in response
+ * to the external breakpoint pin, or both.
+ * - Bits 14 and 1 perform the above-described functions for
+ *   internally-generated conditions, i.e., the debug comparators.
+ * - Bits 0 and 2 perform the above-described functions for external
+ *   conditions, i.e., the breakpoint external pin.
+ *
+ * Note that, although you "always" get the interrupt when you turn
+ * the debug functions, the interrupt can nevertheless, if desired, be
+ * masked by the corresponding bit in the PTD's IMR. Note also that
+ * this means that bits 14 and 0 must enable debug functions before
+ * bits 1 and 2, respectively, have any effect.
+ *
+ * NOTE: It's extremely important to not pause more than one DMA channel
+ *  at a time.
+ ********************************************************************/
+
+/********************************************************************/
+/* Function:    MCD_pauseDma
+ * Purpose:     Pauses the DMA on a given channel (if any DMA is running
+ *              on that channel).
+ * Arguments:   channel
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ */
+int MCD_pauseDma(int channel)
+{
+	/* MCD_XferProg progRep; */
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) {
+		MCD_dmaBar->debugComp1 = channel;
+		MCD_dmaBar->debugControl =
+		    DBG_CTL_ENABLE | (1 << (channel + 16));
+		MCD_chStatus[channel] = MCD_PAUSED;
+
+		/*
+		 * Update the current buffer descriptor's lastDestAddr field
+		 *
+		 * MCD_XferProgrQuery (channel, &progRep);
+		 * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
+		 */
+	}
+	return (MCD_OK);
+}
+
+/************************* End of MCD_pauseDma() ********************/
+
+/********************************************************************/
+/* Function:    MCD_resumeDma
+ * Purpose:     Resumes the DMA on a given channel (if any DMA is
+ *              running on that channel).
+ * Arguments:   channel - channel on which to resume DMA
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ */
+int MCD_resumeDma(int channel)
+{
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
+		MCD_resmActions(channel);
+
+	return (MCD_OK);
+}
+
+/************************ End of MCD_resumeDma() ********************/
+
+/********************************************************************/
+/* Function:    MCD_csumQuery
+ * Purpose:     Provide the checksum after performing a non-chained DMA
+ * Arguments:   channel - channel to report on
+ *              csum - pointer to where to write the checksum/CRC
+ * Returns:     MCD_ERROR if the channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *
+ */
+int MCD_csumQuery(int channel, u32 * csum)
+{
+#ifdef MCD_INCLUDE_EU
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	*csum = MCD_relocBuffDesc[channel].csumResult;
+	return (MCD_OK);
+#else
+	return (MCD_ERROR);
+#endif
+}
+
+/*********************** End of MCD_resumeDma() *********************/
+
+/********************************************************************/
+/* Function:    MCD_getCodeSize
+ * Purpose:     Provide the size requirements of the microcoded tasks
+ * Returns:     Size in bytes
+ */
+int MCD_getCodeSize(void)
+{
+#ifdef MCD_INCLUDE_EU
+	return (0x2b5c);
+#else
+	return (0x173c);
+#endif
+}
+
+/********************** End of MCD_getCodeSize() ********************/
+
+/********************************************************************/
+/* Function:    MCD_getVersion
+ * Purpose:     Provide the version string and number
+ * Arguments:   longVersion - user supplied pointer to a pointer to a char
+ *                    which points to the version string
+ * Returns:     Version number and version string (by reference)
+ */
+char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
+#define MCD_REV_MAJOR   0x00
+#define MCD_REV_MINOR   0x03
+
+int MCD_getVersion(char **longVersion)
+{
+	*longVersion = MCD_versionString;
+	return ((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
+}
+
+/********************** End of MCD_getVersion() *********************/
+
+/********************************************************************/
+/* Private version of memcpy()
+ * Note that everything this is used for is longword-aligned.
+ */
+static void MCD_memcpy(int *dest, int *src, u32 size)
+{
+	u32 i;
+
+	for (i = 0; i < size; i += sizeof(int), dest++, src++)
+		*dest = *src;
+}
+#endif				/* CONFIG_FSLDMAFEC */
diff --git a/drivers/dma/MCD_tasks.c b/drivers/dma/MCD_tasks.c
new file mode 100644
index 0000000..694e780
--- /dev/null
+++ b/drivers/dma/MCD_tasks.c
@@ -0,0 +1,2428 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Contains task code and structures for Multi-channel DMA */
+
+#include <MCD_dma.h>
+
+u32 MCD_varTab0[];
+u32 MCD_varTab1[];
+u32 MCD_varTab2[];
+u32 MCD_varTab3[];
+u32 MCD_varTab4[];
+u32 MCD_varTab5[];
+u32 MCD_varTab6[];
+u32 MCD_varTab7[];
+u32 MCD_varTab8[];
+u32 MCD_varTab9[];
+u32 MCD_varTab10[];
+u32 MCD_varTab11[];
+u32 MCD_varTab12[];
+u32 MCD_varTab13[];
+u32 MCD_varTab14[];
+u32 MCD_varTab15[];
+
+u32 MCD_funcDescTab0[];
+#ifdef MCD_INCLUDE_EU
+u32 MCD_funcDescTab1[];
+u32 MCD_funcDescTab2[];
+u32 MCD_funcDescTab3[];
+u32 MCD_funcDescTab4[];
+u32 MCD_funcDescTab5[];
+u32 MCD_funcDescTab6[];
+u32 MCD_funcDescTab7[];
+u32 MCD_funcDescTab8[];
+u32 MCD_funcDescTab9[];
+u32 MCD_funcDescTab10[];
+u32 MCD_funcDescTab11[];
+u32 MCD_funcDescTab12[];
+u32 MCD_funcDescTab13[];
+u32 MCD_funcDescTab14[];
+u32 MCD_funcDescTab15[];
+#endif
+
+u32 MCD_contextSave0[];
+u32 MCD_contextSave1[];
+u32 MCD_contextSave2[];
+u32 MCD_contextSave3[];
+u32 MCD_contextSave4[];
+u32 MCD_contextSave5[];
+u32 MCD_contextSave6[];
+u32 MCD_contextSave7[];
+u32 MCD_contextSave8[];
+u32 MCD_contextSave9[];
+u32 MCD_contextSave10[];
+u32 MCD_contextSave11[];
+u32 MCD_contextSave12[];
+u32 MCD_contextSave13[];
+u32 MCD_contextSave14[];
+u32 MCD_contextSave15[];
+
+u32 MCD_realTaskTableSrc[] = {
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab0,	/* Task 0 Variable Table */
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave0,	/* Task 0 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab1,	/* Task 1 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab1,	/* Task 1 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave1,	/* Task 1 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab2,	/* Task 2 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab2,	/* Task 2 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave2,	/* Task 2 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab3,	/* Task 3 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab3,	/* Task 3 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave3,	/* Task 3 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab4,	/* Task 4 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab4,	/* Task 4 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave4,	/* Task 4 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab5,	/* Task 5 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab5,	/* Task 5 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave5,	/* Task 5 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab6,	/* Task 6 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab6,	/* Task 6 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave6,	/* Task 6 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab7,	/* Task 7 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab7,	/* Task 7 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave7,	/* Task 7 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab8,	/* Task 8 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab8,	/* Task 8 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave8,	/* Task 8 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab9,	/* Task 9 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab9,	/* Task 9 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave9,	/* Task 9 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab10,	/* Task 10 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab10,	/* Task 10 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave10,	/* Task 10 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab11,	/* Task 11 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab11,	/* Task 11 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave11,	/* Task 11 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab12,	/* Task 12 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab12,	/* Task 12 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave12,	/* Task 12 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab13,	/* Task 13 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab13,	/* Task 13 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave13,	/* Task 13 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab14,	/* Task 14 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab14,	/* Task 14 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave14,	/* Task 14 context save space */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_varTab15,	/* Task 15 Variable Table */
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_funcDescTab15,	/* Task 15 Fn Desc. Table & Flags */
+#else
+	(u32) MCD_funcDescTab0,	/* Task 0 Fn Desc. Table & Flags */
+#endif
+	0x00000000,
+	0x00000000,
+	(u32) MCD_contextSave15,	/* Task 15 context save space */
+	0x00000000,
+};
+
+u32 MCD_varTab0[] = {		/* Task 0 Variable Table */
+	0x00000000,		/* var[0] */
+	0x00000000,		/* var[1] */
+	0x00000000,		/* var[2] */
+	0x00000000,		/* var[3] */
+	0x00000000,		/* var[4] */
+	0x00000000,		/* var[5] */
+	0x00000000,		/* var[6] */
+	0x00000000,		/* var[7] */
+	0x00000000,		/* var[8] */
+	0x00000000,		/* var[9] */
+	0x00000000,		/* var[10] */
+	0x00000000,		/* var[11] */
+	0x00000000,		/* var[12] */
+	0x00000000,		/* var[13] */
+	0x00000000,		/* var[14] */
+	0x00000000,		/* var[15] */
+	0x00000000,		/* var[16] */
+	0x00000000,		/* var[17] */
+	0x00000000,		/* var[18] */
+	0x00000000,		/* var[19] */
+	0x00000000,		/* var[20] */
+	0x00000000,		/* var[21] */
+	0x00000000,		/* var[22] */
+	0x00000000,		/* var[23] */
+	0xe0000000,		/* inc[0] */
+	0x20000000,		/* inc[1] */
+	0x2000ffff,		/* inc[2] */
+	0x00000000,		/* inc[3] */
+	0x00000000,		/* inc[4] */
+	0x00000000,		/* inc[5] */
+	0x00000000,		/* inc[6] */
+	0x00000000,		/* inc[7] */
+};
+
+u32 MCD_varTab1[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab2[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab3[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab4[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab5[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab6[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab7[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab8[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab9[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab10[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab11[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab12[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab13[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab14[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_varTab15[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xe0000000,
+	0x20000000,
+	0x2000ffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_funcDescTab0[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+#ifdef MCD_INCLUDE_EU
+u32 MCD_funcDescTab1[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab2[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab3[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab4[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab5[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab6[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab7[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab8[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab9[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab10[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab11[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab12[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab13[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab14[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+
+u32 MCD_funcDescTab15[] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xa0045670,
+	0xa0000000,
+	0xa0000000,
+	0x20000000,
+	0x21800000,
+	0x21e00000,
+	0x20400000,
+	0x20500000,
+	0x205a0000,
+	0x20a00000,
+	0x202fa000,
+	0x202f9000,
+	0x202ea000,
+	0x202da000,
+	0x202e2000,
+	0x202f2000,
+};
+#endif				/*MCD_INCLUDE_EU */
+
+u32 MCD_contextSave0[128];	/* Task 0 context save space */
+u32 MCD_contextSave1[128];	/* Task 1 context save space */
+u32 MCD_contextSave2[128];	/* Task 2 context save space */
+u32 MCD_contextSave3[128];	/* Task 3 context save space */
+u32 MCD_contextSave4[128];	/* Task 4 context save space */
+u32 MCD_contextSave5[128];	/* Task 5 context save space */
+u32 MCD_contextSave6[128];	/* Task 6 context save space */
+u32 MCD_contextSave7[128];	/* Task 7 context save space */
+u32 MCD_contextSave8[128];	/* Task 8 context save space */
+u32 MCD_contextSave9[128];	/* Task 9 context save space */
+u32 MCD_contextSave10[128];	/* Task 10 context save space */
+u32 MCD_contextSave11[128];	/* Task 11 context save space */
+u32 MCD_contextSave12[128];	/* Task 12 context save space */
+u32 MCD_contextSave13[128];	/* Task 13 context save space */
+u32 MCD_contextSave14[128];	/* Task 14 context save space */
+u32 MCD_contextSave15[128];	/* Task 15 context save space */
+
+u32 MCD_ChainNoEu_TDT[];
+u32 MCD_SingleNoEu_TDT[];
+#ifdef MCD_INCLUDE_EU
+u32 MCD_ChainEu_TDT[];
+u32 MCD_SingleEu_TDT[];
+#endif
+u32 MCD_ENetRcv_TDT[];
+u32 MCD_ENetXmit_TDT[];
+
+u32 MCD_modelTaskTableSrc[] = {
+	(u32) MCD_ChainNoEu_TDT,
+	(u32) & ((u8 *) MCD_ChainNoEu_TDT)[0x0000016c],
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_SingleNoEu_TDT,
+	(u32) & ((u8 *) MCD_SingleNoEu_TDT)[0x000000d4],
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+#ifdef MCD_INCLUDE_EU
+	(u32) MCD_ChainEu_TDT,
+	(u32) & ((u8 *) MCD_ChainEu_TDT)[0x000001b4],
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_SingleEu_TDT,
+	(u32) & ((u8 *) MCD_SingleEu_TDT)[0x00000124],
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+#endif
+	(u32) MCD_ENetRcv_TDT,
+	(u32) & ((u8 *) MCD_ENetRcv_TDT)[0x0000009c],
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	(u32) MCD_ENetXmit_TDT,
+	(u32) & ((u8 *) MCD_ENetXmit_TDT)[0x000000d0],
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+u32 MCD_ChainNoEu_TDT[] = {
+	0x80004000,
+	0x8118801b,
+	0xb8c60018,
+	0x10002b10,
+	0x7000000d,
+	0x018cf89f,
+	0x6000000a,
+	0x080cf89f,
+	0x000001f8,
+	0x98180364,
+	0x8118801b,
+	0xf8c6001a,
+	0xb8c6601b,
+	0x10002710,
+	0x00000f18,
+	0xb8c6001d,
+	0x10001310,
+	0x60000007,
+	0x014cf88b,
+	0x98c6001c,
+	0x00000710,
+	0x98c70018,
+	0x10001f10,
+	0x0000c818,
+	0x000001f8,
+	0xc1476018,
+	0xc003231d,
+	0x811a601b,
+	0xc1862102,
+	0x849be009,
+	0x03fed7b8,
+	0xda9b001b,
+	0x9b9be01b,
+	0x1000cb20,
+	0x70000006,
+	0x088cf88f,
+	0x1000cb28,
+	0x70000006,
+	0x088cf88f,
+	0x1000cb30,
+	0x70000006,
+	0x088cf88f,
+	0x1000cb38,
+	0x0000c728,
+	0x000001f8,
+	0xc1476018,
+	0xc003241d,
+	0x811a601b,
+	0xda9b001b,
+	0x9b9be01b,
+	0x0000d3a0,
+	0xc1862102,
+	0x849be009,
+	0x0bfed7b8,
+	0xda9b001b,
+	0x9b9be01b,
+	0x1000cb20,
+	0x70000006,
+	0x088cf88f,
+	0x1000cb28,
+	0x70000006,
+	0x088cf88f,
+	0x1000cb30,
+	0x70000006,
+	0x088cf88f,
+	0x1000cb38,
+	0x0000c728,
+	0x000001f8,
+	0x8118801b,
+	0xd8c60018,
+	0x98c6601c,
+	0x6000000b,
+	0x0c8cfc9f,
+	0x000001f8,
+	0xa146001e,
+	0x10000b08,
+	0x10002050,
+	0xb8c60018,
+	0x10002b10,
+	0x7000000a,
+	0x080cf89f,
+	0x6000000d,
+	0x018cf89f,
+	0x000001f8,
+	0x8618801b,
+	0x7000000e,
+	0x084cf21f,
+	0xd8990336,
+	0x8019801b,
+	0x040001f8,
+	0x000001f8,
+	0x000001f8,
+};
+
+u32 MCD_SingleNoEu_TDT[] = {
+	0x8198001b,
+	0x7000000d,
+	0x080cf81f,
+	0x8198801b,
+	0x6000000e,
+	0x084cf85f,
+	0x000001f8,
+	0x8298001b,
+	0x7000000d,
+	0x010cf81f,
+	0x6000000e,
+	0x018cf81f,
+	0xc202601b,
+	0xc002221c,
+	0x809a601b,
+	0xc10420c2,
+	0x839be009,
+	0x03fed7b8,
+	0xda9b001b,
+	0x9b9be01b,
+	0x70000006,
+	0x088cf889,
+	0x1000cb28,
+	0x70000006,
+	0x088cf889,
+	0x1000cb30,
+	0x70000006,
+	0x088cf889,
+	0x0000cb38,
+	0x000001f8,
+	0xc202601b,
+	0xc002229c,
+	0x809a601b,
+	0xda9b001b,
+	0x9b9be01b,
+	0x0000d3a0,
+	0xc10420c2,
+	0x839be009,
+	0x0bfed7b8,
+	0xda9b001b,
+	0x9b9be01b,
+	0x70000006,
+	0x088cf889,
+	0x1000cb28,
+	0x70000006,
+	0x088cf889,
+	0x1000cb30,
+	0x70000006,
+	0x088cf889,
+	0x0000cb38,
+	0x000001f8,
+	0xc318022d,
+	0x8018801b,
+	0x040001f8,
+};
+
+#ifdef MCD_INCLUDE_EU
+u32 MCD_ChainEu_TDT[] = {
+	0x80004000,
+	0x8198801b,
+	0xb8c68018,
+	0x10002f10,
+	0x7000000d,
+	0x01ccf89f,
+	0x6000000a,
+	0x080cf89f,
+	0x000001f8,
+	0x981803a4,
+	0x8198801b,
+	0xf8c6801a,
+	0xb8c6e01b,
+	0x10002b10,
+	0x00001318,
+	0xb8c6801d,
+	0x10001710,
+	0x60000007,
+	0x018cf88c,
+	0x98c6801c,
+	0x00000b10,
+	0x98c78018,
+	0x10002310,
+	0x0000c820,
+	0x000001f8,
+	0x8698801b,
+	0x7000000f,
+	0x084cf2df,
+	0xd899042d,
+	0x8019801b,
+	0x60000003,
+	0x2cd7c7df,
+	0xd8990364,
+	0x8019801b,
+	0x60000003,
+	0x2c17c7df,
+	0x000001f8,
+	0xc1c7e018,
+	0xc003a35e,
+	0x819a601b,
+	0xc206a142,
+	0x851be009,
+	0x63fe0000,
+	0x0d4cfddf,
+	0xda9b001b,
+	0x9b9be01b,
+	0x70000002,
+	0x004cf81f,
+	0x1000cb20,
+	0x70000006,
+	0x088cf891,
+	0x1000cb28,
+	0x70000006,
+	0x088cf891,
+	0x1000cb30,
+	0x70000006,
+	0x088cf891,
+	0x1000cb38,
+	0x0000c728,
+	0x000001f8,
+	0xc1c7e018,
+	0xc003a49e,
+	0x819a601b,
+	0xda9b001b,
+	0x9b9be01b,
+	0x0000d3a0,
+	0xc206a142,
+	0x851be009,
+	0x6bfe0000,
+	0x0d4cfddf,
+	0xda9b001b,
+	0x9b9be01b,
+	0x70000002,
+	0x004cf81f,
+	0x1000cb20,
+	0x70000006,
+	0x088cf891,
+	0x1000cb28,
+	0x70000006,
+	0x088cf891,
+	0x1000cb30,
+	0x70000006,
+	0x088cf891,
+	0x1000cb38,
+	0x0000c728,
+	0x000001f8,
+	0x8198801b,
+	0xd8c68018,
+	0x98c6e01c,
+	0x6000000b,
+	0x0c8cfc9f,
+	0x0000cc08,
+	0xa1c6801e,
+	0x10000f08,
+	0x10002458,
+	0xb8c68018,
+	0x10002f10,
+	0x7000000a,
+	0x080cf89f,
+	0x6000000d,
+	0x01ccf89f,
+	0x000001f8,
+	0x8698801b,
+	0x7000000e,
+	0x084cf25f,
+	0xd899037f,
+	0x8019801b,
+	0x040001f8,
+	0x000001f8,
+	0x000001f8,
+};
+
+u32 MCD_SingleEu_TDT[] = {
+	0x8218001b,
+	0x7000000d,
+	0x080cf81f,
+	0x8218801b,
+	0x6000000e,
+	0x084cf85f,
+	0x000001f8,
+	0x8318001b,
+	0x7000000d,
+	0x014cf81f,
+	0x6000000e,
+	0x01ccf81f,
+	0x8498001b,
+	0x7000000f,
+	0x080cf19f,
+	0xd81882a4,
+	0x8019001b,
+	0x60000003,
+	0x2c97c7df,
+	0xd818826d,
+	0x8019001b,
+	0x60000003,
+	0x2c17c7df,
+	0x000001f8,
+	0xc282e01b,
+	0xc002a25e,
+	0x811a601b,
+	0xc184a102,
+	0x841be009,
+	0x63fe0000,
+	0x0d4cfddf,
+	0xda9b001b,
+	0x9b9be01b,
+	0x70000002,
+	0x004cf99f,
+	0x70000006,
+	0x088cf88b,
+	0x1000cb28,
+	0x70000006,
+	0x088cf88b,
+	0x1000cb30,
+	0x70000006,
+	0x088cf88b,
+	0x0000cb38,
+	0x000001f8,
+	0xc282e01b,
+	0xc002a31e,
+	0x811a601b,
+	0xda9b001b,
+	0x9b9be01b,
+	0x0000d3a0,
+	0xc184a102,
+	0x841be009,
+	0x6bfe0000,
+	0x0d4cfddf,
+	0xda9b001b,
+	0x9b9be01b,
+	0x70000002,
+	0x004cf99f,
+	0x70000006,
+	0x088cf88b,
+	0x1000cb28,
+	0x70000006,
+	0x088cf88b,
+	0x1000cb30,
+	0x70000006,
+	0x088cf88b,
+	0x0000cb38,
+	0x000001f8,
+	0x8144801c,
+	0x0000c008,
+	0xc398027f,
+	0x8018801b,
+	0x040001f8,
+};
+#endif
+u32 MCD_ENetRcv_TDT[] = {
+	0x80004000,
+	0x81988000,
+	0x10000788,
+	0x6000000a,
+	0x080cf05f,
+	0x98180209,
+	0x81c40004,
+	0x7000000e,
+	0x010cf05f,
+	0x7000000c,
+	0x01ccf05f,
+	0x70000004,
+	0x014cf049,
+	0x70000004,
+	0x004cf04a,
+	0x00000b88,
+	0xc4030150,
+	0x8119e012,
+	0x03e0cf90,
+	0x81188000,
+	0x000ac788,
+	0xc4030000,
+	0x8199e000,
+	0x70000004,
+	0x084cfc8b,
+	0x60000005,
+	0x0cccf841,
+	0x81c60000,
+	0xc399021b,
+	0x80198000,
+	0x00008400,
+	0x00000f08,
+	0x81988000,
+	0x10000788,
+	0x6000000a,
+	0x080cf05f,
+	0xc2188209,
+	0x80190000,
+	0x040001f8,
+	0x000001f8,
+};
+
+u32 MCD_ENetXmit_TDT[] = {
+	0x80004000,
+	0x81988000,
+	0x10000788,
+	0x6000000a,
+	0x080cf05f,
+	0x98180309,
+	0x80004003,
+	0x81c60004,
+	0x7000000e,
+	0x014cf05f,
+	0x7000000c,
+	0x028cf05f,
+	0x7000000d,
+	0x018cf05f,
+	0x70000004,
+	0x01ccf04d,
+	0x10000b90,
+	0x60000004,
+	0x020cf0a1,
+	0xc3188312,
+	0x83c70000,
+	0x00001f10,
+	0xc583a3c3,
+	0x81042325,
+	0x03e0c798,
+	0xd8990000,
+	0x9999e000,
+	0x000acf98,
+	0xd8992306,
+	0x9999e03f,
+	0x03eac798,
+	0xd8990000,
+	0x9999e000,
+	0x000acf98,
+	0xd8990000,
+	0x99832302,
+	0x0beac798,
+	0x81988000,
+	0x6000000b,
+	0x0c4cfc5f,
+	0x81c80000,
+	0xc5190312,
+	0x80198000,
+	0x00008400,
+	0x00000f08,
+	0x81988000,
+	0x10000788,
+	0x6000000a,
+	0x080cf05f,
+	0xc2988309,
+	0x80190000,
+	0x040001f8,
+	0x000001f8,
+};
+
+#ifdef MCD_INCLUDE_EU
+MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
+#endif
diff --git a/drivers/dma/MCD_tasksInit.c b/drivers/dma/MCD_tasksInit.c
new file mode 100644
index 0000000..0d28713
--- /dev/null
+++ b/drivers/dma/MCD_tasksInit.c
@@ -0,0 +1,247 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Functions for initializing variable tables of different types of tasks. */
+
+/*
+ * Do not edit!
+ */
+
+#ifdef CONFIG_FSLDMAFEC
+
+#include <MCD_dma.h>
+
+extern dmaRegs *MCD_dmaBar;
+
+/* Task 0 */
+
+void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
+			   int xferSize, short xferSizeIncr, int *cSave,
+			   volatile TaskTableEntry * taskTable, int channel)
+{
+	volatile TaskTableEntry *taskChan = taskTable + channel;
+
+	MCD_SET_VAR(taskChan, 2, (u32) currBD);	/* var[2] */
+	MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr));	/* inc[1] */
+	MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr));	/* inc[0] */
+	MCD_SET_VAR(taskChan, 11, (u32) xferSize);	/* var[11] */
+	MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr));	/* inc[2] */
+	MCD_SET_VAR(taskChan, 0, (u32) cSave);	/* var[0] */
+	MCD_SET_VAR(taskChan, 1, (u32) 0x00000000);	/* var[1] */
+	MCD_SET_VAR(taskChan, 3, (u32) 0x00000000);	/* var[3] */
+	MCD_SET_VAR(taskChan, 4, (u32) 0x00000000);	/* var[4] */
+	MCD_SET_VAR(taskChan, 5, (u32) 0x00000000);	/* var[5] */
+	MCD_SET_VAR(taskChan, 6, (u32) 0x00000000);	/* var[6] */
+	MCD_SET_VAR(taskChan, 7, (u32) 0x00000000);	/* var[7] */
+	MCD_SET_VAR(taskChan, 8, (u32) 0x00000000);	/* var[8] */
+	MCD_SET_VAR(taskChan, 9, (u32) 0x00000000);	/* var[9] */
+	MCD_SET_VAR(taskChan, 10, (u32) 0x00000000);	/* var[10] */
+	MCD_SET_VAR(taskChan, 12, (u32) 0x00000000);	/* var[12] */
+	MCD_SET_VAR(taskChan, 13, (u32) 0x80000000);	/* var[13] */
+	MCD_SET_VAR(taskChan, 14, (u32) 0x00000010);	/* var[14] */
+	MCD_SET_VAR(taskChan, 15, (u32) 0x00000004);	/* var[15] */
+	MCD_SET_VAR(taskChan, 16, (u32) 0x08000000);	/* var[16] */
+	MCD_SET_VAR(taskChan, 27, (u32) 0x00000000);	/* inc[3] */
+	MCD_SET_VAR(taskChan, 28, (u32) 0x80000000);	/* inc[4] */
+	MCD_SET_VAR(taskChan, 29, (u32) 0x80000001);	/* inc[5] */
+	MCD_SET_VAR(taskChan, 30, (u32) 0x40000000);	/* inc[6] */
+
+	/* Set the task's Enable bit in its Task Control Register */
+	MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
+}
+
+/* Task 1 */
+
+void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
+			    short destIncr, int dmaSize, short xferSizeIncr,
+			    int flags, int *currBD, int *cSave,
+			    volatile TaskTableEntry * taskTable, int channel)
+{
+	volatile TaskTableEntry *taskChan = taskTable + channel;
+
+	MCD_SET_VAR(taskChan, 7, (u32) srcAddr);	/* var[7] */
+	MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr));	/* inc[1] */
+	MCD_SET_VAR(taskChan, 2, (u32) destAddr);	/* var[2] */
+	MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr));	/* inc[0] */
+	MCD_SET_VAR(taskChan, 3, (u32) dmaSize);	/* var[3] */
+	MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr));	/* inc[2] */
+	MCD_SET_VAR(taskChan, 5, (u32) flags);	/* var[5] */
+	MCD_SET_VAR(taskChan, 1, (u32) currBD);	/* var[1] */
+	MCD_SET_VAR(taskChan, 0, (u32) cSave);	/* var[0] */
+	MCD_SET_VAR(taskChan, 4, (u32) 0x00000000);	/* var[4] */
+	MCD_SET_VAR(taskChan, 6, (u32) 0x00000000);	/* var[6] */
+	MCD_SET_VAR(taskChan, 8, (u32) 0x00000000);	/* var[8] */
+	MCD_SET_VAR(taskChan, 9, (u32) 0x00000004);	/* var[9] */
+	MCD_SET_VAR(taskChan, 10, (u32) 0x08000000);	/* var[10] */
+	MCD_SET_VAR(taskChan, 27, (u32) 0x00000000);	/* inc[3] */
+	MCD_SET_VAR(taskChan, 28, (u32) 0x80000001);	/* inc[4] */
+	MCD_SET_VAR(taskChan, 29, (u32) 0x40000000);	/* inc[5] */
+
+	/* Set the task's Enable bit in its Task Control Register */
+	MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
+}
+
+/* Task 2 */
+
+void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
+			 int xferSize, short xferSizeIncr, int *cSave,
+			 volatile TaskTableEntry * taskTable, int channel)
+{
+	volatile TaskTableEntry *taskChan = taskTable + channel;
+
+	MCD_SET_VAR(taskChan, 3, (u32) currBD);	/* var[3] */
+	MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr));	/* inc[1] */
+	MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr));	/* inc[0] */
+	MCD_SET_VAR(taskChan, 12, (u32) xferSize);	/* var[12] */
+	MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr));	/* inc[2] */
+	MCD_SET_VAR(taskChan, 0, (u32) cSave);	/* var[0] */
+	MCD_SET_VAR(taskChan, 1, (u32) 0x00000000);	/* var[1] */
+	MCD_SET_VAR(taskChan, 2, (u32) 0x00000000);	/* var[2] */
+	MCD_SET_VAR(taskChan, 4, (u32) 0x00000000);	/* var[4] */
+	MCD_SET_VAR(taskChan, 5, (u32) 0x00000000);	/* var[5] */
+	MCD_SET_VAR(taskChan, 6, (u32) 0x00000000);	/* var[6] */
+	MCD_SET_VAR(taskChan, 7, (u32) 0x00000000);	/* var[7] */
+	MCD_SET_VAR(taskChan, 8, (u32) 0x00000000);	/* var[8] */
+	MCD_SET_VAR(taskChan, 9, (u32) 0x00000000);	/* var[9] */
+	MCD_SET_VAR(taskChan, 10, (u32) 0x00000000);	/* var[10] */
+	MCD_SET_VAR(taskChan, 11, (u32) 0x00000000);	/* var[11] */
+	MCD_SET_VAR(taskChan, 13, (u32) 0x00000000);	/* var[13] */
+	MCD_SET_VAR(taskChan, 14, (u32) 0x80000000);	/* var[14] */
+	MCD_SET_VAR(taskChan, 15, (u32) 0x00000010);	/* var[15] */
+	MCD_SET_VAR(taskChan, 16, (u32) 0x00000001);	/* var[16] */
+	MCD_SET_VAR(taskChan, 17, (u32) 0x00000004);	/* var[17] */
+	MCD_SET_VAR(taskChan, 18, (u32) 0x08000000);	/* var[18] */
+	MCD_SET_VAR(taskChan, 27, (u32) 0x00000000);	/* inc[3] */
+	MCD_SET_VAR(taskChan, 28, (u32) 0x80000000);	/* inc[4] */
+	MCD_SET_VAR(taskChan, 29, (u32) 0xc0000000);	/* inc[5] */
+	MCD_SET_VAR(taskChan, 30, (u32) 0x80000001);	/* inc[6] */
+	MCD_SET_VAR(taskChan, 31, (u32) 0x40000000);	/* inc[7] */
+
+	/* Set the task's Enable bit in its Task Control Register */
+	MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
+}
+
+/* Task 3 */
+
+void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
+			  short destIncr, int dmaSize, short xferSizeIncr,
+			  int flags, int *currBD, int *cSave,
+			  volatile TaskTableEntry * taskTable, int channel)
+{
+	volatile TaskTableEntry *taskChan = taskTable + channel;
+
+	MCD_SET_VAR(taskChan, 8, (u32) srcAddr);	/* var[8] */
+	MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr));	/* inc[1] */
+	MCD_SET_VAR(taskChan, 3, (u32) destAddr);	/* var[3] */
+	MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr));	/* inc[0] */
+	MCD_SET_VAR(taskChan, 4, (u32) dmaSize);	/* var[4] */
+	MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr));	/* inc[2] */
+	MCD_SET_VAR(taskChan, 6, (u32) flags);	/* var[6] */
+	MCD_SET_VAR(taskChan, 2, (u32) currBD);	/* var[2] */
+	MCD_SET_VAR(taskChan, 0, (u32) cSave);	/* var[0] */
+	MCD_SET_VAR(taskChan, 1, (u32) 0x00000000);	/* var[1] */
+	MCD_SET_VAR(taskChan, 5, (u32) 0x00000000);	/* var[5] */
+	MCD_SET_VAR(taskChan, 7, (u32) 0x00000000);	/* var[7] */
+	MCD_SET_VAR(taskChan, 9, (u32) 0x00000000);	/* var[9] */
+	MCD_SET_VAR(taskChan, 10, (u32) 0x00000001);	/* var[10] */
+	MCD_SET_VAR(taskChan, 11, (u32) 0x00000004);	/* var[11] */
+	MCD_SET_VAR(taskChan, 12, (u32) 0x08000000);	/* var[12] */
+	MCD_SET_VAR(taskChan, 27, (u32) 0x00000000);	/* inc[3] */
+	MCD_SET_VAR(taskChan, 28, (u32) 0xc0000000);	/* inc[4] */
+	MCD_SET_VAR(taskChan, 29, (u32) 0x80000000);	/* inc[5] */
+	MCD_SET_VAR(taskChan, 30, (u32) 0x80000001);	/* inc[6] */
+	MCD_SET_VAR(taskChan, 31, (u32) 0x40000000);	/* inc[7] */
+
+	/* Set the task's Enable bit in its Task Control Register */
+	MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
+}
+
+/* Task 4 */
+
+void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
+			 volatile TaskTableEntry * taskTable, int channel)
+{
+	volatile TaskTableEntry *taskChan = taskTable + channel;
+
+	MCD_SET_VAR(taskChan, 0, (u32) bDBase);	/* var[0] */
+	MCD_SET_VAR(taskChan, 3, (u32) currBD);	/* var[3] */
+	MCD_SET_VAR(taskChan, 6, (u32) rcvFifoPtr);	/* var[6] */
+	MCD_SET_VAR(taskChan, 1, (u32) 0x00000000);	/* var[1] */
+	MCD_SET_VAR(taskChan, 2, (u32) 0x00000000);	/* var[2] */
+	MCD_SET_VAR(taskChan, 4, (u32) 0x00000000);	/* var[4] */
+	MCD_SET_VAR(taskChan, 5, (u32) 0x00000000);	/* var[5] */
+	MCD_SET_VAR(taskChan, 7, (u32) 0x00000000);	/* var[7] */
+	MCD_SET_VAR(taskChan, 8, (u32) 0x00000000);	/* var[8] */
+	MCD_SET_VAR(taskChan, 9, (u32) 0x0000ffff);	/* var[9] */
+	MCD_SET_VAR(taskChan, 10, (u32) 0x30000000);	/* var[10] */
+	MCD_SET_VAR(taskChan, 11, (u32) 0x0fffffff);	/* var[11] */
+	MCD_SET_VAR(taskChan, 12, (u32) 0x00000008);	/* var[12] */
+	MCD_SET_VAR(taskChan, 24, (u32) 0x00000000);	/* inc[0] */
+	MCD_SET_VAR(taskChan, 25, (u32) 0x60000000);	/* inc[1] */
+	MCD_SET_VAR(taskChan, 26, (u32) 0x20000004);	/* inc[2] */
+	MCD_SET_VAR(taskChan, 27, (u32) 0x40000000);	/* inc[3] */
+
+	/* Set the task's Enable bit in its Task Control Register */
+	MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
+}
+
+/* Task 5 */
+
+void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
+			  volatile TaskTableEntry * taskTable, int channel)
+{
+	volatile TaskTableEntry *taskChan = taskTable + channel;
+
+	MCD_SET_VAR(taskChan, 0, (u32) bDBase);	/* var[0] */
+	MCD_SET_VAR(taskChan, 3, (u32) currBD);	/* var[3] */
+	MCD_SET_VAR(taskChan, 11, (u32) xmitFifoPtr);	/* var[11] */
+	MCD_SET_VAR(taskChan, 1, (u32) 0x00000000);	/* var[1] */
+	MCD_SET_VAR(taskChan, 2, (u32) 0x00000000);	/* var[2] */
+	MCD_SET_VAR(taskChan, 4, (u32) 0x00000000);	/* var[4] */
+	MCD_SET_VAR(taskChan, 5, (u32) 0x00000000);	/* var[5] */
+	MCD_SET_VAR(taskChan, 6, (u32) 0x00000000);	/* var[6] */
+	MCD_SET_VAR(taskChan, 7, (u32) 0x00000000);	/* var[7] */
+	MCD_SET_VAR(taskChan, 8, (u32) 0x00000000);	/* var[8] */
+	MCD_SET_VAR(taskChan, 9, (u32) 0x00000000);	/* var[9] */
+	MCD_SET_VAR(taskChan, 10, (u32) 0x00000000);	/* var[10] */
+	MCD_SET_VAR(taskChan, 12, (u32) 0x00000000);	/* var[12] */
+	MCD_SET_VAR(taskChan, 13, (u32) 0x0000ffff);	/* var[13] */
+	MCD_SET_VAR(taskChan, 14, (u32) 0xffffffff);	/* var[14] */
+	MCD_SET_VAR(taskChan, 15, (u32) 0x00000004);	/* var[15] */
+	MCD_SET_VAR(taskChan, 16, (u32) 0x00000008);	/* var[16] */
+	MCD_SET_VAR(taskChan, 24, (u32) 0x00000000);	/* inc[0] */
+	MCD_SET_VAR(taskChan, 25, (u32) 0x60000000);	/* inc[1] */
+	MCD_SET_VAR(taskChan, 26, (u32) 0x40000000);	/* inc[2] */
+	MCD_SET_VAR(taskChan, 27, (u32) 0xc000fffc);	/* inc[3] */
+	MCD_SET_VAR(taskChan, 28, (u32) 0xe0000004);	/* inc[4] */
+	MCD_SET_VAR(taskChan, 29, (u32) 0x80000000);	/* inc[5] */
+	MCD_SET_VAR(taskChan, 30, (u32) 0x4000ffff);	/* inc[6] */
+	MCD_SET_VAR(taskChan, 31, (u32) 0xe0000001);	/* inc[7] */
+
+	/* Set the task's Enable bit in its Task Control Register */
+	MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
+}
+
+#endif			/* CONFIG_FSLDMAFEC */
+
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
new file mode 100644
index 0000000..2dd5a0e
--- /dev/null
+++ b/drivers/dma/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB 	:= $(obj)libdma.a
+
+COBJS-y += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
+
+COBJS	:= $(COBJS-y)
+SRCS 	:= $(COBJS:.o=.c)
+OBJS 	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 41e1bde..b9723fa 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -33,6 +33,7 @@ COBJS-y += dm9000x.o
 COBJS-y += e1000.o
 COBJS-y += eepro100.o
 COBJS-y += enc28j60.o
+COBJS-y += fsl_mcdmafec.o
 COBJS-y += inca-ip_sw.o
 COBJS-y += ks8695eth.o
 COBJS-y += lan91c96.o
diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
new file mode 100644
index 0000000..0c876f3
--- /dev/null
+++ b/drivers/net/fsl_mcdmafec.c
@@ -0,0 +1,571 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <command.h>
+#include <config.h>
+#include <net.h>
+#include <miiphy.h>
+
+#ifdef CONFIG_FSLDMAFEC
+#undef	ET_DEBUG
+#undef	MII_DEBUG
+
+/* Ethernet Transmit and Receive Buffers */
+#define DBUF_LENGTH		1520
+#define PKT_MAXBUF_SIZE		1518
+#define PKT_MINBUF_SIZE		64
+#define PKT_MAXBLR_SIZE		1536
+#define LAST_PKTBUFSRX		PKTBUFSRX - 1
+#define BD_ENET_RX_W_E		(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
+#define BD_ENET_TX_RDY_LST	(BD_ENET_TX_READY | BD_ENET_TX_LAST)
+#define FIFO_ERRSTAT		(FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
+
+/* RxBD bits definitions */
+#define BD_ENET_RX_ERR	(BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
+			 BD_ENET_RX_OV | BD_ENET_RX_TR)
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#include <asm/immap.h>
+#include <asm/fsl_mcdmafec.h>
+
+#include "MCD_dma.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct fec_info_dma fec_info[] = {
+#ifdef CFG_FEC0_IOBASE
+	{
+	 0,			/* index */
+	 CFG_FEC0_IOBASE,	/* io base */
+	 CFG_FEC0_PINMUX,	/* gpio pin muxing */
+	 CFG_FEC0_MIIBASE,	/* mii base */
+	 -1,			/* phy_addr */
+	 0,			/* duplex and speed */
+	 0,			/* phy name */
+	 0,			/* phyname init */
+	 0,			/* RX BD */
+	 0,			/* TX BD */
+	 0,			/* rx Index */
+	 0,			/* tx Index */
+	 0,			/* tx buffer */
+	 0,			/* initialized flag */
+	 (struct fec_info_dma *)-1,	/* next */
+	 FEC0_RX_TASK,		/* rxTask */
+	 FEC0_TX_TASK,		/* txTask */
+	 FEC0_RX_PRIORITY,	/* rxPri */
+	 FEC0_TX_PRIORITY,	/* txPri */
+	 FEC0_RX_INIT,		/* rxInit */
+	 FEC0_TX_INIT,		/* txInit */
+	 0,			/* usedTbdIndex */
+	 0,			/* cleanTbdNum */
+	 },
+#endif
+#ifdef CFG_FEC1_IOBASE
+	{
+	 1,			/* index */
+	 CFG_FEC1_IOBASE,	/* io base */
+	 CFG_FEC1_PINMUX,	/* gpio pin muxing */
+	 CFG_FEC1_MIIBASE,	/* mii base */
+	 -1,			/* phy_addr */
+	 0,			/* duplex and speed */
+	 0,			/* phy name */
+	 0,			/* phy name init */
+	 0,			/* RX BD */
+	 0,			/* TX BD */
+	 0,			/* rx Index */
+	 0,			/* tx Index */
+	 0,			/* tx buffer */
+	 0,			/* initialized flag */
+	 (struct fec_info_dma *)-1,	/* next */
+	 FEC1_RX_TASK,		/* rxTask */
+	 FEC1_TX_TASK,		/* txTask */
+	 FEC1_RX_PRIORITY,	/* rxPri */
+	 FEC1_TX_PRIORITY,	/* txPri */
+	 FEC1_RX_INIT,		/* rxInit */
+	 FEC1_TX_INIT,		/* txInit */
+	 0,			/* usedTbdIndex */
+	 0,			/* cleanTbdNum */
+	 }
+#endif
+};
+
+static int fec_send(struct eth_device *dev, volatile void *packet, int length);
+static int fec_recv(struct eth_device *dev);
+static int fec_init(struct eth_device *dev, bd_t * bd);
+static void fec_halt(struct eth_device *dev);
+
+#ifdef ET_DEBUG
+static void dbg_fec_regs(struct eth_device *dev)
+{
+	struct fec_info_dma *info = dev->priv;
+	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
+
+	printf("=====\n");
+	printf("ievent       %x - %x\n", (int)&fecp->eir, fecp->eir);
+	printf("imask        %x - %x\n", (int)&fecp->eimr, fecp->eimr);
+	printf("ecntrl       %x - %x\n", (int)&fecp->ecr, fecp->ecr);
+	printf("mii_mframe   %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
+	printf("mii_speed    %x - %x\n", (int)&fecp->mscr, fecp->mscr);
+	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
+	printf("r_cntrl      %x - %x\n", (int)&fecp->rcr, fecp->rcr);
+	printf("r hash       %x - %x\n", (int)&fecp->rhr, fecp->rhr);
+	printf("x_cntrl      %x - %x\n", (int)&fecp->tcr, fecp->tcr);
+	printf("padr_l       %x - %x\n", (int)&fecp->palr, fecp->palr);
+	printf("padr_u       %x - %x\n", (int)&fecp->paur, fecp->paur);
+	printf("op_pause     %x - %x\n", (int)&fecp->opd, fecp->opd);
+	printf("iadr_u       %x - %x\n", (int)&fecp->iaur, fecp->iaur);
+	printf("iadr_l       %x - %x\n", (int)&fecp->ialr, fecp->ialr);
+	printf("gadr_u       %x - %x\n", (int)&fecp->gaur, fecp->gaur);
+	printf("gadr_l       %x - %x\n", (int)&fecp->galr, fecp->galr);
+	printf("x_wmrk       %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
+	printf("r_fdata      %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
+	printf("r_fstat      %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
+	printf("r_fctrl      %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
+	printf("r_flrfp      %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
+	printf("r_flwfp      %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
+	printf("r_frfar      %x - %x\n", (int)&fecp->rfar, fecp->rfar);
+	printf("r_frfrp      %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
+	printf("r_frfwp      %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
+	printf("t_fdata      %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
+	printf("t_fstat      %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
+	printf("t_fctrl      %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
+	printf("t_flrfp      %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
+	printf("t_flwfp      %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
+	printf("t_ftfar      %x - %x\n", (int)&fecp->tfar, fecp->tfar);
+	printf("t_ftfrp      %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
+	printf("t_ftfwp      %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
+	printf("frst         %x - %x\n", (int)&fecp->frst, fecp->frst);
+	printf("ctcwr        %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
+}
+#endif
+
+static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, int dup_spd)
+{
+	if ((dup_spd >> 16) == FULL) {
+		/* Set maximum frame length */
+		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
+		    FEC_RCR_PROM | 0x100;
+		fecp->tcr = FEC_TCR_FDEN;
+	} else {
+		/* Half duplex mode */
+		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
+		    FEC_RCR_MII_MODE | FEC_RCR_DRT;
+		fecp->tcr &= ~FEC_TCR_FDEN;
+	}
+
+	if ((dup_spd & 0xFFFF) == _100BASET) {
+#ifdef MII_DEBUG
+		printf("100Mbps\n");
+#endif
+		bd->bi_ethspeed = 100;
+	} else {
+#ifdef MII_DEBUG
+		printf("10Mbps\n");
+#endif
+		bd->bi_ethspeed = 10;
+	}
+}
+
+static int fec_send(struct eth_device *dev, volatile void *packet, int length)
+{
+	struct fec_info_dma *info = dev->priv;
+	cbd_t *pTbd, *pUsedTbd;
+	u16 phyStatus;
+
+	miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
+
+	/* process all the consumed TBDs */
+	while (info->cleanTbdNum < CFG_TX_ETH_BUFFER) {
+		pUsedTbd = &info->txbd[info->usedTbdIdx];
+		if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
+#ifdef ET_DEBUG
+			printf("Cannot clean TBD %d, in use\n",
+			       info->cleanTbdNum);
+#endif
+			return 0;
+		}
+
+		/* clean this buffer descriptor */
+		if (info->usedTbdIdx == (CFG_TX_ETH_BUFFER - 1))
+			pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
+		else
+			pUsedTbd->cbd_sc = 0;
+
+		/* update some indeces for a correct handling of the TBD ring */
+		info->cleanTbdNum++;
+		info->usedTbdIdx = (info->usedTbdIdx + 1) % CFG_TX_ETH_BUFFER;
+	}
+
+	/* Check for valid length of data. */
+	if ((length > 1500) || (length <= 0)) {
+		return -1;
+	}
+
+	/* Check the number of vacant TxBDs. */
+	if (info->cleanTbdNum < 1) {
+		printf("No available TxBDs ...\n");
+		return -1;
+	}
+
+	/* Get the first TxBD to send the mac header */
+	pTbd = &info->txbd[info->txIdx];
+	pTbd->cbd_datlen = length;
+	pTbd->cbd_bufaddr = (u32) packet;
+	pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
+	info->txIdx = (info->txIdx + 1) % CFG_TX_ETH_BUFFER;
+
+	/* Enable DMA transmit task */
+	MCD_continDma(info->txTask);
+
+	info->cleanTbdNum -= 1;
+
+	/* wait until frame is sent . */
+	while (pTbd->cbd_sc & BD_ENET_TX_READY) {
+		udelay(10);
+	}
+
+	return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
+}
+
+static int fec_recv(struct eth_device *dev)
+{
+	struct fec_info_dma *info = dev->priv;
+	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
+
+	cbd_t *pRbd = &info->rxbd[info->rxIdx];
+	u32 ievent;
+	int frame_length, len = 0;
+
+	/* Check if any critical events have happened */
+	ievent = fecp->eir;
+	if (ievent != 0) {
+		fecp->eir = ievent;
+
+		if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
+			printf("fec_recv: error\n");
+			fec_halt(dev);
+			fec_init(dev, NULL);
+			return 0;
+		}
+
+		if (ievent & FEC_EIR_HBERR) {
+			/* Heartbeat error */
+			fecp->tcr |= FEC_TCR_GTS;
+		}
+
+		if (ievent & FEC_EIR_GRA) {
+			/* Graceful stop complete */
+			if (fecp->tcr & FEC_TCR_GTS) {
+				printf("fec_recv: tcr_gts\n");
+				fec_halt(dev);
+				fecp->tcr &= ~FEC_TCR_GTS;
+				fec_init(dev, NULL);
+			}
+		}
+	}
+
+	if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) {
+		if ((pRbd->cbd_sc & BD_ENET_RX_LAST)
+		    && !(pRbd->cbd_sc & BD_ENET_RX_ERR)
+		    && ((pRbd->cbd_datlen - 4) > 14)) {
+
+			/* Get buffer address and size */
+			frame_length = pRbd->cbd_datlen - 4;
+
+			/* Fill the buffer and pass it to upper layers */
+			NetReceive((volatile uchar *)pRbd->cbd_bufaddr,
+				   frame_length);
+			len = frame_length;
+		}
+
+		/* Reset buffer descriptor as empty */
+		if ((info->rxIdx) == (PKTBUFSRX - 1))
+			pRbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
+		else
+			pRbd->cbd_sc = BD_ENET_RX_EMPTY;
+
+		pRbd->cbd_datlen = PKTSIZE_ALIGN;
+
+		/* Now, we have an empty RxBD, restart the DMA receive task */
+		MCD_continDma(info->rxTask);
+
+		/* Increment BD count */
+		info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
+	}
+
+	return len;
+}
+
+static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
+{
+	u8 currByte;		/* byte for which to compute the CRC */
+	int byte;		/* loop - counter */
+	int bit;		/* loop - counter */
+	u32 crc = 0xffffffff;	/* initial value */
+
+	for (byte = 0; byte < 6; byte++) {
+		currByte = mac[byte];
+		for (bit = 0; bit < 8; bit++) {
+			if ((currByte & 0x01) ^ (crc & 0x01)) {
+				crc >>= 1;
+				crc = crc ^ 0xedb88320;
+			} else {
+				crc >>= 1;
+			}
+			currByte >>= 1;
+		}
+	}
+
+	crc = crc >> 26;
+
+	/* Set individual hash table register */
+	if (crc >= 32) {
+		fecp->ialr = (1 << (crc - 32));
+		fecp->iaur = 0;
+	} else {
+		fecp->ialr = 0;
+		fecp->iaur = (1 << crc);
+	}
+
+	/* Set physical address */
+	fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
+	fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
+
+	/* Clear multicast address hash table */
+	fecp->gaur = 0;
+	fecp->galr = 0;
+}
+
+static int fec_init(struct eth_device *dev, bd_t * bd)
+{
+	struct fec_info_dma *info = dev->priv;
+	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
+	int i;
+
+#ifdef ET_DEBUG
+	printf("fec_init: iobase 0x%08x ...\n", info->iobase);
+#endif
+
+	fecpin_setclear(dev, 1);
+
+	fec_halt(dev);
+
+#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
+	defined (CFG_DISCOVER_PHY)
+
+	mii_init();
+
+	set_fec_duplex_speed(fecp, bd, info->dup_spd);
+#else
+#ifndef CFG_DISCOVER_PHY
+	set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
+#endif				/* ifndef CFG_DISCOVER_PHY */
+#endif				/* CONFIG_CMD_MII || CONFIG_MII */
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	/* Set station address   */
+	if ((u32) fecp == CFG_FEC0_IOBASE) {
+		fec_set_hwaddr(fecp, bd->bi_enetaddr);
+	} else {
+		fec_set_hwaddr(fecp, bd->bi_enet1addr);
+	}
+
+	/* Set Opcode/Pause Duration Register */
+	fecp->opd = 0x00010020;
+
+	/* Setup Buffers and Buffer Desriptors */
+	info->rxIdx = 0;
+	info->txIdx = 0;
+
+	/* Setup Receiver Buffer Descriptors (13.14.24.18)
+	 * Settings:     Empty, Wrap */
+	for (i = 0; i < PKTBUFSRX; i++) {
+		info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+		info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
+		info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
+	}
+	info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
+
+	/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
+	 * Settings:    Last, Tx CRC */
+	for (i = 0; i < CFG_TX_ETH_BUFFER; i++) {
+		info->txbd[i].cbd_sc = 0;
+		info->txbd[i].cbd_datlen = 0;
+		info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
+	}
+	info->txbd[CFG_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
+
+	info->usedTbdIdx = 0;
+	info->cleanTbdNum = CFG_TX_ETH_BUFFER;
+
+	/* Set Rx FIFO alarm and granularity value */
+	fecp->rfcr = 0x0c000000;
+	fecp->rfar = 0x0000030c;
+
+	/* Set Tx FIFO granularity value */
+	fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
+	fecp->tfar = 0x00000080;
+
+	fecp->tfwr = 0x2;
+	fecp->ctcwr = 0x03000000;
+
+	/* Enable DMA receive task */
+	MCD_startDma(info->rxTask,	/* Dma channel */
+		     (s8 *) info->rxbd,	/*Source Address */
+		     0,		/* Source increment */
+		     (s8 *) (&fecp->rfdr),	/* dest */
+		     4,		/* dest increment */
+		     0,		/* DMA size */
+		     4,		/* xfer size */
+		     info->rxInit,	/* initiator */
+		     info->rxPri,	/* priority */
+		     (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),	/* Flags */
+		     (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)	/* Function description */
+	    );
+
+	/* Enable DMA tx task with no ready buffer descriptors */
+	MCD_startDma(info->txTask,	/* Dma channel */
+		     (s8 *) info->txbd,	/*Source Address */
+		     0,		/* Source increment */
+		     (s8 *) (&fecp->tfdr),	/* dest */
+		     4,		/* dest incr */
+		     0,		/* DMA size */
+		     4,		/* xfer size */
+		     info->txInit,	/* initiator */
+		     info->txPri,	/* priority */
+		     (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),	/* Flags */
+		     (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)	/* Function description */
+	    );
+
+	/* Now enable the transmit and receive processing */
+	fecp->ecr |= FEC_ECR_ETHER_EN;
+
+	return 1;
+}
+
+static void fec_halt(struct eth_device *dev)
+{
+	struct fec_info_dma *info = dev->priv;
+	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
+	int counter = 0xffff;
+
+	/* issue graceful stop command to the FEC transmitter if necessary */
+	fecp->tcr |= FEC_TCR_GTS;
+
+	/* wait for graceful stop to register */
+	while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
+
+	/* Disable DMA tasks */
+	MCD_killDma(info->txTask);
+	MCD_killDma(info->rxTask);;
+
+	/* Disable the Ethernet Controller */
+	fecp->ecr &= ~FEC_ECR_ETHER_EN;
+
+	/* Clear FIFO status registers */
+	fecp->rfsr &= FIFO_ERRSTAT;
+	fecp->tfsr &= FIFO_ERRSTAT;
+
+	fecp->frst = 0x01000000;
+
+	/* Issue a reset command to the FEC chip */
+	fecp->ecr |= FEC_ECR_RESET;
+
+	/* wait at least 20 clock cycles */
+	udelay(10000);
+
+#ifdef ET_DEBUG
+	printf("Ethernet task stopped\n");
+#endif
+}
+
+int mcdmafec_initialize(bd_t * bis)
+{
+	struct eth_device *dev;
+	int i;
+
+	for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
+
+		dev =
+		    (struct eth_device *)memalign(CFG_CACHELINE_SIZE,
+						  sizeof *dev);
+		if (dev == NULL)
+			hang();
+
+		memset(dev, 0, sizeof(*dev));
+
+		sprintf(dev->name, "FEC%d", fec_info[i].index);
+
+		dev->priv = &fec_info[i];
+		dev->init = fec_init;
+		dev->halt = fec_halt;
+		dev->send = fec_send;
+		dev->recv = fec_recv;
+
+		/* setup Receive and Transmit buffer descriptor */
+		fec_info[i].rxbd =
+		    (cbd_t *) memalign(CFG_CACHELINE_SIZE,
+				       (PKTBUFSRX * sizeof(cbd_t)));
+		fec_info[i].txbd =
+		    (cbd_t *) memalign(CFG_CACHELINE_SIZE,
+				       (CFG_TX_ETH_BUFFER * sizeof(cbd_t)));
+		fec_info[i].txbuf =
+		    (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
+
+#ifdef ET_DEBUG
+		printf("rxbd %x txbd %x\n",
+		       (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
+#endif
+
+		fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
+
+		eth_register(dev);
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+		miiphy_register(dev->name,
+				mcffec_miiphy_read, mcffec_miiphy_write);
+#endif
+
+		if (i > 0)
+			fec_info[i - 1].next = &fec_info[i];
+	}
+	fec_info[i - 1].next = &fec_info[0];
+
+	/* default speed */
+	bis->bi_ethspeed = 10;
+
+	return 1;
+}
+
+#endif				/* CONFIG_CMD_NET && CONFIG_NET_MULTI */
+#endif				/* CONFIG_FSLDMAFEC */
diff --git a/include/MCD_dma.h b/include/MCD_dma.h
new file mode 100644
index 0000000..2d6bc00
--- /dev/null
+++ b/include/MCD_dma.h
@@ -0,0 +1,386 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MCD_API_H
+#define _MCD_API_H
+
+/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
+#undef MCD_INCLUDE_EU
+
+/* Number of DMA channels */
+#define NCHANNELS	16
+
+/* Total number of variants */
+#ifdef MCD_INCLUDE_EU
+#define NUMOFVARIANTS	6
+#else
+#define NUMOFVARIANTS	4
+#endif
+
+/* Define sizes of the various tables */
+#define TASK_TABLE_SIZE		(NCHANNELS*32)
+#define VAR_TAB_SIZE		(128)
+#define CONTEXT_SAVE_SIZE	(128)
+#define FUNCDESC_TAB_SIZE	(256)
+
+#ifdef MCD_INCLUDE_EU
+#define FUNCDESC_TAB_NUM	16
+#else
+#define FUNCDESC_TAB_NUM	1
+#endif
+
+#ifndef DEFINESONLY
+
+/* Portability typedefs */
+#if 1
+#include "common.h"
+#else
+#ifndef s32
+typedef int s32;
+#endif
+#ifndef u32
+typedef unsigned int u32;
+#endif
+#ifndef s16
+typedef short s16;
+#endif
+#ifndef u16
+typedef unsigned short u16;
+#endif
+#ifndef s8
+typedef char s8;
+#endif
+#ifndef u8
+typedef unsigned char u8;
+#endif
+#endif
+
+/*
+ * These structures represent the internal registers of the
+ * multi-channel DMA
+ */
+struct dmaRegs_s {
+	u32 taskbar;		/* task table base address */
+	u32 currPtr;
+	u32 endPtr;
+	u32 varTablePtr;
+	u16 dma_rsvd0;
+	u16 ptdControl;		/* ptd control */
+	u32 intPending;		/* interrupt pending */
+	u32 intMask;		/* interrupt mask */
+	u16 taskControl[16];	/* task control */
+	u8 priority[32];	/* priority */
+	u32 initiatorMux;	/* initiator mux control */
+	u32 taskSize0;		/* task size control 0. */
+	u32 taskSize1;		/* task size control 1. */
+	u32 dma_rsvd1;		/* reserved */
+	u32 dma_rsvd2;		/* reserved */
+	u32 debugComp1;		/* debug comparator 1 */
+	u32 debugComp2;		/* debug comparator 2 */
+	u32 debugControl;	/* debug control */
+	u32 debugStatus;	/* debug status */
+	u32 ptdDebug;		/* priority task decode debug */
+	u32 dma_rsvd3[31];	/* reserved */
+};
+typedef volatile struct dmaRegs_s dmaRegs;
+
+#endif
+
+/* PTD contrl reg bits */
+#define PTD_CTL_TSK_PRI		0x8000
+#define PTD_CTL_COMM_PREFETCH	0x0001
+
+/* Task Control reg bits and field masks */
+#define TASK_CTL_EN		0x8000
+#define TASK_CTL_VALID		0x4000
+#define TASK_CTL_ALWAYS		0x2000
+#define TASK_CTL_INIT_MASK	0x1f00
+#define TASK_CTL_ASTRT		0x0080
+#define TASK_CTL_HIPRITSKEN	0x0040
+#define TASK_CTL_HLDINITNUM	0x0020
+#define TASK_CTL_ASTSKNUM_MASK	0x000f
+
+/* Priority reg bits and field masks */
+#define PRIORITY_HLD		0x80
+#define PRIORITY_PRI_MASK	0x07
+
+/* Debug Control reg bits and field masks */
+#define DBG_CTL_BLOCK_TASKS_MASK	0xffff0000
+#define DBG_CTL_AUTO_ARM		0x00008000
+#define DBG_CTL_BREAK			0x00004000
+#define DBG_CTL_COMP1_TYP_MASK		0x00003800
+#define DBG_CTL_COMP2_TYP_MASK		0x00000070
+#define DBG_CTL_EXT_BREAK		0x00000004
+#define DBG_CTL_INT_BREAK		0x00000002
+
+/*
+ * PTD Debug reg selector addresses
+ * This reg must be written with a value to show the contents of
+ * one of the desired internal register.
+ */
+#define PTD_DBG_REQ		0x00	/* shows the state of 31 initiators */
+#define PTD_DBG_TSK_VLD_INIT	0x01	/* shows which 16 tasks are valid and
+					   have initiators asserted */
+
+/* General return values */
+#define MCD_OK			0
+#define MCD_ERROR		-1
+#define MCD_TABLE_UNALIGNED	-2
+#define MCD_CHANNEL_INVALID	-3
+
+/* MCD_initDma input flags */
+#define MCD_RELOC_TASKS		0x00000001
+#define MCD_NO_RELOC_TASKS	0x00000000
+#define MCD_COMM_PREFETCH_EN	0x00000002	/* MCF547x/548x ONLY */
+
+/*
+ * MCD_dmaStatus Status Values for each channel:
+ * MCD_NO_DMA	- No DMA has been requested since reset
+ * MCD_IDLE	- DMA active, but the initiator is currently inactive
+ * MCD_RUNNING	- DMA active, and the initiator is currently active
+ * MCD_PAUSED	- DMA active but it is currently paused
+ * MCD_HALTED	- the most recent DMA has been killed with MCD_killTask()
+ * MCD_DONE	- the most recent DMA has completed
+ */
+#define MCD_NO_DMA		1
+#define MCD_IDLE		2
+#define MCD_RUNNING		3
+#define MCD_PAUSED		4
+#define MCD_HALTED		5
+#define MCD_DONE		6
+
+/* MCD_startDma parameter defines */
+
+/* Constants for the funcDesc parameter */
+/*
+ * MCD_NO_BYTE_SWAP	- to disable byte swapping
+ * MCD_BYTE_REVERSE	- to reverse the bytes of each u32 of the DMAed data
+ * MCD_U16_REVERSE	- to reverse the 16-bit halves of each 32-bit data
+ *			  value being DMAed
+ * MCD_U16_BYTE_REVERSE	- to reverse the byte halves of each 16-bit half of
+ *			  each 32-bit data value DMAed
+ * MCD_NO_BIT_REV	- do not reverse the bits of each byte DMAed
+ * MCD_BIT_REV		- reverse the bits of each byte DMAed
+ * MCD_CRC16		- to perform CRC-16 on DMAed data
+ * MCD_CRCCCITT		- to perform CRC-CCITT on DMAed data
+ * MCD_CRC32		- to perform CRC-32 on DMAed data
+ * MCD_CSUMINET		- to perform internet checksums on DMAed data
+ * MCD_NO_CSUM		- to perform no checksumming
+ */
+#define MCD_NO_BYTE_SWAP	0x00045670
+#define MCD_BYTE_REVERSE	0x00076540
+#define MCD_U16_REVERSE		0x00067450
+#define MCD_U16_BYTE_REVERSE	0x00054760
+#define MCD_NO_BIT_REV		0x00000000
+#define MCD_BIT_REV		0x00088880
+/* CRCing: */
+#define MCD_CRC16		0xc0100000
+#define MCD_CRCCCITT		0xc0200000
+#define MCD_CRC32		0xc0300000
+#define MCD_CSUMINET		0xc0400000
+#define MCD_NO_CSUM		0xa0000000
+
+#define MCD_FUNC_NOEU1		(MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
+				 MCD_NO_CSUM)
+#define MCD_FUNC_NOEU2		(MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
+
+/* Constants for the flags parameter */
+#define MCD_TT_FLAGS_RL		0x00000001	/* Read line */
+#define MCD_TT_FLAGS_CW		0x00000002	/* Combine Writes */
+#define MCD_TT_FLAGS_SP		0x00000004	/* MCF547x/548x ONLY  */
+#define MCD_TT_FLAGS_MASK	0x000000ff
+#define MCD_TT_FLAGS_DEF	(MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
+
+#define MCD_SINGLE_DMA		0x00000100	/* Unchained DMA */
+#define MCD_CHAIN_DMA		/* TBD */
+#define MCD_EU_DMA		/* TBD */
+#define MCD_FECTX_DMA		0x00001000	/* FEC TX ring DMA */
+#define MCD_FECRX_DMA		0x00002000	/* FEC RX ring DMA */
+
+/* these flags are valid for MCD_startDma and the chained buffer descriptors */
+/*
+ * MCD_BUF_READY	- indicates that this buf is now under the DMA's ctrl
+ * MCD_WRAP		- to tell the FEC Dmas to wrap to the first BD
+ * MCD_INTERRUPT	- to generate an interrupt after completion of the DMA
+ * MCD_END_FRAME	- tell the DMA to end the frame when transferring
+ *			  last byte of data in buffer
+ * MCD_CRC_RESTART	- to empty out the accumulated checksum prior to
+ *			  performing the DMA
+ */
+#define MCD_BUF_READY		0x80000000
+#define MCD_WRAP		0x20000000
+#define MCD_INTERRUPT		0x10000000
+#define MCD_END_FRAME		0x08000000
+#define MCD_CRC_RESTART		0x40000000
+
+/* Defines for the FEC buffer descriptor control/status word*/
+#define MCD_FEC_BUF_READY	0x8000
+#define MCD_FEC_WRAP		0x2000
+#define MCD_FEC_INTERRUPT	0x1000
+#define MCD_FEC_END_FRAME	0x0800
+
+/* Defines for general intuitiveness */
+
+#define MCD_TRUE		1
+#define MCD_FALSE		0
+
+/* Three different cases for destination and source. */
+#define MINUS1			-1
+#define ZERO			0
+#define PLUS1			1
+
+#ifndef DEFINESONLY
+
+/* Task Table Entry struct*/
+typedef struct {
+	u32 TDTstart;		/* task descriptor table start */
+	u32 TDTend;		/* task descriptor table end */
+	u32 varTab;		/* variable table start */
+	u32 FDTandFlags;	/* function descriptor table start & flags */
+	volatile u32 descAddrAndStatus;
+	volatile u32 modifiedVarTab;
+	u32 contextSaveSpace;	/* context save space start */
+	u32 literalBases;
+} TaskTableEntry;
+
+/* Chained buffer descriptor:
+ * flags	- flags describing the DMA
+ * csumResult	- checksum performed since last checksum reset
+ * srcAddr	- the address to move data from
+ * destAddr	- the address to move data to
+ * lastDestAddr	- the last address written to
+ * dmaSize	- the no of bytes to xfer independent of the xfer sz
+ * next		- next buffer descriptor in chain
+ * info		- private info about this descriptor;  DMA does not affect it
+ */
+typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
+struct MCD_bufDesc_struct {
+	u32 flags;
+	u32 csumResult;
+	s8 *srcAddr;
+	s8 *destAddr;
+	s8 *lastDestAddr;
+	u32 dmaSize;
+	MCD_bufDesc *next;
+	u32 info;
+};
+
+/* Progress Query struct:
+ * lastSrcAddr	- the most-recent or last, post-increment source address
+ * lastDestAddr	- the most-recent or last, post-increment destination address
+ * dmaSize	- the amount of data transferred for the current buffer
+ * currBufDesc	- pointer to the current buffer descriptor being DMAed
+ */
+
+typedef volatile struct MCD_XferProg_struct {
+	s8 *lastSrcAddr;
+	s8 *lastDestAddr;
+	u32 dmaSize;
+	MCD_bufDesc *currBufDesc;
+} MCD_XferProg;
+
+/* FEC buffer descriptor */
+typedef volatile struct MCD_bufDescFec_struct {
+	u16 statCtrl;
+	u16 length;
+	u32 dataPointer;
+} MCD_bufDescFec;
+
+/*************************************************************************/
+/* API function Prototypes  - see MCD_dmaApi.c for further notes */
+
+/* MCD_startDma starts a particular kind of DMA:
+ * srcAddr	- the channel on which to run the DMA
+ * srcIncr	- the address to move data from, or buffer-descriptor address
+ * destAddr	- the amount to increment the source address per transfer
+ * destIncr	- the address to move data to
+ * dmaSize	- the amount to increment the destination address per transfer
+ * xferSize	- the number bytes in of each data movement (1, 2, or 4)
+ * initiator	- what device initiates the DMA
+ * priority	- priority of the DMA
+ * flags	- flags describing the DMA
+ * funcDesc	- description of byte swapping, bit swapping, and CRC actions
+ */
+int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
+		 s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
+		 int priority, u32 flags, u32 funcDesc);
+
+/*
+ * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
+ * registers, relocating and creating the appropriate task structures, and
+ * setting up some global settings
+ */
+int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
+
+/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
+int MCD_dmaStatus(int channel);
+
+/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
+int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
+
+/*
+ * MCD_killDma() halts the DMA on the requested channel, without any
+ * intention of resuming the DMA.
+ */
+int MCD_killDma(int channel);
+
+/*
+ * MCD_continDma() continues a DMA which as stopped due to encountering an
+ * unready buffer descriptor.
+ */
+int MCD_continDma(int channel);
+
+/*
+ * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
+ * running on that channel).
+ */
+int MCD_pauseDma(int channel);
+
+/*
+ * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
+ * running on that channel).
+ */
+int MCD_resumeDma(int channel);
+
+/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
+int MCD_csumQuery(int channel, u32 * csum);
+
+/*
+ * MCD_getCodeSize provides the packed size required by the microcoded task
+ * and structures.
+ */
+int MCD_getCodeSize(void);
+
+/*
+ * MCD_getVersion provides a pointer to a version string and returns a
+ * version number.
+ */
+int MCD_getVersion(char **longVersion);
+
+/* macro for setting a location in the variable table */
+#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
+/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
+   so I'm avoiding surrounding it with "do {} while(0)" */
+
+#endif				/* DEFINESONLY */
+
+#endif				/* _MCD_API_H */
diff --git a/include/MCD_progCheck.h b/include/MCD_progCheck.h
new file mode 100644
index 0000000..55f7574
--- /dev/null
+++ b/include/MCD_progCheck.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ /* This file is autogenerated. Do not change */
+#define CURRBD		4
+#define DCOUNT		6
+#define DESTPTR		5
+#define SRCPTR		7
diff --git a/include/MCD_tasksInit.h b/include/MCD_tasksInit.h
new file mode 100644
index 0000000..684d5aa
--- /dev/null
+++ b/include/MCD_tasksInit.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MCD_TSK_INIT_H
+#define MCD_TSK_INIT_H 1
+
+/*
+ * Do not edit!
+ */
+
+/* Task 0 */
+void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
+			   int xferSize, short xferSizeIncr, int *cSave,
+			   volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 1 */
+void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
+			    short destIncr, int dmaSize, short xferSizeIncr,
+			    int flags, int *currBD, int *cSave,
+			    volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 2 */
+void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
+			 int xferSize, short xferSizeIncr, int *cSave,
+			 volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 3 */
+void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
+			  short destIncr, int dmaSize, short xferSizeIncr,
+			  int flags, int *currBD, int *cSave,
+			  volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 4 */
+void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
+			 volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 5 */
+void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
+			  volatile TaskTableEntry * taskTable, int channel);
+
+#endif				/* MCD_TSK_INIT_H */
diff --git a/include/asm-m68k/coldfire/crossbar.h b/include/asm-m68k/coldfire/crossbar.h
new file mode 100644
index 0000000..a9c724c
--- /dev/null
+++ b/include/asm-m68k/coldfire/crossbar.h
@@ -0,0 +1,79 @@
+/*
+ * Cross Bar Switch Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CROSSBAR_H__
+#define __CROSSBAR_H__
+
+/*********************************************************************
+* Cross-bar switch (XBS)
+*********************************************************************/
+typedef struct xbs {
+	u32 prs1;		/* 0x100 Priority Register Slave 1 */
+	u32 res1[3];		/* 0x104 - 0F */
+	u32 crs1;		/* 0x110 Control Register Slave 1 */
+	u32 res2[187];		/* 0x114 - 0x3FF */
+
+	u32 prs4;		/* 0x400 Priority Register Slave 4 */
+	u32 res3[3];		/* 0x404 - 0F */
+	u32 crs4;		/* 0x410 Control Register Slave 4 */
+	u32 res4[123];		/* 0x414 - 0x5FF */
+
+	u32 prs6;		/* 0x600 Priority Register Slave 6 */
+	u32 res5[3];		/* 0x604 - 0F */
+	u32 crs6;		/* 0x610 Control Register Slave 6 */
+	u32 res6[59];		/* 0x614 - 0x6FF */
+
+	u32 prs7;		/* 0x700 Priority Register Slave 7 */
+	u32 res7[3];		/* 0x704 - 0F */
+	u32 crs7;		/* 0x710 Control Register Slave 7 */
+} xbs_t;
+
+/* Bit definitions and macros for PRS group */
+#define XBS_PRS_M0(x)			(((x)&0x00000007))	/* Core */
+#define XBS_PRS_M1(x)			(((x)&0x00000007)<<4)	/* eDMA */
+#define XBS_PRS_M2(x)			(((x)&0x00000007)<<8)	/* FEC0 */
+#define XBS_PRS_M3(x)			(((x)&0x00000007)<<12)	/* FEC1 */
+#define XBS_PRS_M5(x)			(((x)&0x00000007)<<20)	/* PCI controller */
+#define XBS_PRS_M6(x)			(((x)&0x00000007)<<24)	/* USB OTG */
+#define XBS_PRS_M7(x)			(((x)&0x00000007)<<28)	/* Serial Boot */
+
+/* Bit definitions and macros for CRS group */
+#define XBS_CRS_PARK(x)			(((x)&0x00000007))	/* Master parking ctrl */
+#define XBS_CRS_PCTL(x)			(((x)&0x00000003)<<4)	/* Parking mode ctrl */
+#define XBS_CRS_ARB			(0x00000100)	/* Arbitration Mode */
+#define XBS_CRS_RO			(0x80000000)	/* Read Only */
+
+#define XBS_CRS_PCTL_PARK_FIELD		(0)
+#define XBS_CRS_PCTL_PARK_ON_LAST	(1)
+#define XBS_CRS_PCTL_PARK_NONE		(2)
+#define XBS_CRS_PCTL_PARK_CORE		(0)
+#define XBS_CRS_PCTL_PARK_EDMA		(1)
+#define XBS_CRS_PCTL_PARK_FEC0		(2)
+#define XBS_CRS_PCTL_PARK_FEC1		(3)
+#define XBS_CRS_PCTL_PARK_PCI		(5)
+#define XBS_CRS_PCTL_PARK_USB		(6)
+#define XBS_CRS_PCTL_PARK_SBF		(7)
+
+#endif				/* __CROSSBAR_H__ */
diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
new file mode 100644
index 0000000..3c579d3
--- /dev/null
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -0,0 +1,156 @@
+/*
+ * MCF5227x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DSPI_H__
+#define __DSPI_H__
+
+/*********************************************************************
+* DMA Serial Peripheral Interface (DSPI)
+*********************************************************************/
+
+typedef struct dspi {
+	u32 dmcr;
+	u8 resv0[0x4];
+	u32 dtcr;
+	u32 dctar0;
+	u32 dctar1;
+	u32 dctar2;
+	u32 dctar3;
+	u32 dctar4;
+	u32 dctar5;
+	u32 dctar6;
+	u32 dctar7;
+	u32 dsr;
+	u32 dirsr;
+	u32 dtfr;
+	u32 drfr;
+	u32 dtfdr0;
+	u32 dtfdr1;
+	u32 dtfdr2;
+	u32 dtfdr3;
+	u8 resv1[0x30];
+	u32 drfdr0;
+	u32 drfdr1;
+	u32 drfdr2;
+	u32 drfdr3;
+} dspi_t;
+
+/* Bit definitions and macros for DMCR */
+#define DSPI_DMCR_HALT			(0x00000001)
+#define DSPI_DMCR_SMPL_PT(x)		(((x)&0x00000003)<<8)
+#define DSPI_DMCR_CRXF			(0x00000400)
+#define DSPI_DMCR_CTXF			(0x00000800)
+#define DSPI_DMCR_DRXF			(0x00001000)
+#define DSPI_DMCR_DTXF			(0x00002000)
+#define DSPI_DMCR_CSIS0			(0x00010000)
+#define DSPI_DMCR_CSIS2			(0x00040000)
+#define DSPI_DMCR_CSIS3			(0x00080000)
+#define DSPI_DMCR_CSIS5			(0x00200000)
+#define DSPI_DMCR_ROOE			(0x01000000)
+#define DSPI_DMCR_PCSSE			(0x02000000)
+#define DSPI_DMCR_MTFE			(0x04000000)
+#define DSPI_DMCR_FRZ			(0x08000000)
+#define DSPI_DMCR_DCONF(x)		(((x)&0x00000003)<<28)
+#define DSPI_DMCR_CSCK			(0x40000000)
+#define DSPI_DMCR_MSTR			(0x80000000)
+
+/* Bit definitions and macros for DTCR */
+#define DSPI_DTCR_SPI_TCNT(x)		(((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for DCTAR group */
+#define DSPI_DCTAR_BR(x)		(((x)&0x0000000F))
+#define DSPI_DCTAR_DT(x)		(((x)&0x0000000F)<<4)
+#define DSPI_DCTAR_ASC(x)		(((x)&0x0000000F)<<8)
+#define DSPI_DCTAR_CSSCK(x)		(((x)&0x0000000F)<<12)
+#define DSPI_DCTAR_PBR(x)		(((x)&0x00000003)<<16)
+#define DSPI_DCTAR_PDT(x)		(((x)&0x00000003)<<18)
+#define DSPI_DCTAR_PASC(x)		(((x)&0x00000003)<<20)
+#define DSPI_DCTAR_PCSSCK(x)		(((x)&0x00000003)<<22)
+#define DSPI_DCTAR_LSBFE		(0x01000000)
+#define DSPI_DCTAR_CPHA			(0x02000000)
+#define DSPI_DCTAR_CPOL			(0x04000000)
+#define DSPI_DCTAR_TRSZ(x)		(((x)&0x0000000F)<<27)
+#define DSPI_DCTAR_PCSSCK_1CLK		(0x00000000)
+#define DSPI_DCTAR_PCSSCK_3CLK		(0x00400000)
+#define DSPI_DCTAR_PCSSCK_5CLK		(0x00800000)
+#define DSPI_DCTAR_PCSSCK_7CLK		(0x00A00000)
+#define DSPI_DCTAR_PASC_1CLK		(0x00000000)
+#define DSPI_DCTAR_PASC_3CLK		(0x00100000)
+#define DSPI_DCTAR_PASC_5CLK		(0x00200000)
+#define DSPI_DCTAR_PASC_7CLK		(0x00300000)
+#define DSPI_DCTAR_PDT_1CLK		(0x00000000)
+#define DSPI_DCTAR_PDT_3CLK		(0x00040000)
+#define DSPI_DCTAR_PDT_5CLK		(0x00080000)
+#define DSPI_DCTAR_PDT_7CLK		(0x000A0000)
+#define DSPI_DCTAR_PBR_1CLK		(0x00000000)
+#define DSPI_DCTAR_PBR_3CLK		(0x00010000)
+#define DSPI_DCTAR_PBR_5CLK		(0x00020000)
+#define DSPI_DCTAR_PBR_7CLK		(0x00030000)
+
+/* Bit definitions and macros for DSR */
+#define DSPI_DSR_RXPTR(x)		(((x)&0x0000000F))
+#define DSPI_DSR_RXCTR(x)		(((x)&0x0000000F)<<4)
+#define DSPI_DSR_TXPTR(x)		(((x)&0x0000000F)<<8)
+#define DSPI_DSR_TXCTR(x)		(((x)&0x0000000F)<<12)
+#define DSPI_DSR_RFDF			(0x00020000)
+#define DSPI_DSR_RFOF			(0x00080000)
+#define DSPI_DSR_TFFF			(0x02000000)
+#define DSPI_DSR_TFUF			(0x08000000)
+#define DSPI_DSR_EOQF			(0x10000000)
+#define DSPI_DSR_TXRXS			(0x40000000)
+#define DSPI_DSR_TCF			(0x80000000)
+
+/* Bit definitions and macros for DIRSR */
+#define DSPI_DIRSR_RFDFS		(0x00010000)
+#define DSPI_DIRSR_RFDFE		(0x00020000)
+#define DSPI_DIRSR_RFOFE		(0x00080000)
+#define DSPI_DIRSR_TFFFS		(0x01000000)
+#define DSPI_DIRSR_TFFFE		(0x02000000)
+#define DSPI_DIRSR_TFUFE		(0x08000000)
+#define DSPI_DIRSR_EOQFE		(0x10000000)
+#define DSPI_DIRSR_TCFE			(0x80000000)
+
+/* Bit definitions and macros for DTFR */
+#define DSPI_DTFR_TXDATA(x)		(((x)&0x0000FFFF))
+#define DSPI_DTFR_CS0			(0x00010000)
+#define DSPI_DTFR_CS2			(0x00040000)
+#define DSPI_DTFR_CS3			(0x00080000)
+#define DSPI_DTFR_CS5			(0x00200000)
+#define DSPI_DTFR_CTCNT			(0x04000000)
+#define DSPI_DTFR_EOQ			(0x08000000)
+#define DSPI_DTFR_CTAS(x)		(((x)&0x00000007)<<28)
+#define DSPI_DTFR_CONT			(0x80000000)
+
+/* Bit definitions and macros for DRFR */
+#define DSPI_DRFR_RXDATA(x)		(((x)&0x0000FFFF))
+
+/* Bit definitions and macros for DTFDR group */
+#define DSPI_DTFDR_TXDATA(x)		(((x)&0x0000FFFF))
+#define DSPI_DTFDR_TXCMD(x)		(((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for DRFDR group */
+#define DSPI_DRFDR_RXDATA(x)		(((x)&0x0000FFFF))
+
+#endif				/* __DSPI_H__ */
diff --git a/include/asm-m68k/coldfire/edma.h b/include/asm-m68k/coldfire/edma.h
new file mode 100644
index 0000000..c88aea6
--- /dev/null
+++ b/include/asm-m68k/coldfire/edma.h
@@ -0,0 +1,177 @@
+/*
+ * EDMA Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EDMA_H__
+#define __EDMA_H__
+
+/*********************************************************************
+* Enhanced DMA (EDMA)
+*********************************************************************/
+
+/* eDMA module registers */
+typedef struct edma_ctrl {
+	u32 cr;			/* 0x00 Control Register */
+	u32 es;			/* 0x04 Error Status Register */
+	u16 res1[3];		/* 0x08 - 0x0D */
+	u16 erq;		/* 0x0E Enable Request Register */
+	u16 res2[3];		/* 0x10 - 0x15 */
+	u16 eei;		/* 0x16 Enable Error Interrupt Request */
+	u8 serq;		/* 0x18 Set Enable Request */
+	u8 cerq;		/* 0x19 Clear Enable Request */
+	u8 seei;		/* 0x1A Set En Error Interrupt Request */
+	u8 ceei;		/* 0x1B Clear En Error Interrupt Request */
+	u8 cint;		/* 0x1C Clear Interrupt Enable */
+	u8 cerr;		/* 0x1D Clear Error */
+	u8 ssrt;		/* 0x1E Set START Bit */
+	u8 cdne;		/* 0x1F Clear DONE Status Bit */
+	u16 res3[3];		/* 0x20 - 0x25 */
+	u16 intr;		/* 0x26 Interrupt Request */
+	u16 res4[3];		/* 0x28 - 0x2D */
+	u16 err;		/* 0x2E Error Register */
+	u32 res5[52];		/* 0x30 - 0xFF */
+	u8 dchpri0;		/* 0x100 Channel 0 Priority */
+	u8 dchpri1;		/* 0x101 Channel 1 Priority */
+	u8 dchpri2;		/* 0x102 Channel 2 Priority */
+	u8 dchpri3;		/* 0x103 Channel 3 Priority */
+	u8 dchpri4;		/* 0x104 Channel 4 Priority */
+	u8 dchpri5;		/* 0x105 Channel 5 Priority */
+	u8 dchpri6;		/* 0x106 Channel 6 Priority */
+	u8 dchpri7;		/* 0x107 Channel 7 Priority */
+	u8 dchpri8;		/* 0x108 Channel 8 Priority */
+	u8 dchpri9;		/* 0x109 Channel 9 Priority */
+	u8 dchpri10;		/* 0x110 Channel 10 Priority */
+	u8 dchpri11;		/* 0x111 Channel 11 Priority */
+	u8 dchpri12;		/* 0x112 Channel 12 Priority */
+	u8 dchpri13;		/* 0x113 Channel 13 Priority */
+	u8 dchpri14;		/* 0x114 Channel 14 Priority */
+	u8 dchpri15;		/* 0x115 Channel 15 Priority */
+} edma_t;
+
+/* TCD - eDMA*/
+typedef struct tcd_ctrl {
+	u32 saddr;		/* 0x00 Source Address */
+	u16 attr;		/* 0x04 Transfer Attributes */
+	u16 soff;		/* 0x06 Signed Source Address Offset */
+	u32 nbytes;		/* 0x08 Minor Byte Count */
+	u32 slast;		/* 0x0C Last Source Address Adjustment */
+	u32 daddr;		/* 0x10 Destination address */
+	u16 citer;		/* 0x14 Cur Minor Loop Link, Major Loop Cnt */
+	u16 doff;		/* 0x16 Signed Destination Address Offset */
+	u32 dlast_sga;		/* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
+	u16 biter;		/* 0x1C Minor Loop Lnk, Major Loop Cnt */
+	u16 csr;		/* 0x1E Control and Status */
+} tcd_st;
+
+typedef struct tcd_multiple {
+	tcd_st tcd[16];
+} tcd_t;
+
+/* Bit definitions and macros for EPPAR */
+#define EPORT_EPPAR_EPPA1(x)		(((x)&0x0003)<<2)
+#define EPORT_EPPAR_EPPA2(x)		(((x)&0x0003)<<4)
+#define EPORT_EPPAR_EPPA3(x)		(((x)&0x0003)<<6)
+#define EPORT_EPPAR_EPPA4(x)		(((x)&0x0003)<<8)
+#define EPORT_EPPAR_EPPA5(x)		(((x)&0x0003)<<10)
+#define EPORT_EPPAR_EPPA6(x)		(((x)&0x0003)<<12)
+#define EPORT_EPPAR_EPPA7(x)		(((x)&0x0003)<<14)
+#define EPORT_EPPAR_LEVEL		(0)
+#define EPORT_EPPAR_RISING		(1)
+#define EPORT_EPPAR_FALLING		(2)
+#define EPORT_EPPAR_BOTH		(3)
+#define EPORT_EPPAR_EPPA7_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA7_RISING	(0x4000)
+#define EPORT_EPPAR_EPPA7_FALLING	(0x8000)
+#define EPORT_EPPAR_EPPA7_BOTH		(0xC000)
+#define EPORT_EPPAR_EPPA6_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA6_RISING	(0x1000)
+#define EPORT_EPPAR_EPPA6_FALLING	(0x2000)
+#define EPORT_EPPAR_EPPA6_BOTH		(0x3000)
+#define EPORT_EPPAR_EPPA5_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA5_RISING	(0x0400)
+#define EPORT_EPPAR_EPPA5_FALLING	(0x0800)
+#define EPORT_EPPAR_EPPA5_BOTH		(0x0C00)
+#define EPORT_EPPAR_EPPA4_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA4_RISING	(0x0100)
+#define EPORT_EPPAR_EPPA4_FALLING	(0x0200)
+#define EPORT_EPPAR_EPPA4_BOTH		(0x0300)
+#define EPORT_EPPAR_EPPA3_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA3_RISING	(0x0040)
+#define EPORT_EPPAR_EPPA3_FALLING	(0x0080)
+#define EPORT_EPPAR_EPPA3_BOTH		(0x00C0)
+#define EPORT_EPPAR_EPPA2_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA2_RISING	(0x0010)
+#define EPORT_EPPAR_EPPA2_FALLING	(0x0020)
+#define EPORT_EPPAR_EPPA2_BOTH		(0x0030)
+#define EPORT_EPPAR_EPPA1_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA1_RISING	(0x0004)
+#define EPORT_EPPAR_EPPA1_FALLING	(0x0008)
+#define EPORT_EPPAR_EPPA1_BOTH		(0x000C)
+
+/* Bit definitions and macros for EPDDR */
+#define EPORT_EPDDR_EPDD1		(0x02)
+#define EPORT_EPDDR_EPDD2		(0x04)
+#define EPORT_EPDDR_EPDD3		(0x08)
+#define EPORT_EPDDR_EPDD4		(0x10)
+#define EPORT_EPDDR_EPDD5		(0x20)
+#define EPORT_EPDDR_EPDD6		(0x40)
+#define EPORT_EPDDR_EPDD7		(0x80)
+
+/* Bit definitions and macros for EPIER */
+#define EPORT_EPIER_EPIE1		(0x02)
+#define EPORT_EPIER_EPIE2		(0x04)
+#define EPORT_EPIER_EPIE3		(0x08)
+#define EPORT_EPIER_EPIE4		(0x10)
+#define EPORT_EPIER_EPIE5		(0x20)
+#define EPORT_EPIER_EPIE6		(0x40)
+#define EPORT_EPIER_EPIE7		(0x80)
+
+/* Bit definitions and macros for EPDR */
+#define EPORT_EPDR_EPD1			(0x02)
+#define EPORT_EPDR_EPD2			(0x04)
+#define EPORT_EPDR_EPD3			(0x08)
+#define EPORT_EPDR_EPD4			(0x10)
+#define EPORT_EPDR_EPD5			(0x20)
+#define EPORT_EPDR_EPD6			(0x40)
+#define EPORT_EPDR_EPD7			(0x80)
+
+/* Bit definitions and macros for EPPDR */
+#define EPORT_EPPDR_EPPD1		(0x02)
+#define EPORT_EPPDR_EPPD2		(0x04)
+#define EPORT_EPPDR_EPPD3		(0x08)
+#define EPORT_EPPDR_EPPD4		(0x10)
+#define EPORT_EPPDR_EPPD5		(0x20)
+#define EPORT_EPPDR_EPPD6		(0x40)
+#define EPORT_EPPDR_EPPD7		(0x80)
+
+/* Bit definitions and macros for EPFR */
+#define EPORT_EPFR_EPF1			(0x02)
+#define EPORT_EPFR_EPF2			(0x04)
+#define EPORT_EPFR_EPF3			(0x08)
+#define EPORT_EPFR_EPF4			(0x10)
+#define EPORT_EPFR_EPF5			(0x20)
+#define EPORT_EPFR_EPF6			(0x40)
+#define EPORT_EPFR_EPF7			(0x80)
+
+#endif					/* __EDMA_H__ */
diff --git a/include/asm-m68k/coldfire/flexbus.h b/include/asm-m68k/coldfire/flexbus.h
new file mode 100644
index 0000000..1d902c0
--- /dev/null
+++ b/include/asm-m68k/coldfire/flexbus.h
@@ -0,0 +1,98 @@
+/*
+ * FlexBus Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLEXBUS_H
+#define __FLEXBUS_H
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+
+typedef struct fbcs {
+	u32 csar0;		/* Chip-select Address Register */
+	u32 csmr0;		/* Chip-select Mask Register */
+	u32 cscr0;		/* Chip-select Control Register */
+	u32 csar1;		/* Chip-select Address Register */
+	u32 csmr1;		/* Chip-select Mask Register */
+	u32 cscr1;		/* Chip-select Control Register */
+	u32 csar2;		/* Chip-select Address Register */
+	u32 csmr2;		/* Chip-select Mask Register */
+	u32 cscr2;		/* Chip-select Control Register */
+	u32 csar3;		/* Chip-select Address Register */
+	u32 csmr3;		/* Chip-select Mask Register */
+	u32 cscr3;		/* Chip-select Control Register */
+	u32 csar4;		/* Chip-select Address Register */
+	u32 csmr4;		/* Chip-select Mask Register */
+	u32 cscr4;		/* Chip-select Control Register */
+	u32 csar5;		/* Chip-select Address Register */
+	u32 csmr5;		/* Chip-select Mask Register */
+	u32 cscr5;		/* Chip-select Control Register */
+} fbcs_t;
+
+/* Bit definitions and macros for CSAR group */
+#define FBCS_CSAR_BA(x)			((x)&0xFFFF0000)
+
+/* Bit definitions and macros for CSMR group */
+#define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
+#define FBCS_CSMR_WP			(0x00000100)	/* Write protect */
+#define FBCS_CSMR_BAM(x)		(((x)&0x0000FFFF)<<16)	/* Base address mask */
+#define FBCS_CSMR_BAM_4G		(0xFFFF0000)
+#define FBCS_CSMR_BAM_2G		(0x7FFF0000)
+#define FBCS_CSMR_BAM_1G		(0x3FFF0000)
+#define FBCS_CSMR_BAM_1024M		(0x3FFF0000)
+#define FBCS_CSMR_BAM_512M		(0x1FFF0000)
+#define FBCS_CSMR_BAM_256M		(0x0FFF0000)
+#define FBCS_CSMR_BAM_128M		(0x07FF0000)
+#define FBCS_CSMR_BAM_64M		(0x03FF0000)
+#define FBCS_CSMR_BAM_32M		(0x01FF0000)
+#define FBCS_CSMR_BAM_16M		(0x00FF0000)
+#define FBCS_CSMR_BAM_8M		(0x007F0000)
+#define FBCS_CSMR_BAM_4M		(0x003F0000)
+#define FBCS_CSMR_BAM_2M		(0x001F0000)
+#define FBCS_CSMR_BAM_1M		(0x000F0000)
+#define FBCS_CSMR_BAM_1024K		(0x000F0000)
+#define FBCS_CSMR_BAM_512K		(0x00070000)
+#define FBCS_CSMR_BAM_256K		(0x00030000)
+#define FBCS_CSMR_BAM_128K		(0x00010000)
+#define FBCS_CSMR_BAM_64K		(0x00000000)
+
+/* Bit definitions and macros for CSCR group */
+#define FBCS_CSCR_BSTW			(0x00000008)	/* Burst-write enable */
+#define FBCS_CSCR_BSTR			(0x00000010)	/* Burst-read enable */
+#define FBCS_CSCR_BEM			(0x00000020)	/* Byte-enable mode */
+#define FBCS_CSCR_PS(x)			(((x)&0x00000003)<<6)	/* Port size */
+#define FBCS_CSCR_AA			(0x00000100)	/* Auto-acknowledge */
+#define FBCS_CSCR_WS(x)			(((x)&0x0000003F)<<10)	/* Wait states */
+#define FBCS_CSCR_WRAH(x)		(((x)&0x00000003)<<16)	/* Write address hold or deselect */
+#define FBCS_CSCR_RDAH(x)		(((x)&0x00000003)<<18)	/* Read address hold or deselect */
+#define FBCS_CSCR_ASET(x)		(((x)&0x00000003)<<20)	/* Address setup */
+#define FBCS_CSCR_SWSEN			(0x00800000)	/* Secondary wait state enable */
+#define FBCS_CSCR_SWS(x)		(((x)&0x0000003F)<<26)	/* Secondary wait states */
+
+#define FBCS_CSCR_PS_8			(0x00000040)
+#define FBCS_CSCR_PS_16			(0x00000080)
+#define FBCS_CSCR_PS_32			(0x00000000)
+
+#endif				/* __FLEXBUS_H */
diff --git a/include/asm-m68k/coldfire/lcd.h b/include/asm-m68k/coldfire/lcd.h
new file mode 100644
index 0000000..66b95b3
--- /dev/null
+++ b/include/asm-m68k/coldfire/lcd.h
@@ -0,0 +1,213 @@
+/*
+ * LCD controller Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LCDC_H__
+#define __LCDC_H__
+
+/* LCD module registers */
+typedef struct lcd_ctrl {
+	u32 ssar;		/* 0x00 Screen Start Address Register */
+	u32 sr;			/* 0x04 LCD Size Register */
+	u32 vpw;		/* 0x08 Virtual Page Width Register */
+	u32 cpr;		/* 0x0C Cursor Position Register */
+	u32 cwhb;		/* 0x10 Cursor Width Height and Blink Register */
+	u32 ccmr;		/* 0x14 Color Cursor Mapping Register */
+	u32 pcr;		/* 0x18 Panel Configuration Register */
+	u32 hcr;		/* 0x1C Horizontal Configuration Register */
+	u32 vcr;		/* 0x20 Vertical Configuration Register */
+	u32 por;		/* 0x24 Panning Offset Register */
+	u32 scr;		/* 0x28 Sharp Configuration Register */
+	u32 pccr;		/* 0x2C PWM Contrast Control Register */
+	u32 dcr;		/* 0x30 DMA Control Register */
+	u32 rmcr;		/* 0x34 Refresh Mode Control Register */
+	u32 icr;		/* 0x38 Refresh Mode Control Register */
+	u32 ier;		/* 0x3C Interrupt Enable Register */
+	u32 isr;		/* 0x40 Interrupt Status Register */
+	u32 res[4];
+	u32 gwsar;		/* 0x50 Graphic Window Start Address Register */
+	u32 gwsr;		/* 0x54 Graphic Window Size Register */
+	u32 gwvpw;		/* 0x58 Graphic Window Virtual Page Width Register */
+	u32 gwpor;		/* 0x5C Graphic Window Panning Offset Register */
+	u32 gwpr;		/* 0x60 Graphic Window Position Register */
+	u32 gwcr;		/* 0x64 Graphic Window Control Register */
+	u32 gwdcr;		/* 0x68 Graphic Window DMA Control Register */
+} lcd_t;
+
+typedef struct lcdbg_ctrl {
+	u32 bglut[255];
+} lcdbg_t;
+
+typedef struct lcdgw_ctrl {
+	u32 gwlut[255];
+} lcdgw_t;
+
+/* Bit definitions and macros for LCDC_LSSAR */
+#define LCDC_SSAR_SSA(x)		(((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LSR */
+#define LCDC_SR_XMAX(x)			(((x)&0x0000003F)<<20)
+#define LCDC_SR_YMAX(x)			((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LVPWR */
+#define LCDC_VPWR_VPW(x)		(((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LCPR */
+#define LCDC_CPR_CC(x)			(((x)&0x00000003)<<30)
+#define LCDC_CPR_CC_AND			(0xC0000000)
+#define LCDC_CPR_CC_XOR			(0x80000000)
+#define LCDC_CPR_CC_OR			(0x40000000)
+#define LCDC_CPR_CC_TRANSPARENT		(0x00000000)
+#define LCDC_CPR_OP			(0x10000000)
+#define LCDC_CPR_CXP(x)			(((x)&0x000003FF)<<16)
+#define LCDC_CPR_CYP(x)			((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LCWHBR */
+#define LCDC_CWHBR_BK_EN		(0x80000000)
+#define LCDC_CWHBR_CW(x)		(((x)&0x0000001F)<<24)
+#define LCDC_CWHBR_CH(x)		(((x)&0x0000001F)<<16)
+#define LCDC_CWHBR_BD(x)		((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_LCCMR */
+#define LCDC_CCMR_CUR_COL_R(x)		(((x)&0x0000003F)<<12)
+#define LCDC_CCMR_CUR_COL_G(x)		(((x)&0x0000003F)<<6)
+#define LCDC_CCMR_CUR_COL_B(x)		((x)&0x0000003F)
+
+/* Bit definitions and macros for LCDC_LPCR */
+#define LCDC_PCR_PANEL_TYPE(x)		(((x)&0x00000003)<<30)
+#define LCDC_PCR_MODE_TFT		(0xC0000000)
+#define LCDC_PCR_MODE_CSTN		(0x40000000)
+#define LCDC_PCR_MODE_MONOCHROME	(0x00000000)
+#define LCDC_PCR_TFT			(0x80000000)
+#define LCDC_PCR_COLOR			(0x40000000)
+#define LCDC_PCR_PBSIZ(x)		(((x)&0x00000003)<<28)
+#define LCDC_PCR_PBSIZ_8		(0x30000000)
+#define LCDC_PCR_PBSIZ_4		(0x20000000)
+#define LCDC_PCR_PBSIZ_2		(0x10000000)
+#define LCDC_PCR_PBSIZ_1		(0x00000000)
+#define LCDC_PCR_BPIX(x)		(((x)&0x00000007)<<25)
+#define LCDC_PCR_BPIX_18bpp		(0x0C000000)
+#define LCDC_PCR_BPIX_16bpp		(0x0A000000)
+#define LCDC_PCR_BPIX_12bpp		(0x08000000)
+#define LCDC_PCR_BPIX_8bpp		(0x06000000)
+#define LCDC_PCR_BPIX_4bpp		(0x04000000)
+#define LCDC_PCR_BPIX_2bpp		(0x02000000)
+#define LCDC_PCR_BPIX_1bpp		(0x00000000)
+#define LCDC_PCR_PIXPOL			(0x01000000)
+#define LCDC_PCR_FLM			(0x00800000)
+#define LCDC_PCR_LPPOL			(0x00400000)
+#define LCDC_PCR_CLKPOL			(0x00200000)
+#define LCDC_PCR_OEPOL			(0x00100000)
+#define LCDC_PCR_SCLKIDLE		(0x00080000)
+#define LCDC_PCR_ENDSEL			(0x00040000)
+#define LCDC_PCR_SWAP_SEL		(0x00020000)
+#define LCDC_PCR_REV_VS			(0x00010000)
+#define LCDC_PCR_ACDSEL			(0x00008000)
+#define LCDC_PCR_ACD(x)			(((x)&0x0000007F)<<8)
+#define LCDC_PCR_SCLKSEL		(0x00000080)
+#define LCDC_PCR_SHARP			(0x00000040)
+#define LCDC_PCR_PCD(x)			((x)&0x0000003F)
+
+/* Bit definitions and macros for LCDC_LHCR */
+#define LCDC_HCR_H_WIDTH(x)		(((x)&0x0000003F)<<26)
+#define LCDC_HCR_H_WAIT_1(x)		(((x)&0x000000FF)<<8)
+#define LCDC_HCR_H_WAIT_2(x)		((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_LVCR */
+#define LCDC_VCR_V_WIDTH(x)		(((x)&0x0000003F)<<26)
+#define LCDC_VCR_V_WAIT_1(x)		(((x)&0x000000FF)<<8)
+#define LCDC_VCR_V_WAIT_2(x)		((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_SCR */
+#define LCDC_SCR_PS_R_DELAY(x)		(((x)&0x0000003F) << 26)
+#define LCDC_SCR_CLS_R_DELAY(x)		(((x)&0x000000FF) << 16)
+#define LCDC_SCR_RTG_DELAY(x)		(((x)&0x0000000F) << 8)
+#define LCDC_SCR_GRAY2(x)		(((x)&0x0000000F) << 4)
+#define LCDC_SCR_GRAY1(x)		((x)&&0x0000000F)
+
+/* Bit definitions and macros for LCDC_LPCCR */
+#define LCDC_PCCR_CLS_HI_WID(x)		(((x)&0x000001FF)<<16)
+#define LCDC_PCCR_LDMSK			(0x00008000)
+#define LCDC_PCCR_SCR(x)		(((x)&0x00000003)<<9)
+#define LCDC_PCCR_SCR_LCDCLK		(0x00000400)
+#define LCDC_PCCR_SCR_PIXCLK		(0x00000200)
+#define LCDC_PCCR_SCR_LNPULSE		(0x00000000)
+#define LCDC_PCCR_CC_EN			(0x00000100)
+#define LCDC_PCCR_PW(x)			((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_LDCR */
+#define LCDC_DCR_BURST			(0x80000000)
+#define LCDC_DCR_HM(x)			(((x)&0x0000001F)<<16)
+#define LCDC_DCR_TM(x)			((x)&0x0000001F)
+
+/* Bit definitions and macros for LCDC_LRMCR */
+#define LCDC_RMCR_SEL_REF		(0x00000001)
+
+/* Bit definitions and macros for LCDC_LICR */
+#define LCDC_ICR_GW_INT_CON		(0x00000010)
+#define LCDC_ICR_INTSYN			(0x00000004)
+#define LCDC_ICR_INTCON			(0x00000001)
+
+/* Bit definitions and macros for LCDC_LIER */
+#define LCDC_IER_GW_UDR			(0x00000080)
+#define LCDC_IER_GW_ERR			(0x00000040)
+#define LCDC_IER_GW_EOF			(0x00000020)
+#define LCDC_IER_GW_BOF			(0x00000010)
+#define LCDC_IER_UDR			(0x00000008)
+#define LCDC_IER_ERR			(0x00000004)
+#define LCDC_IER_EOF			(0x00000002)
+#define LCDC_IER_BOF			(0x00000001)
+
+/* Bit definitions and macros for LCDC_LGWSAR */
+#define LCDC_GWSAR_GWSA(x)		(((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LGWSR */
+#define LCDC_GWSR_GWW(x)		(((x)&0x0000003F)<<20)
+#define LCDC_GWSR_GWH(x)		((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LGWVPWR */
+#define LCDC_GWVPWR_GWVPW(x)		((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LGWPOR */
+#define LCDC_GWPOR_GWPO(x)		((x)&0x0000001F)
+
+/* Bit definitions and macros for LCDC_LGWPR */
+#define LCDC_GWPR_GWXP(x)		(((x)&0x000003FF)<<16)
+#define LCDC_GWPR_GWYP(x)		((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LGWCR */
+#define LCDC_GWCR_GWAV(x)		(((x)&0x000000FF)<<24)
+#define LCDC_GWCR_GWCKE			(0x00800000)
+#define LCDC_LGWCR_GWE			(0x00400000)
+#define LCDC_LGWCR_GW_RVS		(0x00200000)
+#define LCDC_LGWCR_GWCKR(x)		(((x)&0x0000003F)<<12)
+#define LCDC_LGWCR_GWCKG(x)		(((x)&0x0000003F)<<6)
+#define LCDC_LGWCR_GWCKB(x)		((x)&0x0000003F)
+
+/* Bit definitions and macros for LCDC_LGWDCR */
+#define LCDC_LGWDCR_GWBT		(0x80000000)
+#define LCDC_LGWDCR_GWHM(x)		(((x)&0x0000001F)<<16)
+#define LCDC_LGWDCR_GWTM(x)		((x)&0x0000001F)
+
+#endif				/* __LCDC_H__ */
diff --git a/include/asm-m68k/coldfire/ssi.h b/include/asm-m68k/coldfire/ssi.h
new file mode 100644
index 0000000..105c475
--- /dev/null
+++ b/include/asm-m68k/coldfire/ssi.h
@@ -0,0 +1,175 @@
+/*
+ * SSI Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SSI_H__
+#define __SSI_H__
+
+/*********************************************************************
+* Synchronous Serial Interface (SSI)
+*********************************************************************/
+
+typedef struct ssi {
+	u32 tx0;
+	u32 tx1;
+	u32 rx0;
+	u32 rx1;
+	u32 cr;
+	u32 isr;
+	u32 ier;
+	u32 tcr;
+	u32 rcr;
+	u32 ccr;
+	u8 resv0[0x4];
+	u32 fcsr;
+	u8 resv1[0x8];
+	u32 acr;
+	u32 acadd;
+	u32 acdat;
+	u32 atag;
+	u32 tmask;
+	u32 rmask;
+} ssi_t;
+
+/*********************************************************************
+* Synchronous Serial Interface (SSI)
+*********************************************************************/
+
+/* Bit definitions and macros for SSI_CR */
+#define SSI_CR_CIS			(0x00000200)
+#define SSI_CR_TCH			(0x00000100)
+#define SSI_CR_MCE			(0x00000080)
+#define SSI_CR_I2S_SLAVE		(0x00000040)
+#define SSI_CR_I2S_MASTER		(0x00000020)
+#define SSI_CR_I2S_NORMAL		(0x00000000)
+#define SSI_CR_SYN			(0x00000010)
+#define SSI_CR_NET			(0x00000008)
+#define SSI_CR_RE			(0x00000004)
+#define SSI_CR_TE			(0x00000002)
+#define SSI_CR_SSI_EN			(0x00000001)
+
+/* Bit definitions and macros for SSI_ISR */
+#define SSI_ISR_CMDAU			(0x00040000)
+#define SSI_ISR_CMDDU			(0x00020000)
+#define SSI_ISR_RXT			(0x00010000)
+#define SSI_ISR_RDR1			(0x00008000)
+#define SSI_ISR_RDR0			(0x00004000)
+#define SSI_ISR_TDE1			(0x00002000)
+#define SSI_ISR_TDE0			(0x00001000)
+#define SSI_ISR_ROE1			(0x00000800)
+#define SSI_ISR_ROE0			(0x00000400)
+#define SSI_ISR_TUE1			(0x00000200)
+#define SSI_ISR_TUE0			(0x00000100)
+#define SSI_ISR_TFS			(0x00000080)
+#define SSI_ISR_RFS			(0x00000040)
+#define SSI_ISR_TLS			(0x00000020)
+#define SSI_ISR_RLS			(0x00000010)
+#define SSI_ISR_RFF1			(0x00000008)
+#define SSI_ISR_RFF0			(0x00000004)
+#define SSI_ISR_TFE1			(0x00000002)
+#define SSI_ISR_TFE0			(0x00000001)
+
+/* Bit definitions and macros for SSI_IER */
+#define SSI_IER_RDMAE			(0x00400000)
+#define SSI_IER_RIE			(0x00200000)
+#define SSI_IER_TDMAE			(0x00100000)
+#define SSI_IER_TIE			(0x00080000)
+#define SSI_IER_CMDAU			(0x00040000)
+#define SSI_IER_CMDU			(0x00020000)
+#define SSI_IER_RXT			(0x00010000)
+#define SSI_IER_RDR1			(0x00008000)
+#define SSI_IER_RDR0			(0x00004000)
+#define SSI_IER_TDE1			(0x00002000)
+#define SSI_IER_TDE0			(0x00001000)
+#define SSI_IER_ROE1			(0x00000800)
+#define SSI_IER_ROE0			(0x00000400)
+#define SSI_IER_TUE1			(0x00000200)
+#define SSI_IER_TUE0			(0x00000100)
+#define SSI_IER_TFS			(0x00000080)
+#define SSI_IER_RFS			(0x00000040)
+#define SSI_IER_TLS			(0x00000020)
+#define SSI_IER_RLS			(0x00000010)
+#define SSI_IER_RFF1			(0x00000008)
+#define SSI_IER_RFF0			(0x00000004)
+#define SSI_IER_TFE1			(0x00000002)
+#define SSI_IER_TFE0			(0x00000001)
+
+/* Bit definitions and macros for SSI_TCR */
+#define SSI_TCR_TXBIT0			(0x00000200)
+#define SSI_TCR_TFEN1			(0x00000100)
+#define SSI_TCR_TFEN0			(0x00000080)
+#define SSI_TCR_TFDIR			(0x00000040)
+#define SSI_TCR_TXDIR			(0x00000020)
+#define SSI_TCR_TSHFD			(0x00000010)
+#define SSI_TCR_TSCKP			(0x00000008)
+#define SSI_TCR_TFSI			(0x00000004)
+#define SSI_TCR_TFSL			(0x00000002)
+#define SSI_TCR_TEFS			(0x00000001)
+
+/* Bit definitions and macros for SSI_RCR */
+#define SSI_RCR_RXEXT			(0x00000400)
+#define SSI_RCR_RXBIT0			(0x00000200)
+#define SSI_RCR_RFEN1			(0x00000100)
+#define SSI_RCR_RFEN0			(0x00000080)
+#define SSI_RCR_RSHFD			(0x00000010)
+#define SSI_RCR_RSCKP			(0x00000008)
+#define SSI_RCR_RFSI			(0x00000004)
+#define SSI_RCR_RFSL			(0x00000002)
+#define SSI_RCR_REFS			(0x00000001)
+
+/* Bit definitions and macros for SSI_CCR */
+#define SSI_CCR_DIV2			(0x00040000)
+#define SSI_CCR_PSR			(0x00020000)
+#define SSI_CCR_WL(x)			(((x)&0x0000000F)<<13)
+#define SSI_CCR_DC(x)			(((x)&0x0000001F)<<8)
+#define SSI_CCR_PM(x)			((x)&0x000000FF)
+
+/* Bit definitions and macros for SSI_FCSR */
+#define SSI_FCSR_RFCNT1(x)		(((x)&0x0000000F)<<28)
+#define SSI_FCSR_TFCNT1(x)		(((x)&0x0000000F)<<24)
+#define SSI_FCSR_RFWM1(x)		(((x)&0x0000000F)<<20)
+#define SSI_FCSR_TFWM1(x)		(((x)&0x0000000F)<<16)
+#define SSI_FCSR_RFCNT0(x)		(((x)&0x0000000F)<<12)
+#define SSI_FCSR_TFCNT0(x)		(((x)&0x0000000F)<<8)
+#define SSI_FCSR_RFWM0(x)		(((x)&0x0000000F)<<4)
+#define SSI_FCSR_TFWM0(x)		((x)&0x0000000F)
+
+/* Bit definitions and macros for SSI_ACR */
+#define SSI_ACR_FRDIV(x)		(((x)&0x0000003F)<<5)
+#define SSI_ACR_WR			(0x00000010)
+#define SSI_ACR_RD			(0x00000008)
+#define SSI_ACR_TIF			(0x00000004)
+#define SSI_ACR_FV			(0x00000002)
+#define SSI_ACR_AC97EN			(0x00000001)
+
+/* Bit definitions and macros for SSI_ACADD */
+#define SSI_ACADD_SSI_ACADD(x)		((x)&0x0007FFFF)
+
+/* Bit definitions and macros for SSI_ACDAT */
+#define SSI_ACDAT_SSI_ACDAT(x)		((x)&0x0007FFFF)
+
+/* Bit definitions and macros for SSI_ATAG */
+#define SSI_ATAG_DDI_ATAG(x)		((x)&0x0000FFFF)
+
+#endif					/* __SSI_H__ */
diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h
index 344c5e1..e639599 100644
--- a/include/asm-m68k/fec.h
+++ b/include/asm-m68k/fec.h
@@ -39,20 +39,20 @@ typedef struct cpm_buf_desc {
 	uint cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
-#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
-#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
-#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
-#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
-#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
-#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
-#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
-#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
-#define BD_SC_BR	((ushort)0x0020)	/* Break received */
-#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
-#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
-#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
-#define BD_SC_CD	((ushort)0x0001)	/* Carrier Detect lost */
+#define BD_SC_EMPTY		((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_READY		((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP		((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT		((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST		((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_TC		((ushort)0x0400)	/* Transmit CRC */
+#define BD_SC_CM		((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID		((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P			((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR		((ushort)0x0020)	/* Break received */
+#define BD_SC_FR		((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR		((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV		((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD		((ushort)0x0001)	/* Carrier Detect lost */
 
 /* Buffer descriptor control/status used by Ethernet receive.
 */
@@ -95,11 +95,8 @@ typedef struct cpm_buf_desc {
 #define BD_ENET_TX_CSL		((ushort)0x0001)
 #define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
 
-#ifdef CONFIG_MCFFEC
 /*********************************************************************
-*
 * Fast Ethernet Controller (FEC)
-*
 *********************************************************************/
 /* FEC private information */
 struct fec_info_s {
@@ -117,8 +114,10 @@ struct fec_info_s {
 	uint txIdx;
 	char *txbuf;
 	int initialized;
+	struct fec_info_s *next;
 };
 
+#ifdef CONFIG_MCFFEC
 /* Register read/write struct */
 typedef struct fec {
 #ifdef CONFIG_M5272
@@ -254,90 +253,91 @@ typedef struct fec {
 	u32 ieee_r_fdxfc;
 	u32 ieee_r_octets_ok;
 } fec_t;
+#endif				/* CONFIG_MCFFEC */
 
 /*********************************************************************
 * Fast Ethernet Controller (FEC)
 *********************************************************************/
 /* Bit definitions and macros for FEC_EIR */
-#define FEC_EIR_CLEAR_ALL	(0xFFF80000)
-#define FEC_EIR_HBERR		(0x80000000)
-#define FEC_EIR_BABR		(0x40000000)
-#define FEC_EIR_BABT		(0x20000000)
-#define FEC_EIR_GRA		(0x10000000)
-#define FEC_EIR_TXF		(0x08000000)
-#define FEC_EIR_TXB		(0x04000000)
-#define FEC_EIR_RXF		(0x02000000)
-#define FEC_EIR_RXB		(0x01000000)
-#define FEC_EIR_MII		(0x00800000)
-#define FEC_EIR_EBERR		(0x00400000)
-#define FEC_EIR_LC		(0x00200000)
-#define FEC_EIR_RL		(0x00100000)
-#define FEC_EIR_UN		(0x00080000)
+#define FEC_EIR_CLEAR_ALL		(0xFFF80000)
+#define FEC_EIR_HBERR			(0x80000000)
+#define FEC_EIR_BABR			(0x40000000)
+#define FEC_EIR_BABT			(0x20000000)
+#define FEC_EIR_GRA			(0x10000000)
+#define FEC_EIR_TXF			(0x08000000)
+#define FEC_EIR_TXB			(0x04000000)
+#define FEC_EIR_RXF			(0x02000000)
+#define FEC_EIR_RXB			(0x01000000)
+#define FEC_EIR_MII			(0x00800000)
+#define FEC_EIR_EBERR			(0x00400000)
+#define FEC_EIR_LC			(0x00200000)
+#define FEC_EIR_RL			(0x00100000)
+#define FEC_EIR_UN			(0x00080000)
 
 /* Bit definitions and macros for FEC_RDAR */
-#define FEC_RDAR_R_DES_ACTIVE	(0x01000000)
+#define FEC_RDAR_R_DES_ACTIVE		(0x01000000)
 
 /* Bit definitions and macros for FEC_TDAR */
-#define FEC_TDAR_X_DES_ACTIVE	(0x01000000)
+#define FEC_TDAR_X_DES_ACTIVE		(0x01000000)
 
 /* Bit definitions and macros for FEC_ECR */
-#define FEC_ECR_ETHER_EN	(0x00000002)
-#define FEC_ECR_RESET		(0x00000001)
+#define FEC_ECR_ETHER_EN		(0x00000002)
+#define FEC_ECR_RESET			(0x00000001)
 
 /* Bit definitions and macros for FEC_MMFR */
-#define FEC_MMFR_DATA(x)	(((x)&0xFFFF))
-#define FEC_MMFR_ST(x)		(((x)&0x03)<<30)
-#define FEC_MMFR_ST_01		(0x40000000)
-#define FEC_MMFR_OP_RD		(0x20000000)
-#define FEC_MMFR_OP_WR		(0x10000000)
-#define FEC_MMFR_PA(x)		(((x)&0x1F)<<23)
-#define FEC_MMFR_RA(x)		(((x)&0x1F)<<18)
-#define FEC_MMFR_TA(x)		(((x)&0x03)<<16)
-#define FEC_MMFR_TA_10		(0x00020000)
+#define FEC_MMFR_DATA(x)		(((x)&0xFFFF))
+#define FEC_MMFR_ST(x)			(((x)&0x03)<<30)
+#define FEC_MMFR_ST_01			(0x40000000)
+#define FEC_MMFR_OP_RD			(0x20000000)
+#define FEC_MMFR_OP_WR			(0x10000000)
+#define FEC_MMFR_PA(x)			(((x)&0x1F)<<23)
+#define FEC_MMFR_RA(x)			(((x)&0x1F)<<18)
+#define FEC_MMFR_TA(x)			(((x)&0x03)<<16)
+#define FEC_MMFR_TA_10			(0x00020000)
 
 /* Bit definitions and macros for FEC_MSCR */
-#define FEC_MSCR_DIS_PREAMBLE	(0x00000080)
-#define FEC_MSCR_MII_SPEED(x)	(((x)&0x3F)<<1)
+#define FEC_MSCR_DIS_PREAMBLE		(0x00000080)
+#define FEC_MSCR_MII_SPEED(x)		(((x)&0x3F)<<1)
 
 /* Bit definitions and macros for FEC_MIBC */
-#define FEC_MIBC_MIB_DISABLE	(0x80000000)
-#define FEC_MIBC_MIB_IDLE	(0x40000000)
+#define FEC_MIBC_MIB_DISABLE		(0x80000000)
+#define FEC_MIBC_MIB_IDLE		(0x40000000)
 
 /* Bit definitions and macros for FEC_RCR */
-#define FEC_RCR_MAX_FL(x)	(((x)&0x7FF)<<16)
-#define FEC_RCR_FCE		(0x00000020)
-#define FEC_RCR_BC_REJ		(0x00000010)
-#define FEC_RCR_PROM		(0x00000008)
-#define FEC_RCR_MII_MODE	(0x00000004)
-#define FEC_RCR_DRT		(0x00000002)
-#define FEC_RCR_LOOP		(0x00000001)
+#define FEC_RCR_MAX_FL(x)		(((x)&0x7FF)<<16)
+#define FEC_RCR_FCE			(0x00000020)
+#define FEC_RCR_BC_REJ			(0x00000010)
+#define FEC_RCR_PROM			(0x00000008)
+#define FEC_RCR_MII_MODE		(0x00000004)
+#define FEC_RCR_DRT			(0x00000002)
+#define FEC_RCR_LOOP			(0x00000001)
 
 /* Bit definitions and macros for FEC_TCR */
-#define FEC_TCR_RFC_PAUSE	(0x00000010)
-#define FEC_TCR_TFC_PAUSE	(0x00000008)
-#define FEC_TCR_FDEN		(0x00000004)
-#define FEC_TCR_HBC		(0x00000002)
-#define FEC_TCR_GTS		(0x00000001)
+#define FEC_TCR_RFC_PAUSE		(0x00000010)
+#define FEC_TCR_TFC_PAUSE		(0x00000008)
+#define FEC_TCR_FDEN			(0x00000004)
+#define FEC_TCR_HBC			(0x00000002)
+#define FEC_TCR_GTS			(0x00000001)
 
 /* Bit definitions and macros for FEC_PAUR */
-#define FEC_PAUR_PADDR2(x)	(((x)&0xFFFF)<<16)
-#define FEC_PAUR_TYPE(x)	((x)&0xFFFF)
+#define FEC_PAUR_PADDR2(x)		(((x)&0xFFFF)<<16)
+#define FEC_PAUR_TYPE(x)		((x)&0xFFFF)
 
 /* Bit definitions and macros for FEC_OPD */
-#define FEC_OPD_PAUSE_DUR(x)	(((x)&0x0000FFFF)<<0)
-#define FEC_OPD_OPCODE(x)	(((x)&0x0000FFFF)<<16)
+#define FEC_OPD_PAUSE_DUR(x)		(((x)&0x0000FFFF)<<0)
+#define FEC_OPD_OPCODE(x)		(((x)&0x0000FFFF)<<16)
 
 /* Bit definitions and macros for FEC_TFWR */
-#define FEC_TFWR_X_WMRK(x)	((x)&0x03)
-#define FEC_TFWR_X_WMRK_64	(0x01)
-#define FEC_TFWR_X_WMRK_128	(0x02)
-#define FEC_TFWR_X_WMRK_192	(0x03)
+#define FEC_TFWR_X_WMRK(x)		((x)&0x03)
+#define FEC_TFWR_X_WMRK_64		(0x01)
+#define FEC_TFWR_X_WMRK_128		(0x02)
+#define FEC_TFWR_X_WMRK_192		(0x03)
 
 /* Bit definitions and macros for FEC_FRBR */
-#define FEC_FRBR_R_BOUND(x)	(((x)&0xFF)<<2)
+#define FEC_FRBR_R_BOUND(x)		(((x)&0xFF)<<2)
 
 /* Bit definitions and macros for FEC_FRSR */
-#define FEC_FRSR_R_FSTART(x)	(((x)&0xFF)<<2)
+#define FEC_FRSR_R_FSTART(x)		(((x)&0xFF)<<2)
 
 /* Bit definitions and macros for FEC_ERDSR */
 #define FEC_ERDSR_R_DES_START(x)	(((x)&0x3FFFFFFF)<<2)
@@ -348,8 +348,7 @@ typedef struct fec {
 /* Bit definitions and macros for FEC_EMRBR */
 #define FEC_EMRBR_R_BUF_SIZE(x)		(((x)&0x7F)<<4)
 
-#define	FEC_RESET_DELAY		100
-#define FEC_RX_TOUT		100
+#define	FEC_RESET_DELAY			100
+#define FEC_RX_TOUT			100
 
-#endif				/* CONFIG_MCFFEC */
 #endif				/* fec_h */
diff --git a/include/asm-m68k/fsl_mcdmafec.h b/include/asm-m68k/fsl_mcdmafec.h
new file mode 100644
index 0000000..82da593
--- /dev/null
+++ b/include/asm-m68k/fsl_mcdmafec.h
@@ -0,0 +1,176 @@
+/*
+ * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef fsl_mcdmafec_h
+#define fsl_mcdmafec_h
+
+/* Re-use of the definitions */
+#include <asm/fec.h>
+
+typedef struct fecdma {
+	u32 rsvd0;		/* 0x000 */
+	u32 eir;		/* 0x004 */
+	u32 eimr;		/* 0x008 */
+	u32 rsvd1[6];		/* 0x00C - 0x023 */
+	u32 ecr;		/* 0x024 */
+	u32 rsvd2[6];		/* 0x028 - 0x03F */
+	u32 mmfr;		/* 0x040 */
+	u32 mscr;		/* 0x044 */
+	u32 rsvd3[7];		/* 0x048 - 0x063 */
+	u32 mibc;		/* 0x064 */
+	u32 rsvd4[7];		/* 0x068 - 0x083 */
+	u32 rcr;		/* 0x084 */
+	u32 rhr;		/* 0x088 */
+	u32 rsvd5[14];		/* 0x08C - 0x0C3 */
+	u32 tcr;		/* 0x0C4 */
+	u32 rsvd6[7];		/* 0x0C8 - 0x0E3 */
+	u32 palr;		/* 0x0E4 */
+	u32 paur;		/* 0x0E8 */
+	u32 opd;		/* 0x0EC */
+	u32 rsvd7[10];		/* 0x0F0 - 0x117 */
+	u32 iaur;		/* 0x118 */
+	u32 ialr;		/* 0x11C */
+	u32 gaur;		/* 0x120 */
+	u32 galr;		/* 0x124 */
+	u32 rsvd8[7];		/* 0x128 - 0x143 */
+	u32 tfwr;		/* 0x144 */
+	u32 rsvd9[14];		/* 0x148 - 0x17F */
+	u32 fmc;		/* 0x180 */
+	u32 rfdr;		/* 0x184 */
+	u32 rfsr;		/* 0x188 */
+	u32 rfcr;		/* 0x18C */
+	u32 rlrfp;		/* 0x190 */
+	u32 rlwfp;		/* 0x194 */
+	u32 rfar;		/* 0x198 */
+	u32 rfrp;		/* 0x19C */
+	u32 rfwp;		/* 0x1A0 */
+	u32 tfdr;		/* 0x1A4 */
+	u32 tfsr;		/* 0x1A8 */
+	u32 tfcr;		/* 0x1AC */
+	u32 tlrfp;		/* 0x1B0 */
+	u32 tlwfp;		/* 0x1B4 */
+	u32 tfar;		/* 0x1B8 */
+	u32 tfrp;		/* 0x1BC */
+	u32 tfwp;		/* 0x1C0 */
+	u32 frst;		/* 0x1C4 */
+	u32 ctcwr;		/* 0x1C8 */
+} fecdma_t;
+
+struct fec_info_dma {
+	int index;
+	u32 iobase;
+	u32 pinmux;
+	u32 miibase;
+	int phy_addr;
+	int dup_spd;
+	char *phy_name;
+	int phyname_init;
+	cbd_t *rxbd;		/* Rx BD */
+	cbd_t *txbd;		/* Tx BD */
+	uint rxIdx;
+	uint txIdx;
+	char *txbuf;
+	int initialized;
+	struct fec_info_dma *next;
+
+	u16 rxTask;		/* DMA receive Task Number */
+	u16 txTask;		/* DMA Transmit Task Number */
+	u16 rxPri;		/* DMA Receive Priority */
+	u16 txPri;		/* DMA Transmit Priority */
+	u16 rxInit;		/* DMA Receive Initiator */
+	u16 txInit;		/* DMA Transmit Initiator */
+	u16 usedTbdIdx;		/* next transmit BD to clean */
+	u16 cleanTbdNum;	/* the number of available transmit BDs */
+};
+
+/* Bit definitions and macros for IEVENT */
+#define FEC_EIR_TXERR		(0x00040000)
+#define FEC_EIR_RXERR		(0x00020000)
+#undef FEC_EIR_CLEAR_ALL
+#define FEC_EIR_CLEAR_ALL	(0xFFFE0000)
+
+/* Bit definitions and macros for R_HASH */
+#define FEC_RHASH_FCE_DC	(0x80000000)
+#define FEC_RHASH_MULTCAST	(0x40000000)
+#define FEC_RHASH_HASH(x)	(((x)&0x0000003F)<<24)
+
+/* Bit definitions and macros for FEC_TFWR */
+#undef FEC_TFWR_X_WMRK
+#undef FEC_TFWR_X_WMRK_64
+#undef FEC_TFWR_X_WMRK_128
+#undef FEC_TFWR_X_WMRK_192
+
+#define FEC_TFWR_X_WMRK(x)	((x)&0x0F)
+#define FEC_TFWR_X_WMRK_64	(0x00)
+#define FEC_TFWR_X_WMRK_128	(0x01)
+#define FEC_TFWR_X_WMRK_192	(0x02)
+#define FEC_TFWR_X_WMRK_256	(0x03)
+#define FEC_TFWR_X_WMRK_320	(0x04)
+#define FEC_TFWR_X_WMRK_384	(0x05)
+#define FEC_TFWR_X_WMRK_448	(0x06)
+#define FEC_TFWR_X_WMRK_512	(0x07)
+#define FEC_TFWR_X_WMRK_576	(0x08)
+#define FEC_TFWR_X_WMRK_640	(0x09)
+#define FEC_TFWR_X_WMRK_704	(0x0A)
+#define FEC_TFWR_X_WMRK_768	(0x0B)
+#define FEC_TFWR_X_WMRK_832	(0x0C)
+#define FEC_TFWR_X_WMRK_896	(0x0D)
+#define FEC_TFWR_X_WMRK_960	(0x0E)
+#define FEC_TFWR_X_WMRK_1024	(0x0F)
+
+/* FIFO definitions */
+/* Bit definitions and macros for FSTAT */
+#define FIFO_STAT_IP		(0x80000000)
+#define FIFO_STAT_FRAME(x)	(((x)&0x0000000F)<<24)
+#define FIFO_STAT_FAE		(0x00800000)
+#define FIFO_STAT_RXW		(0x00400000)
+#define FIFO_STAT_UF		(0x00200000)
+#define FIFO_STAT_OF		(0x00100000)
+#define FIFO_STAT_FR		(0x00080000)
+#define FIFO_STAT_FULL		(0x00040000)
+#define FIFO_STAT_ALARM		(0x00020000)
+#define FIFO_STAT_EMPTY		(0x00010000)
+
+/* Bit definitions and macros for FCTRL */
+#define FIFO_CTRL_WCTL		(0x40000000)
+#define FIFO_CTRL_WFR		(0x20000000)
+#define FIFO_CTRL_FRAME		(0x08000000)
+#define FIFO_CTRL_GR(x)		(((x)&0x00000007)<<24)
+#define FIFO_CTRL_IPMASK	(0x00800000)
+#define FIFO_CTRL_FAEMASK	(0x00400000)
+#define FIFO_CTRL_RXWMASK	(0x00200000)
+#define FIFO_CTRL_UFMASK	(0x00100000)
+#define FIFO_CTRL_OFMASK	(0x00080000)
+
+int fecpin_setclear(struct eth_device *dev, int setclear);
+void mii_init(void);
+uint mii_send(uint mii_cmd);
+int mii_discover_phy(struct eth_device *dev);
+int mcffec_miiphy_read(char *devname, unsigned char addr,
+		       unsigned char reg, unsigned short *value);
+int mcffec_miiphy_write(char *devname, unsigned char addr,
+			unsigned char reg, unsigned short value);
+
+#endif				/* fsl_mcdmafec_h */
diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h
index 9d9894b..1e26eb0 100644
--- a/include/asm-m68k/global_data.h
+++ b/include/asm-m68k/global_data.h
@@ -53,6 +53,9 @@ typedef	struct	global_data {
 	unsigned long	env_addr;	/* Address  of Environment struct	*/
 	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
 	unsigned long	have_console;	/* serial_init() was called		*/
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
+	unsigned long	fb_base;	/* Base addr of framebuffer memory */
+#endif
 #ifdef CONFIG_BOARD_TYPES
 	unsigned long	board_type;
 #endif
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index ffb9a37..916bf96 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -26,6 +26,40 @@
 #ifndef __IMMAP_H
 #define __IMMAP_H
 
+#ifdef CONFIG_M52277
+#include <asm/immap_5227x.h>
+#include <asm/m5227x.h>
+
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x4000))
+
+#define CFG_MCFRTC_BASE		(MMAP_RTC)
+
+#ifdef CONFIG_LCD
+#define	CFG_LCD_BASE		(MMAP_LCD)
+#endif
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_TMR_BASE		(MMAP_DTMR1)
+#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CFG_TMRINTR_MASK	(INTC_IPRH_INT33)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(6)
+#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE		(MMAP_PIT0)
+#define CFG_PIT_BASE		(MMAP_PIT1)
+#define CFG_PIT_PRESCALE	(6)
+#endif
+
+#define CFG_INTR_BASE		(MMAP_INTC0)
+#define CFG_NUM_IRQS		(128)
+#endif				/* CONFIG_M52277 */
+
 #ifdef CONFIG_M5235
 #include <asm/immap_5235.h>
 #include <asm/m5235.h>
@@ -169,7 +203,7 @@
 #endif
 #endif				/* CONFIG_M5282 */
 
-#ifdef CONFIG_M5329
+#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
 #include <asm/immap_5329.h>
 #include <asm/m5329.h>
 
@@ -197,7 +231,7 @@
 
 #define CFG_INTR_BASE		(MMAP_INTC0)
 #define CFG_NUM_IRQS		(128)
-#endif				/* CONFIG_M5329 */
+#endif				/* CONFIG_M5329 && CONFIG_M5373 */
 
 #ifdef CONFIG_M54455
 #include <asm/immap_5445x.h>
@@ -232,11 +266,104 @@
 #define CFG_NUM_IRQS		(128)
 
 #ifdef CONFIG_PCI
-#define CFG_PCI_BAR0		CFG_SDRAM_BASE
-#define CFG_PCI_BAR4		CFG_SDRAM_BASE
-#define CFG_PCI_TBATR0		(CFG_SDRAM_BASE)
-#define CFG_PCI_TBATR4		(CFG_SDRAM_BASE)
+#define CFG_PCI_BAR0		(CFG_MBAR)
+#define CFG_PCI_BAR5		(CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0		(CFG_MBAR)
+#define CFG_PCI_TBATR5		(CFG_SDRAM_BASE)
 #endif
 #endif				/* CONFIG_M54455 */
 
+#ifdef CONFIG_M547x
+#include <asm/immap_547x_8x.h>
+#include <asm/m547x_8x.h>
+
+#ifdef CONFIG_FSLDMAFEC
+#define CFG_FEC0_IOBASE		(MMAP_FEC0)
+#define CFG_FEC1_IOBASE		(MMAP_FEC1)
+
+#define FEC0_RX_TASK		0
+#define FEC0_TX_TASK		1
+#define FEC0_RX_PRIORITY	6
+#define FEC0_TX_PRIORITY	7
+#define FEC0_RX_INIT		16
+#define FEC0_TX_INIT		17
+#define FEC1_RX_TASK		2
+#define FEC1_TX_TASK		3
+#define FEC1_RX_PRIORITY	6
+#define FEC1_TX_PRIORITY	7
+#define FEC1_RX_INIT		30
+#define FEC1_TX_INIT		31
+#endif
+
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x100))
+
+#ifdef CONFIG_SLTTMR
+#define CFG_UDELAY_BASE		(MMAP_SLT1)
+#define CFG_TMR_BASE		(MMAP_SLT0)
+#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO		(INT0_HI_SLT0)
+#define CFG_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(0x1E)
+#define CFG_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#endif
+
+#define CFG_INTR_BASE		(MMAP_INTC0)
+#define CFG_NUM_IRQS		(128)
+
+#ifdef CONFIG_PCI
+#define CFG_PCI_BAR0		(0x40000000)
+#define CFG_PCI_BAR1		(CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0		(CFG_MBAR)
+#define CFG_PCI_TBATR1		(CFG_SDRAM_BASE)
+#endif
+#endif				/* CONFIG_M547x */
+
+#ifdef CONFIG_M548x
+#include <asm/immap_547x_8x.h>
+#include <asm/m547x_8x.h>
+
+#ifdef CONFIG_FSLDMAFEC
+#define CFG_FEC0_IOBASE		(MMAP_FEC0)
+#define CFG_FEC1_IOBASE		(MMAP_FEC1)
+
+#define FEC0_RX_TASK		0
+#define FEC0_TX_TASK		1
+#define FEC0_RX_PRIORITY	6
+#define FEC0_TX_PRIORITY	7
+#define FEC0_RX_INIT		16
+#define FEC0_TX_INIT		17
+#define FEC1_RX_TASK		2
+#define FEC1_TX_TASK		3
+#define FEC1_RX_PRIORITY	6
+#define FEC1_TX_PRIORITY	7
+#define FEC1_RX_INIT		30
+#define FEC1_TX_INIT		31
+#endif
+
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x100))
+
+/* Timer */
+#ifdef CONFIG_SLTTMR
+#define CFG_UDELAY_BASE		(MMAP_SLT1)
+#define CFG_TMR_BASE		(MMAP_SLT0)
+#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO		(INT0_HI_SLT0)
+#define CFG_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(0x1E)
+#define CFG_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#endif
+
+#define CFG_INTR_BASE		(MMAP_INTC0)
+#define CFG_NUM_IRQS		(128)
+
+#ifdef CONFIG_PCI
+#define CFG_PCI_BAR0		(CFG_MBAR)
+#define CFG_PCI_BAR1		(CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0		(CFG_MBAR)
+#define CFG_PCI_TBATR1		(CFG_SDRAM_BASE)
+#endif
+#endif				/* CONFIG_M548x */
+
 #endif				/* __IMMAP_H */
diff --git a/include/asm-m68k/immap_5227x.h b/include/asm-m68k/immap_5227x.h
new file mode 100644
index 0000000..1d1e6f1
--- /dev/null
+++ b/include/asm-m68k/immap_5227x.h
@@ -0,0 +1,343 @@
+/*
+ * MCF5227x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5227X__
+#define __IMMAP_5227X__
+
+/* Module Base Addresses */
+#define MMAP_SCM1	(CFG_MBAR + 0x00000000)
+#define MMAP_XBS	(CFG_MBAR + 0x00004000)
+#define MMAP_FBCS	(CFG_MBAR + 0x00008000)
+#define MMAP_CAN	(CFG_MBAR + 0x00020000)
+#define MMAP_RTC	(CFG_MBAR + 0x0003C000)
+#define MMAP_SCM2	(CFG_MBAR + 0x00040010)
+#define MMAP_SCM3	(CFG_MBAR + 0x00040070)
+#define MMAP_EDMA	(CFG_MBAR + 0x00044000)
+#define MMAP_INTC0	(CFG_MBAR + 0x00048000)
+#define MMAP_INTC1	(CFG_MBAR + 0x0004C000)
+#define MMAP_IACK	(CFG_MBAR + 0x00054000)
+#define MMAP_I2C	(CFG_MBAR + 0x00058000)
+#define MMAP_DSPI	(CFG_MBAR + 0x0005C000)
+#define MMAP_UART0	(CFG_MBAR + 0x00060000)
+#define MMAP_UART1	(CFG_MBAR + 0x00064000)
+#define MMAP_UART2	(CFG_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CFG_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CFG_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CFG_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CFG_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CFG_MBAR + 0x00080000)
+#define MMAP_PIT1	(CFG_MBAR + 0x00084000)
+#define MMAP_PWM	(CFG_MBAR + 0x00090000)
+#define MMAP_EPORT	(CFG_MBAR + 0x00094000)
+#define MMAP_RCM	(CFG_MBAR + 0x000A0000)
+#define MMAP_CCM	(CFG_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CFG_MBAR + 0x000A4000)
+#define MMAP_ADC	(CFG_MBAR + 0x000A8000)
+#define MMAP_LCD	(CFG_MBAR + 0x000AC000)
+#define MMAP_LCD_BGLUT	(CFG_MBAR + 0x000AC800)
+#define MMAP_LCD_GWLUT	(CFG_MBAR + 0x000ACC00)
+#define MMAP_USBHW	(CFG_MBAR + 0x000B0000)
+#define MMAP_USBCAPS	(CFG_MBAR + 0x000B0100)
+#define MMAP_USBEHCI	(CFG_MBAR + 0x000B0140)
+#define MMAP_USBOTG	(CFG_MBAR + 0x000B01A0)
+#define MMAP_SDRAM	(CFG_MBAR + 0x000B8000)
+#define MMAP_SSI	(CFG_MBAR + 0x000BC000)
+#define MMAP_PLL	(CFG_MBAR + 0x000C0000)
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/lcd.h>
+#include <asm/coldfire/ssi.h>
+
+/* Interrupt Controller (INTC) */
+typedef struct int0_ctrl {
+	u32 iprh0;		/* 0x00 Pending Register High */
+	u32 iprl0;		/* 0x04 Pending Register Low */
+	u32 imrh0;		/* 0x08 Mask Register High */
+	u32 imrl0;		/* 0x0C Mask Register Low */
+	u32 frch0;		/* 0x10 Force Register High */
+	u32 frcl0;		/* 0x14 Force Register Low */
+	u16 res1;		/* 0x18 - 0x19 */
+	u16 icfg0;		/* 0x1A Configuration Register */
+	u8 simr0;		/* 0x1C Set Interrupt Mask */
+	u8 cimr0;		/* 0x1D Clear Interrupt Mask */
+	u8 clmask0;		/* 0x1E Current Level Mask */
+	u8 slmask;		/* 0x1F Saved Level Mask */
+	u32 res2[8];		/* 0x20 - 0x3F */
+	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
+	u32 res3[24];		/* 0x80 - 0xDF */
+	u8 swiack0;		/* 0xE0 Software Interrupt ack */
+	u8 res4[3];		/* 0xE1 - 0xE3 */
+	u8 Lniack0_1;		/* 0xE4 Level n interrupt ack */
+	u8 res5[3];		/* 0xE5 - 0xE7 */
+	u8 Lniack0_2;		/* 0xE8 Level n interrupt ack */
+	u8 res6[3];		/* 0xE9 - 0xEB */
+	u8 Lniack0_3;		/* 0xEC Level n interrupt ack */
+	u8 res7[3];		/* 0xED - 0xEF */
+	u8 Lniack0_4;		/* 0xF0 Level n interrupt ack */
+	u8 res8[3];		/* 0xF1 - 0xF3 */
+	u8 Lniack0_5;		/* 0xF4 Level n interrupt ack */
+	u8 res9[3];		/* 0xF5 - 0xF7 */
+	u8 Lniack0_6;		/* 0xF8 Level n interrupt ack */
+	u8 resa[3];		/* 0xF9 - 0xFB */
+	u8 Lniack0_7;		/* 0xFC Level n interrupt ack */
+	u8 resb[3];		/* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+	/* Interrupt Controller 1 */
+	u32 iprh1;		/* 0x00 Pending Register High */
+	u32 iprl1;		/* 0x04 Pending Register Low */
+	u32 imrh1;		/* 0x08 Mask Register High */
+	u32 imrl1;		/* 0x0C Mask Register Low */
+	u32 frch1;		/* 0x10 Force Register High */
+	u32 frcl1;		/* 0x14 Force Register Low */
+	u16 res1;		/* 0x18 */
+	u16 icfg1;		/* 0x1A Configuration Register */
+	u8 simr1;		/* 0x1C Set Interrupt Mask */
+	u8 cimr1;		/* 0x1D Clear Interrupt Mask */
+	u16 res2;		/* 0x1E - 0x1F */
+	u32 res3[8];		/* 0x20 - 0x3F */
+	u8 icr1[64];		/* 0x40 - 0x7F */
+	u32 res4[24];		/* 0x80 - 0xDF */
+	u8 swiack1;		/* 0xE0 Software Interrupt ack */
+	u8 res5[3];		/* 0xE1 - 0xE3 */
+	u8 Lniack1_1;		/* 0xE4 Level n interrupt ack */
+	u8 res6[3];		/* 0xE5 - 0xE7 */
+	u8 Lniack1_2;		/* 0xE8 Level n interrupt ack */
+	u8 res7[3];		/* 0xE9 - 0xEB */
+	u8 Lniack1_3;		/* 0xEC Level n interrupt ack */
+	u8 res8[3];		/* 0xED - 0xEF */
+	u8 Lniack1_4;		/* 0xF0 Level n interrupt ack */
+	u8 res9[3];		/* 0xF1 - 0xF3 */
+	u8 Lniack1_5;		/* 0xF4 Level n interrupt ack */
+	u8 resa[3];		/* 0xF5 - 0xF7 */
+	u8 Lniack1_6;		/* 0xF8 Level n interrupt ack */
+	u8 resb[3];		/* 0xF9 - 0xFB */
+	u8 Lniack1_7;		/* 0xFC Level n interrupt ack */
+	u8 resc[3];		/* 0xFD - 0xFF */
+} int1_t;
+
+/* Global Interrupt Acknowledge (IACK) */
+typedef struct iack {
+	u8 resv0[0xE0];
+	u8 gswiack;
+	u8 resv1[0x3];
+	u8 gl1iack;
+	u8 resv2[0x3];
+	u8 gl2iack;
+	u8 resv3[0x3];
+	u8 gl3iack;
+	u8 resv4[0x3];
+	u8 gl4iack;
+	u8 resv5[0x3];
+	u8 gl5iack;
+	u8 resv6[0x3];
+	u8 gl6iack;
+	u8 resv7[0x3];
+	u8 gl7iack;
+} iack_t;
+
+/* Edge Port Module (EPORT) */
+typedef struct eport {
+	u16 eppar;
+	u8 epddr;
+	u8 epier;
+	u8 epdr;
+	u8 eppdr;
+	u8 epfr;
+} eport_t;
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+	u16 ccr;		/* Chip Configuration (Rd-only) */
+	u16 resv1;
+	u16 rcon;		/* Reset Configuration (Rd-only) */
+	u16 cir;		/* Chip Identification (Rd-only) */
+	u32 resv2;
+	u16 misccr;		/* Miscellaneous Control */
+	u16 cdr;		/* Clock Divider */
+	u16 uocsr;		/* USB On-the-Go Controller Status */
+	u16 resv4;
+	u16 sbfsr;		/* Serial Boot Status */
+	u16 sbfcr;		/* Serial Boot Control */
+} ccm_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+	/* Port Output Data Registers */
+	u8 podr_be;		/* 0x00 */
+	u8 podr_cs;		/* 0x01 */
+	u8 podr_fbctl;		/* 0x02 */
+	u8 podr_i2c;		/* 0x03 */
+	u8 rsvd1;		/* 0x04 */
+	u8 podr_uart;		/* 0x05 */
+	u8 podr_dspi;		/* 0x06 */
+	u8 podr_timer;		/* 0x07 */
+	u8 podr_lcdctl;		/* 0x08 */
+	u8 podr_lcddatah;	/* 0x09 */
+	u8 podr_lcddatam;	/* 0x0A */
+	u8 podr_lcddatal;	/* 0x0B */
+
+	/* Port Data Direction Registers */
+	u8 pddr_be;		/* 0x0C */
+	u8 pddr_cs;		/* 0x0D */
+	u8 pddr_fbctl;		/* 0x0E */
+	u8 pddr_i2c;		/* 0x0F */
+	u8 rsvd2;		/* 0x10 */
+	u8 pddr_uart;		/* 0x11 */
+	u8 pddr_dspi;		/* 0x12 */
+	u8 pddr_timer;		/* 0x13 */
+	u8 pddr_lcdctl;		/* 0x14 */
+	u8 pddr_lcddatah;	/* 0x15 */
+	u8 pddr_lcddatam;	/* 0x16 */
+	u8 pddr_lcddatal;	/* 0x17 */
+
+	/* Port Pin Data/Set Data Registers */
+	u8 ppdsdr_be;		/* 0x18 */
+	u8 ppdsdr_cs;		/* 0x19 */
+	u8 ppdsdr_fbctl;	/* 0x1A */
+	u8 ppdsdr_i2c;		/* 0x1B */
+	u8 rsvd3;		/* 0x1C */
+	u8 ppdsdr_uart;		/* 0x1D */
+	u8 ppdsdr_dspi;		/* 0x1E */
+	u8 ppdsdr_timer;	/* 0x1F */
+	u8 ppdsdr_lcdctl;	/* 0x20 */
+	u8 ppdsdr_lcddatah;	/* 0x21 */
+	u8 ppdsdr_lcddatam;	/* 0x22 */
+	u8 ppdsdr_lcddatal;	/* 0x23 */
+
+	/* Port Clear Output Data Registers */
+	u8 pclrr_be;		/* 0x24 */
+	u8 pclrr_cs;		/* 0x25 */
+	u8 pclrr_fbctl;		/* 0x26 */
+	u8 pclrr_i2c;		/* 0x27 */
+	u8 rsvd4;		/* 0x28 */
+	u8 pclrr_uart;		/* 0x29 */
+	u8 pclrr_dspi;		/* 0x2A */
+	u8 pclrr_timer;		/* 0x2B */
+	u8 pclrr_lcdctl;	/* 0x2C */
+	u8 pclrr_lcddatah;	/* 0x2D */
+	u8 pclrr_lcddatam;	/* 0x2E */
+	u8 pclrr_lcddatal;	/* 0x2F */
+
+	/* Pin Assignment Registers */
+	u8 par_be;		/* 0x30 */
+	u8 par_cs;		/* 0x31 */
+	u8 par_fbctl;		/* 0x32 */
+	u8 par_i2c;		/* 0x33 */
+	u16 par_uart;		/* 0x34 */
+	u8 par_dspi;		/* 0x36 */
+	u8 par_timer;		/* 0x37 */
+	u8 par_lcdctl;		/* 0x38 */
+	u8 par_irq;		/* 0x39 */
+	u16 rsvd6;		/* 0x3A - 0x3B */
+	u32 par_lcdh;		/* 0x3C */
+	u32 par_lcdl;		/* 0x40 */
+
+	/* Mode select control registers */
+	u8 mscr_fb;		/* 0x44 */
+	u8 mscr_sdram;		/* 0x45 */
+
+	u16 rsvd7;		/* 0x46 - 0x47 */
+	u8 dscr_dspi;		/* 0x48 */
+	u8 dscr_timer;		/* 0x49 */
+	u8 dscr_i2c;		/* 0x4A */
+	u8 dscr_lcd;		/* 0x4B */
+	u8 dscr_debug;		/* 0x4C */
+	u8 dscr_clkrst;		/* 0x4D */
+	u8 dscr_irq;		/* 0x4E */
+	u8 dscr_uart;		/* 0x4F */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+	u32 sdmr;		/* Mode/Extended Mode */
+	u32 sdcr;		/* Control */
+	u32 sdcfg1;		/* Configuration 1 */
+	u32 sdcfg2;		/* Chip Select */
+	u8 resv0[0x100];
+	u32 sdcs0;		/* Mode/Extended Mode */
+	u32 sdcs1;		/* Mode/Extended Mode */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+	u32 pcr;		/* PLL Control */
+	u32 psr;		/* PLL Status */
+} pll_t;
+
+/* System Control Module register  */
+typedef struct scm1 {
+	u32 mpr;		/* 0x00 Master Privilege */
+	u32 rsvd1[7];
+	u32 pacra;		/* 0x20 */
+	u32 pacrb;		/* 0x24 */
+	u32 pacrc;		/* 0x28 */
+	u32 pacrd;		/* 0x2C */
+	u32 rsvd2[4];
+	u32 pacre;		/* 0x40 */
+	u32 pacrf;		/* 0x44 */
+	u32 pacrg;		/* 0x48 */
+	u32 rsvd3;
+	u32 pacri;		/* 0x50 */
+} scm1_t;
+
+typedef struct scm2_ctrl {
+	u8 res1[3];		/* 0x00 - 0x02 */
+	u8 wcr;			/* 0x03 wakeup control */
+	u16 res2;		/* 0x04 - 0x05 */
+	u16 cwcr;		/* 0x06 Core Watchdog Control */
+	u8 res3[3];		/* 0x08 - 0x0A */
+	u8 cwsr;		/* 0x0B Core Watchdog Service */
+	u8 res4[2];		/* 0x0C - 0x0D */
+	u8 scmisr;		/* 0x0F Interrupt Status */
+	u32 res5;		/* 0x20 */
+	u32 bcr;		/* 0x24 Burst Configuration */
+} scm2_t;
+
+typedef struct scm3_ctrl {
+	u32 cfadr;		/* 0x00 Core Fault Address */
+	u8 res7;		/* 0x04 */
+	u8 cfier;		/* 0x05 Core Fault Interrupt Enable */
+	u8 cfloc;		/* 0x06 Core Fault Location */
+	u8 cfatr;		/* 0x07 Core Fault Attributes */
+	u32 cfdtr;		/* 0x08 Core Fault Data */
+} scm3_t;
+
+typedef struct rtcex {
+	u32 rsvd1[3];
+	u32 gocu;
+	u32 gocl;
+} rtcex_t;
+#endif				/* __IMMAP_5227X__ */
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index 271c276..7678406 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -68,6 +68,12 @@
 #define MMAP_SSI	0xFC0BC000
 #define MMAP_PLL	0xFC0C0000
 
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/lcd.h>
+#include <asm/coldfire/ssi.h>
+
 /* System control module registers */
 typedef struct scm1_ctrl {
 	u32 mpr0;		/* 0x00 Master Privilege Register 0 */
@@ -159,61 +165,6 @@ typedef struct scm2_ctrl {
 	u32 bmt1;		/* 0x54 Bus Monitor Timeout 1 */
 } scm2_t;
 
-/* Cross-Bar Switch Module */
-typedef struct xbs_ctrl {
-	u32 prs1;		/* 0x100 Priority Register Slave 1 */
-	u32 res1[3];		/* 0x104 - 0F */
-	u32 crs1;		/* 0x110 Control Register Slave 1 */
-	u32 res2[187];		/* 0x114 - 0x3FF */
-
-	u32 prs4;		/* 0x400 Priority Register Slave 4 */
-	u32 res3[3];		/* 0x404 - 0F */
-	u32 crs4;		/* 0x410 Control Register Slave 4 */
-	u32 res4[123];		/* 0x414 - 0x5FF */
-
-	u32 prs6;		/* 0x600 Priority Register Slave 6 */
-	u32 res5[3];		/* 0x604 - 0F */
-	u32 crs6;		/* 0x610 Control Register Slave 6 */
-	u32 res6[59];		/* 0x614 - 0x6FF */
-
-	u32 prs7;		/* 0x700 Priority Register Slave 7 */
-	u32 res7[3];		/* 0x704 - 0F */
-	u32 crs7;		/* 0x710 Control Register Slave 7 */
-} xbs_t;
-
-/* Flexbus module Chip select registers */
-typedef struct fbcs_ctrl {
-	u16 csar0;		/* 0x00 Chip-Select Address Register 0 */
-	u16 res0;
-	u32 csmr0;		/* 0x04 Chip-Select Mask Register 0 */
-	u32 cscr0;		/* 0x08 Chip-Select Control Register 0 */
-
-	u16 csar1;		/* 0x0C Chip-Select Address Register 1 */
-	u16 res1;
-	u32 csmr1;		/* 0x10 Chip-Select Mask Register 1 */
-	u32 cscr1;		/* 0x14 Chip-Select Control Register 1 */
-
-	u16 csar2;		/* 0x18 Chip-Select Address Register 2 */
-	u16 res2;
-	u32 csmr2;		/* 0x1C Chip-Select Mask Register 2 */
-	u32 cscr2;		/* 0x20 Chip-Select Control Register 2 */
-
-	u16 csar3;		/* 0x24 Chip-Select Address Register 3 */
-	u16 res3;
-	u32 csmr3;		/* 0x28 Chip-Select Mask Register 3 */
-	u32 cscr3;		/* 0x2C Chip-Select Control Register 3 */
-
-	u16 csar4;		/* 0x30 Chip-Select Address Register 4 */
-	u16 res4;
-	u32 csmr4;		/* 0x34 Chip-Select Mask Register 4 */
-	u32 cscr4;		/* 0x38 Chip-Select Control Register 4 */
-
-	u16 csar5;		/* 0x3C Chip-Select Address Register 5 */
-	u16 res5;
-	u32 csmr5;		/* 0x40 Chip-Select Mask Register 5 */
-	u32 cscr5;		/* 0x44 Chip-Select Control Register 5 */
-} fbcs_t;
-
 /* FlexCan module registers */
 typedef struct can_ctrl {
 	u32 mcr;		/* 0x00 Module Configuration register */
@@ -255,64 +206,6 @@ typedef struct scm3_ctrl {
 	u32 cfdtr;		/* 0x7C Core Fault Data Register */
 } scm3_t;
 
-/* eDMA module registers */
-typedef struct edma_ctrl {
-	u32 cr;			/* 0x00 Control Register */
-	u32 es;			/* 0x04 Error Status Register */
-	u16 res1[3];		/* 0x08 - 0x0D */
-	u16 erq;		/* 0x0E Enable Request Register */
-	u16 res2[3];		/* 0x10 - 0x15 */
-	u16 eei;		/* 0x16 Enable Error Interrupt Request */
-	u8 serq;		/* 0x18 Set Enable Request */
-	u8 cerq;		/* 0x19 Clear Enable Request */
-	u8 seei;		/* 0x1A Set Enable Error Interrupt Request */
-	u8 ceei;		/* 0x1B Clear Enable Error Interrupt Request */
-	u8 cint;		/* 0x1C Clear Interrupt Enable Register */
-	u8 cerr;		/* 0x1D Clear Error Register */
-	u8 ssrt;		/* 0x1E Set START Bit Register */
-	u8 cdne;		/* 0x1F Clear DONE Status Bit Register */
-	u16 res3[3];		/* 0x20 - 0x25 */
-	u16 intr;		/* 0x26 Interrupt Request Register */
-	u16 res4[3];		/* 0x28 - 0x2D */
-	u16 err;		/* 0x2E Error Register */
-	u32 res5[52];		/* 0x30 - 0xFF */
-	u8 dchpri0;		/* 0x100 Channel 0 Priority Register */
-	u8 dchpri1;		/* 0x101 Channel 1 Priority Register */
-	u8 dchpri2;		/* 0x102 Channel 2 Priority Register */
-	u8 dchpri3;		/* 0x103 Channel 3 Priority Register */
-	u8 dchpri4;		/* 0x104 Channel 4 Priority Register */
-	u8 dchpri5;		/* 0x105 Channel 5 Priority Register */
-	u8 dchpri6;		/* 0x106 Channel 6 Priority Register */
-	u8 dchpri7;		/* 0x107 Channel 7 Priority Register */
-	u8 dchpri8;		/* 0x108 Channel 8 Priority Register */
-	u8 dchpri9;		/* 0x109 Channel 9 Priority Register */
-	u8 dchpri10;		/* 0x110 Channel 10 Priority Register */
-	u8 dchpri11;		/* 0x111 Channel 11 Priority Register */
-	u8 dchpri12;		/* 0x112 Channel 12 Priority Register */
-	u8 dchpri13;		/* 0x113 Channel 13 Priority Register */
-	u8 dchpri14;		/* 0x114 Channel 14 Priority Register */
-	u8 dchpri15;		/* 0x115 Channel 15 Priority Register */
-} edma_t;
-
-/* TCD - eDMA*/
-typedef struct tcd_ctrl {
-	u32 saddr;		/* 0x00 Source Address */
-	u16 attr;		/* 0x04 Transfer Attributes */
-	u16 soff;		/* 0x06 Signed Source Address Offset */
-	u32 nbytes;		/* 0x08 Minor Byte Count */
-	u32 slast;		/* 0x0C Last Source Address Adjustment */
-	u32 daddr;		/* 0x10 Destination address */
-	u16 citer;		/* 0x14 Current Minor Loop Link, Major Loop Count */
-	u16 doff;		/* 0x16 Signed Destination Address Offset */
-	u32 dlast_sga;		/* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
-	u16 biter;		/* 0x1C Beginning Minor Loop Link, Major Loop Count */
-	u16 csr;		/* 0x1E Control and Status */
-} tcd_st;
-
-typedef struct tcd_multiple {
-	tcd_st tcd[16];
-} tcd_t;
-
 /* Interrupt module registers */
 typedef struct int0_ctrl {
 	/* Interrupt Controller 0 */
@@ -389,20 +282,6 @@ typedef struct intgack_ctrl1 {
 	u8 Lniack[7];		/* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
 } intgack_t;
 
-/*I2C module registers */
-typedef struct i2c_ctrl {
-	u8 adr;			/* 0x00 address register */
-	u8 res1[3];		/* 0x01 - 0x03 */
-	u8 fdr;			/* 0x04 frequency divider register */
-	u8 res2[3];		/* 0x05 - 0x07 */
-	u8 cr;			/* 0x08 control register */
-	u8 res3[3];		/* 0x09 - 0x0B */
-	u8 sr;			/* 0x0C status register */
-	u8 res4[3];		/* 0x0D - 0x0F */
-	u8 dr;			/* 0x10 data register */
-	u8 res5[3];		/* 0x11 - 0x13 */
-} i2c_t;
-
 /* QSPI module registers */
 typedef struct qspi_ctrl {
 	u16 qmr;		/* Mode register */
@@ -499,91 +378,133 @@ typedef struct rcm {
 /* GPIO port registers */
 typedef struct gpio_ctrl {
 	/* Port Output Data Registers */
+#ifdef CONFIG_M5329
 	u8 podr_fech;		/* 0x00 */
 	u8 podr_fecl;		/* 0x01 */
+#else
+	u16 res00;		/* 0x00 - 0x01 */
+#endif
 	u8 podr_ssi;		/* 0x02 */
 	u8 podr_busctl;		/* 0x03 */
 	u8 podr_be;		/* 0x04 */
 	u8 podr_cs;		/* 0x05 */
 	u8 podr_pwm;		/* 0x06 */
 	u8 podr_feci2c;		/* 0x07 */
-	u8 res1;		/* 0x08 */
+	u8 res08;		/* 0x08 */
 	u8 podr_uart;		/* 0x09 */
 	u8 podr_qspi;		/* 0x0A */
 	u8 podr_timer;		/* 0x0B */
-	u8 res2;		/* 0x0C */
+#ifdef CONFIG_M5329
+	u8 res0C;		/* 0x0C */
 	u8 podr_lcddatah;	/* 0x0D */
 	u8 podr_lcddatam;	/* 0x0E */
 	u8 podr_lcddatal;	/* 0x0F */
 	u8 podr_lcdctlh;	/* 0x10 */
 	u8 podr_lcdctll;	/* 0x11 */
+#else
+	u16 res0C;		/* 0x0C - 0x0D */
+	u8 podr_fech;		/* 0x0E */
+	u8 podr_fecl;		/* 0x0F */
+	u16 res10[3];		/* 0x10 - 0x15 */
+#endif
 
 	/* Port Data Direction Registers */
-	u16 res3;		/* 0x12 - 0x13 */
+#ifdef CONFIG_M5329
+	u16 res12;		/* 0x12 - 0x13 */
 	u8 pddr_fech;		/* 0x14 */
 	u8 pddr_fecl;		/* 0x15 */
+#endif
 	u8 pddr_ssi;		/* 0x16 */
 	u8 pddr_busctl;		/* 0x17 */
 	u8 pddr_be;		/* 0x18 */
 	u8 pddr_cs;		/* 0x19 */
 	u8 pddr_pwm;		/* 0x1A */
 	u8 pddr_feci2c;		/* 0x1B */
-	u8 res4;		/* 0x1C */
+	u8 res1C;		/* 0x1C */
 	u8 pddr_uart;		/* 0x1D */
 	u8 pddr_qspi;		/* 0x1E */
 	u8 pddr_timer;		/* 0x1F */
-	u8 res5;		/* 0x20 */
+#ifdef CONFIG_M5329
+	u8 res20;		/* 0x20 */
 	u8 pddr_lcddatah;	/* 0x21 */
 	u8 pddr_lcddatam;	/* 0x22 */
 	u8 pddr_lcddatal;	/* 0x23 */
 	u8 pddr_lcdctlh;	/* 0x24 */
 	u8 pddr_lcdctll;	/* 0x25 */
-	u16 res6;		/* 0x26 - 0x27 */
+	u16 res26;		/* 0x26 - 0x27 */
+#else
+	u16 res20;		/* 0x20 - 0x21 */
+	u8 pddr_fech;		/* 0x22 */
+	u8 pddr_fecl;		/* 0x23 */
+	u16 res24[3];		/* 0x24 - 0x29 */
+#endif
 
 	/* Port Data Direction Registers */
+#ifdef CONFIG_M5329
 	u8 ppd_fech;		/* 0x28 */
 	u8 ppd_fecl;		/* 0x29 */
+#endif
 	u8 ppd_ssi;		/* 0x2A */
 	u8 ppd_busctl;		/* 0x2B */
 	u8 ppd_be;		/* 0x2C */
 	u8 ppd_cs;		/* 0x2D */
 	u8 ppd_pwm;		/* 0x2E */
 	u8 ppd_feci2c;		/* 0x2F */
-	u8 res7;		/* 0x30 */
+	u8 res30;		/* 0x30 */
 	u8 ppd_uart;		/* 0x31 */
 	u8 ppd_qspi;		/* 0x32 */
 	u8 ppd_timer;		/* 0x33 */
-	u8 res8;		/* 0x34 */
+#ifdef CONFIG_M5329
+	u8 res34;		/* 0x34 */
 	u8 ppd_lcddatah;	/* 0x35 */
 	u8 ppd_lcddatam;	/* 0x36 */
 	u8 ppd_lcddatal;	/* 0x37 */
 	u8 ppd_lcdctlh;		/* 0x38 */
 	u8 ppd_lcdctll;		/* 0x39 */
-	u16 res9;		/* 0x3A - 0x3B */
+	u16 res3A;		/* 0x3A - 0x3B */
+#else
+	u16 res34;		/* 0x34 - 0x35 */
+	u8 ppd_fech;		/* 0x36 */
+	u8 ppd_fecl;		/* 0x37 */
+	u16 res38[3];		/* 0x38 - 0x3D */
+#endif
 
 	/* Port Clear Output Data Registers */
-	u8 pclrr_fech;		/* 0x3C */
-	u8 pclrr_fecl;		/* 0x3D */
+#ifdef CONFIG_M5329
+	u8 res3C;		/* 0x3C */
+	u8 pclrr_fech;		/* 0x3D */
+	u8 pclrr_fecl;		/* 0x3E */
+#else
 	u8 pclrr_ssi;		/* 0x3E */
+#endif
 	u8 pclrr_busctl;	/* 0x3F */
 	u8 pclrr_be;		/* 0x40 */
 	u8 pclrr_cs;		/* 0x41 */
 	u8 pclrr_pwm;		/* 0x42 */
 	u8 pclrr_feci2c;	/* 0x43 */
-	u8 res10;		/* 0x44 */
+	u8 res44;		/* 0x44 */
 	u8 pclrr_uart;		/* 0x45 */
 	u8 pclrr_qspi;		/* 0x46 */
 	u8 pclrr_timer;		/* 0x47 */
-	u8 res11;		/* 0x48 */
-	u8 pclrr_lcddatah;	/* 0x49 */
-	u8 pclrr_lcddatam;	/* 0x4A */
-	u8 pclrr_lcddatal;	/* 0x4B */
+#ifdef CONFIG_M5329
+	u8 pclrr_lcddatah;	/* 0x48 */
+	u8 pclrr_lcddatam;	/* 0x49 */
+	u8 pclrr_lcddatal;	/* 0x4A */
+	u8 pclrr_ssi;		/* 0x4B */
 	u8 pclrr_lcdctlh;	/* 0x4C */
 	u8 pclrr_lcdctll;	/* 0x4D */
-	u16 res12;		/* 0x4E - 0x4F */
+	u16 res4E;		/* 0x4E - 0x4F */
+#else
+	u16 res48;		/* 0x48 - 0x49 */
+	u8 pclrr_fech;		/* 0x4A */
+	u8 pclrr_fecl;		/* 0x4B */
+	u8 res4C[5];		/* 0x4C - 0x50 */
+#endif
 
 	/* Pin Assignment Registers */
+#ifdef CONFIG_M5329
 	u8 par_fec;		/* 0x50 */
+#endif
 	u8 par_pwm;		/* 0x51 */
 	u8 par_busctl;		/* 0x52 */
 	u8 par_feci2c;		/* 0x53 */
@@ -593,15 +514,20 @@ typedef struct gpio_ctrl {
 	u16 par_uart;		/* 0x58 */
 	u16 par_qspi;		/* 0x5A */
 	u8 par_timer;		/* 0x5C */
+#ifdef CONFIG_M5329
 	u8 par_lcddata;		/* 0x5D */
 	u16 par_lcdctl;		/* 0x5E */
+#else
+	u8 par_fec;		/* 0x5D */
+	u16 res5E;		/* 0x5E - 0x5F */
+#endif
 	u16 par_irq;		/* 0x60 */
-	u16 res16;		/* 0x62 - 0x63 */
+	u16 res62;		/* 0x62 - 0x63 */
 
 	/* Mode Select Control Registers */
 	u8 mscr_flexbus;	/* 0x64 */
 	u8 mscr_sdram;		/* 0x65 */
-	u16 res17;		/* 0x66 - 0x67 */
+	u16 res66;		/* 0x66 - 0x67 */
 
 	/* Drive Strength Control Registers */
 	u8 dscr_i2c;		/* 0x68 */
@@ -611,49 +537,16 @@ typedef struct gpio_ctrl {
 	u8 dscr_qspi;		/* 0x6C */
 	u8 dscr_timer;		/* 0x6D */
 	u8 dscr_ssi;		/* 0x6E */
+#ifdef CONFIG_M5329
 	u8 dscr_lcd;		/* 0x6F */
+#else
+	u8 res6F;		/* 0x6F */
+#endif
 	u8 dscr_debug;		/* 0x70 */
 	u8 dscr_clkrst;		/* 0x71 */
 	u8 dscr_irq;		/* 0x72 */
 } gpio_t;
 
-/* LCD module registers */
-typedef struct lcd_ctrl {
-	u32 ssar;		/* 0x00 Screen Start Address Register */
-	u32 sr;			/* 0x04 LCD Size Register */
-	u32 vpw;		/* 0x08 Virtual Page Width Register */
-	u32 cpr;		/* 0x0C Cursor Position Register */
-	u32 cwhb;		/* 0x10 Cursor Width Height and Blink Register */
-	u32 ccmr;		/* 0x14 Color Cursor Mapping Register */
-	u32 pcr;		/* 0x18 Panel Configuration Register */
-	u32 hcr;		/* 0x1C Horizontal Configuration Register */
-	u32 vcr;		/* 0x20 Vertical Configuration Register */
-	u32 por;		/* 0x24 Panning Offset Register */
-	u32 scr;		/* 0x28 Sharp Configuration Register */
-	u32 pccr;		/* 0x2C PWM Contrast Control Register */
-	u32 dcr;		/* 0x30 DMA Control Register */
-	u32 rmcr;		/* 0x34 Refresh Mode Control Register */
-	u32 icr;		/* 0x38 Refresh Mode Control Register */
-	u32 ier;		/* 0x3C Interrupt Enable Register */
-	u32 isr;		/* 0x40 Interrupt Status Register */
-	u32 res[4];
-	u32 gwsar;		/* 0x50 Graphic Window Start Address Register */
-	u32 gwsr;		/* 0x54 Graphic Window Size Register */
-	u32 gwvpw;		/* 0x58 Graphic Window Virtual Page Width Register */
-	u32 gwpor;		/* 0x5C Graphic Window Panning Offset Register */
-	u32 gwpr;		/* 0x60 Graphic Window Position Register */
-	u32 gwcr;		/* 0x64 Graphic Window Control Register */
-	u32 gwdcr;		/* 0x68 Graphic Window DMA Control Register */
-} lcd_t;
-
-typedef struct lcdbg_ctrl {
-	u32 bglut[255];
-} lcdbg_t;
-
-typedef struct lcdgw_ctrl {
-	u32 gwlut[255];
-} lcdgw_t;
-
 /* USB OTG module registers */
 typedef struct usb_otg {
 	u32 id;			/* 0x000 Identification Register */
@@ -758,29 +651,6 @@ typedef struct sdram_ctrl {
 	u32 cs1;		/* 0x114 Chip Select 1 Configuration */
 } sdram_t;
 
-/* Synchronous serial interface */
-typedef struct ssi_ctrl {
-	u32 tx0;		/* 0x00 Transmit Data Register 0 */
-	u32 tx1;		/* 0x04 Transmit Data Register 1 */
-	u32 rx0;		/* 0x08 Receive Data Register 0 */
-	u32 rx1;		/* 0x0C Receive Data Register 1 */
-	u32 cr;			/* 0x10 Control Register */
-	u32 isr;		/* 0x14 Interrupt Status Register */
-	u32 ier;		/* 0x18 Interrupt Enable Register */
-	u32 tcr;		/* 0x1C Transmit Configuration Register */
-	u32 rcr;		/* 0x20 Receive Configuration Register */
-	u32 ccr;		/* 0x24 Clock Control Register */
-	u32 res1;		/* 0x28 */
-	u32 fcsr;		/* 0x2C FIFO Control/Status Register */
-	u32 res2[2];		/* 0x30 - 0x37 */
-	u32 acr;		/* 0x38 AC97 Control Register */
-	u32 acadd;		/* 0x3C AC97 Command Address Register */
-	u32 acdat;		/* 0x40 AC97 Command Data Register */
-	u32 atag;		/* 0x44 AC97 Tag Register */
-	u32 tmask;		/* 0x48 Transmit Time Slot Mask Register */
-	u32 rmask;		/* 0x4C Receive Time Slot Mask Register */
-} ssi_t;
-
 /* Clock Module registers */
 typedef struct pll_ctrl {
 	u8 podr;		/* 0x00 Output Divider Register */
diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h
index d091d7b..ef8930e 100644
--- a/include/asm-m68k/immap_5445x.h
+++ b/include/asm-m68k/immap_5445x.h
@@ -33,6 +33,7 @@
 #define MMAP_FEC0	0xFC030000
 #define MMAP_FEC1	0xFC034000
 #define MMAP_RTC	0xFC03C000
+#define MMAP_SCM2	0xFC040000
 #define MMAP_EDMA	0xFC044000
 #define MMAP_INTC0	0xFC048000
 #define MMAP_INTC1	0xFC04C000
@@ -63,11 +64,18 @@
 #define MMAP_SSI	0xFC0BC000
 #define MMAP_PLL	0xFC0C4000
 #define MMAP_ATA	0x90000000
-
-/*********************************************************************
-* ATA
-*********************************************************************/
-
+#define MMAP_USBHW	0xFC0B0000
+#define MMAP_USBCAPS	0xFC0B0100
+#define MMAP_USBEHCI	0xFC0B0140
+#define MMAP_USBOTG	0xFC0B01A0
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/ssi.h>
+
+/* ATA */
 typedef struct atac {
 	/* PIO */
 	u8 toff;		/* 0x00 */
@@ -117,379 +125,7 @@ typedef struct atac {
 	u8 rsvd6[106];
 } atac_t;
 
-/*********************************************************************
-* Cross-bar switch (XBS)
-*********************************************************************/
-
-typedef struct xbs {
-	u8 resv0[0x100];
-	u32 prs1;		/* XBS Priority Register */
-	u8 resv1[0xC];
-	u32 crs1;		/* XBS Control Register */
-	u8 resv2[0xEC];
-	u32 prs2;		/* XBS Priority Register */
-	u8 resv3[0xC];
-	u32 crs2;		/* XBS Control Register */
-	u8 resv4[0xEC];
-	u32 prs3;		/* XBS Priority Register */
-	u8 resv5[0xC];
-	u32 crs3;		/* XBS Control Register */
-	u8 resv6[0xEC];
-	u32 prs4;		/* XBS Priority Register */
-	u8 resv7[0xC];
-	u32 crs4;		/* XBS Control Register */
-	u8 resv8[0xEC];
-	u32 prs5;		/* XBS Priority Register */
-	u8 resv9[0xC];
-	u32 crs5;		/* XBS Control Register */
-	u8 resv10[0xEC];
-	u32 prs6;		/* XBS Priority Register */
-	u8 resv11[0xC];
-	u32 crs6;		/* XBS Control Register */
-	u8 resv12[0xEC];
-	u32 prs7;		/* XBS Priority Register */
-	u8 resv13[0xC];
-	u32 crs7;		/* XBS Control Register */
-} xbs_t;
-
-/*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-
-typedef struct fbcs {
-	u32 csar0;		/* Chip-select Address Register */
-	u32 csmr0;		/* Chip-select Mask Register */
-	u32 cscr0;		/* Chip-select Control Register */
-	u32 csar1;		/* Chip-select Address Register */
-	u32 csmr1;		/* Chip-select Mask Register */
-	u32 cscr1;		/* Chip-select Control Register */
-	u32 csar2;		/* Chip-select Address Register */
-	u32 csmr2;		/* Chip-select Mask Register */
-	u32 cscr2;		/* Chip-select Control Register */
-	u32 csar3;		/* Chip-select Address Register */
-	u32 csmr3;		/* Chip-select Mask Register */
-	u32 cscr3;		/* Chip-select Control Register */
-} fbcs_t;
-
-/*********************************************************************
-* Enhanced DMA (EDMA)
-*********************************************************************/
-
-typedef struct edma {
-	u32 cr;
-	u32 es;
-	u8 resv0[0x6];
-	u16 erq;
-	u8 resv1[0x6];
-	u16 eei;
-	u8 serq;
-	u8 cerq;
-	u8 seei;
-	u8 ceei;
-	u8 cint;
-	u8 cerr;
-	u8 ssrt;
-	u8 cdne;
-	u8 resv2[0x6];
-	u16 intr;
-	u8 resv3[0x6];
-	u16 err;
-	u8 resv4[0xD0];
-	u8 dchpri0;
-	u8 dchpri1;
-	u8 dchpri2;
-	u8 dchpri3;
-	u8 dchpri4;
-	u8 dchpri5;
-	u8 dchpri6;
-	u8 dchpri7;
-	u8 dchpri8;
-	u8 dchpri9;
-	u8 dchpri10;
-	u8 dchpri11;
-	u8 dchpri12;
-	u8 dchpri13;
-	u8 dchpri14;
-	u8 dchpri15;
-	u8 resv5[0xEF0];
-	u32 tcd0_saddr;
-	u16 tcd0_attr;
-	u16 tcd0_soff;
-	u32 tcd0_nbytes;
-	u32 tcd0_slast;
-	u32 tcd0_daddr;
-	union {
-		u16 tcd0_citer_elink;
-		u16 tcd0_citer;
-	};
-	u16 tcd0_doff;
-	u32 tcd0_dlast_sga;
-	union {
-		u16 tcd0_biter_elink;
-		u16 tcd0_biter;
-	};
-	u16 tcd0_csr;
-	u32 tcd1_saddr;
-	u16 tcd1_attr;
-	u16 tcd1_soff;
-	u32 tcd1_nbytes;
-	u32 tcd1_slast;
-	u32 tcd1_daddr;
-	union {
-		u16 tcd1_citer_elink;
-		u16 tcd1_citer;
-	};
-	u16 tcd1_doff;
-	u32 tcd1_dlast_sga;
-	union {
-		u16 tcd1_biter;
-		u16 tcd1_biter_elink;
-	};
-	u16 tcd1_csr;
-	u32 tcd2_saddr;
-	u16 tcd2_attr;
-	u16 tcd2_soff;
-	u32 tcd2_nbytes;
-	u32 tcd2_slast;
-	u32 tcd2_daddr;
-	union {
-		u16 tcd2_citer;
-		u16 tcd2_citer_elink;
-	};
-	u16 tcd2_doff;
-	u32 tcd2_dlast_sga;
-	union {
-		u16 tcd2_biter_elink;
-		u16 tcd2_biter;
-	};
-	u16 tcd2_csr;
-	u32 tcd3_saddr;
-	u16 tcd3_attr;
-	u16 tcd3_soff;
-	u32 tcd3_nbytes;
-	u32 tcd3_slast;
-	u32 tcd3_daddr;
-	union {
-		u16 tcd3_citer;
-		u16 tcd3_citer_elink;
-	};
-	u16 tcd3_doff;
-	u32 tcd3_dlast_sga;
-	union {
-		u16 tcd3_biter_elink;
-		u16 tcd3_biter;
-	};
-	u16 tcd3_csr;
-	u32 tcd4_saddr;
-	u16 tcd4_attr;
-	u16 tcd4_soff;
-	u32 tcd4_nbytes;
-	u32 tcd4_slast;
-	u32 tcd4_daddr;
-	union {
-		u16 tcd4_citer;
-		u16 tcd4_citer_elink;
-	};
-	u16 tcd4_doff;
-	u32 tcd4_dlast_sga;
-	union {
-		u16 tcd4_biter;
-		u16 tcd4_biter_elink;
-	};
-	u16 tcd4_csr;
-	u32 tcd5_saddr;
-	u16 tcd5_attr;
-	u16 tcd5_soff;
-	u32 tcd5_nbytes;
-	u32 tcd5_slast;
-	u32 tcd5_daddr;
-	union {
-		u16 tcd5_citer;
-		u16 tcd5_citer_elink;
-	};
-	u16 tcd5_doff;
-	u32 tcd5_dlast_sga;
-	union {
-		u16 tcd5_biter_elink;
-		u16 tcd5_biter;
-	};
-	u16 tcd5_csr;
-	u32 tcd6_saddr;
-	u16 tcd6_attr;
-	u16 tcd6_soff;
-	u32 tcd6_nbytes;
-	u32 tcd6_slast;
-	u32 tcd6_daddr;
-	union {
-		u16 tcd6_citer;
-		u16 tcd6_citer_elink;
-	};
-	u16 tcd6_doff;
-	u32 tcd6_dlast_sga;
-	union {
-		u16 tcd6_biter_elink;
-		u16 tcd6_biter;
-	};
-	u16 tcd6_csr;
-	u32 tcd7_saddr;
-	u16 tcd7_attr;
-	u16 tcd7_soff;
-	u32 tcd7_nbytes;
-	u32 tcd7_slast;
-	u32 tcd7_daddr;
-	union {
-		u16 tcd7_citer;
-		u16 tcd7_citer_elink;
-	};
-	u16 tcd7_doff;
-	u32 tcd7_dlast_sga;
-	union {
-		u16 tcd7_biter_elink;
-		u16 tcd7_biter;
-	};
-	u16 tcd7_csr;
-	u32 tcd8_saddr;
-	u16 tcd8_attr;
-	u16 tcd8_soff;
-	u32 tcd8_nbytes;
-	u32 tcd8_slast;
-	u32 tcd8_daddr;
-	union {
-		u16 tcd8_citer;
-		u16 tcd8_citer_elink;
-	};
-	u16 tcd8_doff;
-	u32 tcd8_dlast_sga;
-	union {
-		u16 tcd8_biter_elink;
-		u16 tcd8_biter;
-	};
-	u16 tcd8_csr;
-	u32 tcd9_saddr;
-	u16 tcd9_attr;
-	u16 tcd9_soff;
-	u32 tcd9_nbytes;
-	u32 tcd9_slast;
-	u32 tcd9_daddr;
-	union {
-		u16 tcd9_citer_elink;
-		u16 tcd9_citer;
-	};
-	u16 tcd9_doff;
-	u32 tcd9_dlast_sga;
-	union {
-		u16 tcd9_biter_elink;
-		u16 tcd9_biter;
-	};
-	u16 tcd9_csr;
-	u32 tcd10_saddr;
-	u16 tcd10_attr;
-	u16 tcd10_soff;
-	u32 tcd10_nbytes;
-	u32 tcd10_slast;
-	u32 tcd10_daddr;
-	union {
-		u16 tcd10_citer_elink;
-		u16 tcd10_citer;
-	};
-	u16 tcd10_doff;
-	u32 tcd10_dlast_sga;
-	union {
-		u16 tcd10_biter;
-		u16 tcd10_biter_elink;
-	};
-	u16 tcd10_csr;
-	u32 tcd11_saddr;
-	u16 tcd11_attr;
-	u16 tcd11_soff;
-	u32 tcd11_nbytes;
-	u32 tcd11_slast;
-	u32 tcd11_daddr;
-	union {
-		u16 tcd11_citer;
-		u16 tcd11_citer_elink;
-	};
-	u16 tcd11_doff;
-	u32 tcd11_dlast_sga;
-	union {
-		u16 tcd11_biter;
-		u16 tcd11_biter_elink;
-	};
-	u16 tcd11_csr;
-	u32 tcd12_saddr;
-	u16 tcd12_attr;
-	u16 tcd12_soff;
-	u32 tcd12_nbytes;
-	u32 tcd12_slast;
-	u32 tcd12_daddr;
-	union {
-		u16 tcd12_citer;
-		u16 tcd12_citer_elink;
-	};
-	u16 tcd12_doff;
-	u32 tcd12_dlast_sga;
-	union {
-		u16 tcd12_biter;
-		u16 tcd12_biter_elink;
-	};
-	u16 tcd12_csr;
-	u32 tcd13_saddr;
-	u16 tcd13_attr;
-	u16 tcd13_soff;
-	u32 tcd13_nbytes;
-	u32 tcd13_slast;
-	u32 tcd13_daddr;
-	union {
-		u16 tcd13_citer_elink;
-		u16 tcd13_citer;
-	};
-	u16 tcd13_doff;
-	u32 tcd13_dlast_sga;
-	union {
-		u16 tcd13_biter_elink;
-		u16 tcd13_biter;
-	};
-	u16 tcd13_csr;
-	u32 tcd14_saddr;
-	u16 tcd14_attr;
-	u16 tcd14_soff;
-	u32 tcd14_nbytes;
-	u32 tcd14_slast;
-	u32 tcd14_daddr;
-	union {
-		u16 tcd14_citer;
-		u16 tcd14_citer_elink;
-	};
-	u16 tcd14_doff;
-	u32 tcd14_dlast_sga;
-	union {
-		u16 tcd14_biter_elink;
-		u16 tcd14_biter;
-	};
-	u16 tcd14_csr;
-	u32 tcd15_saddr;
-	u16 tcd15_attr;
-	u16 tcd15_soff;
-	u32 tcd15_nbytes;
-	u32 tcd15_slast;
-	u32 tcd15_daddr;
-	union {
-		u16 tcd15_citer_elink;
-		u16 tcd15_citer;
-	};
-	u16 tcd15_doff;
-	u32 tcd15_dlast_sga;
-	union {
-		u16 tcd15_biter;
-		u16 tcd15_biter_elink;
-	};
-	u16 tcd15_csr;
-} edma_t;
-
-/*********************************************************************
-* Interrupt Controller (INTC)
-*********************************************************************/
-
+/* Interrupt Controller (INTC) */
 typedef struct int0_ctrl {
 	u32 iprh0;		/* 0x00 Pending Register High */
 	u32 iprl0;		/* 0x04 Pending Register Low */
@@ -558,10 +194,7 @@ typedef struct int1_ctrl {
 	u8 resc[3];		/* 0xFD - 0xFF */
 } int1_t;
 
-/*********************************************************************
-* Global Interrupt Acknowledge (IACK)
-*********************************************************************/
-
+/* Global Interrupt Acknowledge (IACK) */
 typedef struct iack {
 	u8 resv0[0xE0];
 	u8 gswiack;
@@ -581,41 +214,7 @@ typedef struct iack {
 	u8 gl7iack;
 } iack_t;
 
-/*********************************************************************
-* DMA Serial Peripheral Interface (DSPI)
-*********************************************************************/
-
-typedef struct dspi {
-	u32 dmcr;
-	u8 resv0[0x4];
-	u32 dtcr;
-	u32 dctar0;
-	u32 dctar1;
-	u32 dctar2;
-	u32 dctar3;
-	u32 dctar4;
-	u32 dctar5;
-	u32 dctar6;
-	u32 dctar7;
-	u32 dsr;
-	u32 dirsr;
-	u32 dtfr;
-	u32 drfr;
-	u32 dtfdr0;
-	u32 dtfdr1;
-	u32 dtfdr2;
-	u32 dtfdr3;
-	u8 resv1[0x30];
-	u32 drfdr0;
-	u32 drfdr1;
-	u32 drfdr2;
-	u32 drfdr3;
-} dspi_t;
-
-/*********************************************************************
-* Edge Port Module (EPORT)
-*********************************************************************/
-
+/* Edge Port Module (EPORT) */
 typedef struct eport {
 	u16 eppar;
 	u8 epddr;
@@ -625,10 +224,7 @@ typedef struct eport {
 	u8 epfr;
 } eport_t;
 
-/*********************************************************************
-* Watchdog Timer Modules (WTM)
-*********************************************************************/
-
+/* Watchdog Timer Modules (WTM) */
 typedef struct wtm {
 	u16 wcr;
 	u16 wmr;
@@ -636,10 +232,7 @@ typedef struct wtm {
 	u16 wsr;
 } wtm_t;
 
-/*********************************************************************
-* Serial Boot Facility (SBF)
-*********************************************************************/
-
+/* Serial Boot Facility (SBF) */
 typedef struct sbf {
 	u8 resv0[0x18];
 	u16 sbfsr;		/* Serial Boot Facility Status Register */
@@ -647,19 +240,13 @@ typedef struct sbf {
 	u16 sbfcr;		/* Serial Boot Facility Control Register */
 } sbf_t;
 
-/*********************************************************************
-* Reset Controller Module (RCM)
-*********************************************************************/
-
+/* Reset Controller Module (RCM) */
 typedef struct rcm {
 	u8 rcr;
 	u8 rsr;
 } rcm_t;
 
-/*********************************************************************
-* Chip Configuration Module (CCM)
-*********************************************************************/
-
+/* Chip Configuration Module (CCM) */
 typedef struct ccm {
 	u8 ccm_resv0[0x4];
 	u16 ccr;		/* Chip Configuration Register (256 TEPBGA, Read-only) */
@@ -672,10 +259,7 @@ typedef struct ccm {
 	u16 uocsr;		/* USB On-the-Go Controller Status Register */
 } ccm_t;
 
-/*********************************************************************
-* General Purpose I/O Module (GPIO)
-*********************************************************************/
-
+/* General Purpose I/O Module (GPIO) */
 typedef struct gpio {
 	u8 podr_fec0h;		/* FEC0 High Port Output Data Register */
 	u8 podr_fec0l;		/* FEC0 Low Port Output Data Register */
@@ -803,10 +387,7 @@ typedef struct gpio {
 	u8 dscr_ata;		/* ATA Drive Strength Control Register */
 } gpio_t;
 
-/*********************************************************************
-* Random Number Generator (RNG)
-*********************************************************************/
-
+/* Random Number Generator (RNG) */
 typedef struct rng {
 	u32 rngcr;
 	u32 rngsr;
@@ -814,10 +395,7 @@ typedef struct rng {
 	u32 rngout;
 } rng_t;
 
-/*********************************************************************
-* SDRAM Controller (SDRAMC)
-*********************************************************************/
-
+/* SDRAM Controller (SDRAMC) */
 typedef struct sdramc {
 	u32 sdmr;		/* SDRAM Mode/Extended Mode Register */
 	u32 sdcr;		/* SDRAM Control Register */
@@ -828,36 +406,7 @@ typedef struct sdramc {
 	u32 sdcs1;		/* SDRAM Mode/Extended Mode Register */
 } sdramc_t;
 
-/*********************************************************************
-* Synchronous Serial Interface (SSI)
-*********************************************************************/
-
-typedef struct ssi {
-	u32 tx0;
-	u32 tx1;
-	u32 rx0;
-	u32 rx1;
-	u32 cr;
-	u32 isr;
-	u32 ier;
-	u32 tcr;
-	u32 rcr;
-	u32 ccr;
-	u8 resv0[0x4];
-	u32 fcsr;
-	u8 resv1[0x8];
-	u32 acr;
-	u32 acadd;
-	u32 acdat;
-	u32 atag;
-	u32 tmask;
-	u32 rmask;
-} ssi_t;
-
-/*********************************************************************
-* Phase Locked Loop (PLL)
-*********************************************************************/
-
+/* Phase Locked Loop (PLL) */
 typedef struct pll {
 	u32 pcr;		/* PLL Control Register */
 	u32 psr;		/* PLL Status Register */
@@ -927,7 +476,27 @@ typedef struct scm1 {
 	u32 pacrf;		/* 0x44 Peripheral Access Control Register F */
 	u32 pacrg;		/* 0x48 Peripheral Access Control Register G */
 } scm1_t;
-/********************************************************************/
+
+typedef struct scm2 {
+	u8 rsvd1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 */
+	u16 rsvd2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 */
+	u8 rsvd3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B */
+	u8 rsvd4[3];		/* 0x1C - 0x1E */
+	u8 scmisr;		/* 0x1F */
+	u32 rsvd5;		/* 0x20 - 0x23 */
+	u8 bcr;			/* 0x24 */
+	u8 rsvd6[74];		/* 0x25 - 0x6F */
+	u32 cfadr;		/* 0x70 */
+	u8 rsvd7;		/* 0x74 */
+	u8 cfier;		/* 0x75 */
+	u8 cfloc;		/* 0x76 */
+	u8 cfatr;		/* 0x77 */
+	u32 rsvd8;		/* 0x78 - 0x7B */
+	u32 cfdtr;		/* 0x7C */
+} scm2_t;
 
 typedef struct rtcex {
 	u32 rsvd1[3];
diff --git a/include/asm-m68k/immap_547x_8x.h b/include/asm-m68k/immap_547x_8x.h
new file mode 100644
index 0000000..54ef40f
--- /dev/null
+++ b/include/asm-m68k/immap_547x_8x.h
@@ -0,0 +1,297 @@
+/*
+ * MCF547x_8x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_547x_8x__
+#define __IMMAP_547x_8x__
+
+#define MMAP_SIU	(CFG_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CFG_MBAR + 0x00000100)
+#define MMAP_XARB	(CFG_MBAR + 0x00000240)
+#define MMAP_FBCS	(CFG_MBAR + 0x00000500)
+#define MMAP_INTC0	(CFG_MBAR + 0x00000700)
+#define MMAP_GPTMR	(CFG_MBAR + 0x00000800)
+#define MMAP_SLT0	(CFG_MBAR + 0x00000900)
+#define MMAP_SLT1	(CFG_MBAR + 0x00000910)
+#define MMAP_GPIO	(CFG_MBAR + 0x00000A00)
+#define MMAP_PCI	(CFG_MBAR + 0x00000B00)
+#define MMAP_PCIARB	(CFG_MBAR + 0x00000C00)
+#define MMAP_EXTDMA	(CFG_MBAR + 0x00000D00)
+#define MMAP_EPORT	(CFG_MBAR + 0x00000F00)
+#define MMAP_CTM	(CFG_MBAR + 0x00007F00)
+#define MMAP_MCDMA	(CFG_MBAR + 0x00008000)
+#define MMAP_SCPCI	(CFG_MBAR + 0x00008400)
+#define MMAP_UART0	(CFG_MBAR + 0x00008600)
+#define MMAP_UART1	(CFG_MBAR + 0x00008700)
+#define MMAP_UART2	(CFG_MBAR + 0x00008800)
+#define MMAP_UART3	(CFG_MBAR + 0x00008900)
+#define MMAP_DSPI	(CFG_MBAR + 0x00008A00)
+#define MMAP_I2C	(CFG_MBAR + 0x00008F00)
+#define MMAP_FEC0	(CFG_MBAR + 0x00009000)
+#define MMAP_FEC1	(CFG_MBAR + 0x00009800)
+#define MMAP_CAN0	(CFG_MBAR + 0x0000A000)
+#define MMAP_CAN1	(CFG_MBAR + 0x0000A800)
+#define MMAP_USBD	(CFG_MBAR + 0x0000B000)
+#define MMAP_SRAM	(CFG_MBAR + 0x00010000)
+#define MMAP_SRAMCFG	(CFG_MBAR + 0x0001FF00)
+#define MMAP_SEC	(CFG_MBAR + 0x00020000)
+
+#include <asm/coldfire/flexbus.h>
+
+typedef struct siu {
+	u32 mbar;		/* 0x00 */
+	u32 drv;		/* 0x04 */
+	u32 rsvd1[2];		/* 0x08 - 0x1F */
+	u32 sbcr;		/* 0x10 */
+	u32 rsvd2[3];		/* 0x14 - 0x1F */
+	u32 cs0cfg;		/* 0x20 */
+	u32 cs1cfg;		/* 0x24 */
+	u32 cs2cfg;		/* 0x28 */
+	u32 cs3cfg;		/* 0x2C */
+	u32 rsvd3[2];		/* 0x30 - 0x37 */
+	u32 secsacr;		/* 0x38 */
+	u32 rsvd4[2];		/* 0x3C - 0x43 */
+	u32 rsr;		/* 0x44 */
+	u32 rsvd5[2];		/* 0x48 - 0x4F */
+	u32 jtagid;		/* 0x50 */
+} siu_t;
+
+typedef struct sdram {
+	u32 mode;		/* 0x00 */
+	u32 ctrl;		/* 0x04 */
+	u32 cfg1;		/* 0x08 */
+	u32 cfg2;		/* 0x0c */
+} sdram_t;
+
+typedef struct xlb_arb {
+	u32 cfg;		/* 0x240 */
+	u32 ver;		/* 0x244 */
+	u32 sr;			/* 0x248 */
+	u32 imr;		/* 0x24c */
+	u32 adrcap;		/* 0x250 */
+	u32 sigcap;		/* 0x254 */
+	u32 adrto;		/* 0x258 */
+	u32 datto;		/* 0x25c */
+	u32 busto;		/* 0x260 */
+	u32 prien;		/* 0x264 */
+	u32 pri;		/* 0x268 */
+} xlbarb_t;
+
+typedef struct int0_ctrl {
+	u32 iprh0;		/* 0x00 */
+	u32 iprl0;		/* 0x04 */
+	u32 imrh0;		/* 0x08 */
+	u32 imrl0;		/* 0x0C */
+	u32 frch0;		/* 0x10 */
+	u32 frcl0;		/* 0x14 */
+	u8 irlr;		/* 0x18 */
+	u8 iacklpr;		/* 0x19 */
+	u16 res1;		/* 0x1A - 0x1B */
+	u32 res2[9];		/* 0x1C - 0x3F */
+	u8 icr0[64];		/* 0x40 - 0x7F */
+	u32 res3[24];		/* 0x80 - 0xDF */
+	u8 swiack0;		/* 0xE0 */
+	u8 res4[3];		/* 0xE1 - 0xE3 */
+	u8 Lniack0_1;		/* 0xE4 */
+	u8 res5[3];		/* 0xE5 - 0xE7 */
+	u8 Lniack0_2;		/* 0xE8 */
+	u8 res6[3];		/* 0xE9 - 0xEB */
+	u8 Lniack0_3;		/* 0xEC */
+	u8 res7[3];		/* 0xED - 0xEF */
+	u8 Lniack0_4;		/* 0xF0 */
+	u8 res8[3];		/* 0xF1 - 0xF3 */
+	u8 Lniack0_5;		/* 0xF4 */
+	u8 res9[3];		/* 0xF5 - 0xF7 */
+	u8 Lniack0_6;		/* 0xF8 */
+	u8 resa[3];		/* 0xF9 - 0xFB */
+	u8 Lniack0_7;		/* 0xFC */
+	u8 resb[3];		/* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct gptmr {
+	u8 ocpw;
+	u8 octict;
+	u8 ctrl;
+	u8 mode;
+
+	u16 pre;		/* Prescale */
+	u16 cnt;
+
+	u16 pwmwidth;
+	u8 pwmop;		/* Output Polarity */
+	u8 pwmld;		/* Immediate Update */
+
+	u16 cap;		/* Capture internal counter */
+	u8 ovfpin;		/* Ovf and Pin */
+	u8 intr;		/* Interrupts */
+} gptmr_t;
+
+typedef struct slt {
+	u32 tcnt;		/* 0x00 */
+	u32 cr;			/* 0x04 */
+	u32 cnt;		/* 0x08 */
+	u32 sr;			/* 0x0C */
+} slt_t;
+
+typedef struct gpio {
+	/* Port Output Data Registers */
+	u8 podr_fbctl;		/*0x00 */
+	u8 podr_fbcs;		/*0x01 */
+	u8 podr_dma;		/*0x02 */
+	u8 rsvd1;		/*0x03 */
+	u8 podr_fec0h;		/*0x04 */
+	u8 podr_fec0l;		/*0x05 */
+	u8 podr_fec1h;		/*0x06 */
+	u8 podr_fec1l;		/*0x07 */
+	u8 podr_feci2c;		/*0x08 */
+	u8 podr_pcibg;		/*0x09 */
+	u8 podr_pcibr;		/*0x0A */
+	u8 rsvd2;		/*0x0B */
+	u8 podr_psc3psc2;	/*0x0C */
+	u8 podr_psc1psc0;	/*0x0D */
+	u8 podr_dspi;		/*0x0E */
+	u8 rsvd3;		/*0x0F */
+
+	/* Port Data Direction Registers */
+	u8 pddr_fbctl;		/*0x10 */
+	u8 pddr_fbcs;		/*0x11 */
+	u8 pddr_dma;		/*0x12 */
+	u8 rsvd4;		/*0x13 */
+	u8 pddr_fec0h;		/*0x14 */
+	u8 pddr_fec0l;		/*0x15 */
+	u8 pddr_fec1h;		/*0x16 */
+	u8 pddr_fec1l;		/*0x17 */
+	u8 pddr_feci2c;		/*0x18 */
+	u8 pddr_pcibg;		/*0x19 */
+	u8 pddr_pcibr;		/*0x1A */
+	u8 rsvd5;		/*0x1B */
+	u8 pddr_psc3psc2;	/*0x1C */
+	u8 pddr_psc1psc0;	/*0x1D */
+	u8 pddr_dspi;		/*0x1E */
+	u8 rsvd6;		/*0x1F */
+
+	/* Port Pin Data/Set Data Registers */
+	u8 ppdsdr_fbctl;	/*0x20 */
+	u8 ppdsdr_fbcs;		/*0x21 */
+	u8 ppdsdr_dma;		/*0x22 */
+	u8 rsvd7;		/*0x23 */
+	u8 ppdsdr_fec0h;	/*0x24 */
+	u8 ppdsdr_fec0l;	/*0x25 */
+	u8 ppdsdr_fec1h;	/*0x26 */
+	u8 ppdsdr_fec1l;	/*0x27 */
+	u8 ppdsdr_feci2c;	/*0x28 */
+	u8 ppdsdr_pcibg;	/*0x29 */
+	u8 ppdsdr_pcibr;	/*0x2A */
+	u8 rsvd8;		/*0x2B */
+	u8 ppdsdr_psc3psc2;	/*0x2C */
+	u8 ppdsdr_psc1psc0;	/*0x2D */
+	u8 ppdsdr_dspi;		/*0x2E */
+	u8 rsvd9;		/*0x2F */
+
+	/* Port Clear Output Data Registers */
+	u8 pclrr_fbctl;		/*0x30 */
+	u8 pclrr_fbcs;		/*0x31 */
+	u8 pclrr_dma;		/*0x32 */
+	u8 rsvd10;		/*0x33 */
+	u8 pclrr_fec0h;		/*0x34 */
+	u8 pclrr_fec0l;		/*0x35 */
+	u8 pclrr_fec1h;		/*0x36 */
+	u8 pclrr_fec1l;		/*0x37 */
+	u8 pclrr_feci2c;	/*0x38 */
+	u8 pclrr_pcibg;		/*0x39 */
+	u8 pclrr_pcibr;		/*0x3A */
+	u8 rsvd11;		/*0x3B */
+	u8 pclrr_psc3psc2;	/*0x3C */
+	u8 pclrr_psc1psc0;	/*0x3D */
+	u8 pclrr_dspi;		/*0x3E */
+	u8 rsvd12;		/*0x3F */
+
+	/* Pin Assignment Registers */
+	u16 par_fbctl;		/*0x40 */
+	u8 par_fbcs;		/*0x42 */
+	u8 par_dma;		/*0x43 */
+	u16 par_feci2cirq;	/*0x44 */
+	u16 rsvd13;		/*0x46 */
+	u16 par_pcibg;		/*0x48 */
+	u16 par_pcibr;		/*0x4A */
+	u8 par_psc3;		/*0x4C */
+	u8 par_psc2;		/*0x4D */
+	u8 par_psc1;		/*0x4E */
+	u8 par_psc0;		/*0x4F */
+	u16 par_dspi;		/*0x50 */
+	u8 par_timer;		/*0x52 */
+	u8 rsvd14;		/*0x53 */
+} gpio_t;
+
+typedef struct pci {
+	u32 idr;		/* 0x00 Device Id / Vendor Id */
+	u32 scr;		/* 0x04 Status / command */
+	u32 ccrir;		/* 0x08 Class Code / Revision Id */
+	u32 cr1;		/* 0x0c Configuration 1 */
+	u32 bar0;		/* 0x10 Base address register 0 */
+	u32 bar1;		/* 0x14 Base address register 1 */
+	u32 bar2;		/* 0x18 NA */
+	u32 bar3;		/* 0x1c NA */
+	u32 bar4;		/* 0x20 NA */
+	u32 bar5;		/* 0x24 NA */
+	u32 ccpr;		/* 0x28 Cardbus CIS Pointer */
+	u32 sid;		/* 0x2c Subsystem ID / Subsystem Vendor ID */
+	u32 erbar;		/* 0x30 Expansion ROM Base Address */
+	u32 cpr;		/* 0x34 Capabilities Pointer */
+	u32 rsvd1;		/* 0x38 */
+	u32 cr2;		/* 0x3c Configuration 2 */
+	u32 rsvd2[8];		/* 0x40 - 0x5f */
+
+	/* General control / status registers */
+	u32 gscr;		/* 0x60 Global Status / Control */
+	u32 tbatr0a;		/* 0x64 Target Base Adr Translation 0 */
+	u32 tbatr1a;		/* 0x68 Target Base Adr Translation 1 */
+	u32 tcr1;		/* 0x6c Target Control 1 Register */
+	u32 iw0btar;		/* 0x70 Initiator Win 0 Base/Translation adr */
+	u32 iw1btar;		/* 0x74 Initiator Win 1 Base/Translation adr */
+	u32 iw2btar;		/* 0x78 NA */
+	u32 rsvd3;		/* 0x7c */
+	u32 iwcr;		/* 0x80 Initiator Window Configuration */
+	u32 icr;		/* 0x84 Initiator Control */
+	u32 isr;		/* 0x88 Initiator Status */
+	u32 tcr2;		/* 0x8c NA */
+	u32 tbatr0;		/* 0x90 NA */
+	u32 tbatr1;		/* 0x94 NA */
+	u32 tbatr2;		/* 0x98 NA */
+	u32 tbatr3;		/* 0x9c NA */
+	u32 tbatr4;		/* 0xa0 NA */
+	u32 tbatr5;		/* 0xa4 NA */
+	u32 intr;		/* 0xa8 NA */
+	u32 rsvd4[19];		/* 0xac - 0xf7 */
+	u32 car;		/* 0xf8 Configuration Address */
+} pci_t;
+
+typedef struct pci_arbiter {
+	/* Pci Arbiter Registers */
+	union {
+		u32 acr;	/* Arbiter Control */
+		u32 asr;	/* Arbiter Status */
+	};
+} pciarb_t;
+#endif				/* __IMMAP_547x_8x__ */
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 91d7592..33c454a 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -28,19 +28,13 @@
 
 #include <asm/byteorder.h>
 
-/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
- * two accesses to memory, which may be undesirable for some devices.
- */
-#define __raw_readb(addr) \
-    ({ u8 __v = (*(volatile u8 *) (addr)); __v; })
-#define __raw_readw(addr) \
-    ({ u16 __v = (*(volatile u16 *) (addr)); __v; })
-#define __raw_readl(addr) \
-    ({ u32 __v = (*(volatile u32 *) (addr)); __v; })
+#define __raw_readb(addr) (*(volatile u8 *)(addr))
+#define __raw_readw(addr) (*(volatile u16 *)(addr))
+#define __raw_readl(addr) (*(volatile u32 *)(addr))
 
-#define __raw_writeb(addr,b) (void)((*(volatile u8 *) (addr)) = (b))
-#define __raw_writew(addr,w) (void)((*(volatile u16 *) (addr)) = (w))
-#define __raw_writel(addr,l) (void)((*(volatile u32 *) (addr)) = (l))
+#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w))
+#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l))
 
 #define readb(addr)		in_8((volatile u8 *)(addr))
 #define writeb(b,addr)		out_8((volatile u8 *)(addr), (b))
@@ -245,8 +239,8 @@ typedef unsigned long phys_addr_t;
 #define MAP_WRBACK	(0)
 #define MAP_WRTHROUGH	(0)
 
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+static inline void *map_physmem(phys_addr_t paddr, unsigned long len,
+				unsigned long flags)
 {
 	return (void *)paddr;
 }
diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h
new file mode 100644
index 0000000..afd31ba
--- /dev/null
+++ b/include/asm-m68k/m5227x.h
@@ -0,0 +1,796 @@
+/*
+ * MCF5227x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCF5227X__
+#define __MCF5227X__
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EDMA_00			(8)
+#define INT0_LO_EDMA_01			(9)
+#define INT0_LO_EDMA_02			(10)
+#define INT0_LO_EDMA_03			(11)
+#define INT0_LO_EDMA_04			(12)
+#define INT0_LO_EDMA_05			(13)
+#define INT0_LO_EDMA_06			(14)
+#define INT0_LO_EDMA_07			(15)
+#define INT0_LO_EDMA_08			(16)
+#define INT0_LO_EDMA_09			(17)
+#define INT0_LO_EDMA_10			(18)
+#define INT0_LO_EDMA_11			(19)
+#define INT0_LO_EDMA_12			(20)
+#define INT0_LO_EDMA_13			(21)
+#define INT0_LO_EDMA_14			(22)
+#define INT0_LO_EDMA_15			(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM_CWIC		(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+#define INT0_LO_I2C			(30)
+#define INT0_LO_DSPI			(31)
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_SCMIR			(62)
+#define INT0_HI_RTC_ISR			(63)
+
+#define INT1_HI_CAN_BOFFINT		(1)
+#define INT1_HI_CAN_ERRINT		(3)
+#define INT1_HI_CAN_BUF0I		(4)
+#define INT1_HI_CAN_BUF1I		(5)
+#define INT1_HI_CAN_BUF2I		(6)
+#define INT1_HI_CAN_BUF3I		(7)
+#define INT1_HI_CAN_BUF4I		(8)
+#define INT1_HI_CAN_BUF5I		(9)
+#define INT1_HI_CAN_BUF6I		(10)
+#define INT1_HI_CAN_BUF7I		(11)
+#define INT1_HI_CAN_BUF8I		(12)
+#define INT1_HI_CAN_BUF9I		(13)
+#define INT1_HI_CAN_BUF10I		(14)
+#define INT1_HI_CAN_BUF11I		(15)
+#define INT1_HI_CAN_BUF12I		(16)
+#define INT1_HI_CAN_BUF13I		(17)
+#define INT1_HI_CAN_BUF14I		(18)
+#define INT1_HI_CAN_BUF15I		(19)
+#define INT1_HI_PIT0_PIF		(43)
+#define INT1_HI_PIT1_PIF		(44)
+#define INT1_HI_USBOTG_STS		(47)
+#define INT1_HI_SSI_ISR			(49)
+#define INT1_HI_PWM_INT			(50)
+#define INT1_HI_LCDC_ISR		(51)
+#define INT1_HI_CCM_UOCSR		(53)
+#define INT1_HI_DSPI_EOQF		(54)
+#define INT1_HI_DSPI_TFFF		(55)
+#define INT1_HI_DSPI_TCF		(56)
+#define INT1_HI_DSPI_TFUF		(57)
+#define INT1_HI_DSPI_RFDF		(58)
+#define INT1_HI_DSPI_RFOF		(59)
+#define INT1_HI_DSPI_RFOF_TFUF		(60)
+#define INT1_HI_TOUCH_ADC		(61)
+#define INT1_HI_PLL_LOCKS		(62)
+
+/* Bit definitions and macros for IPRH */
+#define INTC_IPRH_INT32			(0x00000001)
+#define INTC_IPRH_INT33			(0x00000002)
+#define INTC_IPRH_INT34			(0x00000004)
+#define INTC_IPRH_INT35			(0x00000008)
+#define INTC_IPRH_INT36			(0x00000010)
+#define INTC_IPRH_INT37			(0x00000020)
+#define INTC_IPRH_INT38			(0x00000040)
+#define INTC_IPRH_INT39			(0x00000080)
+#define INTC_IPRH_INT40			(0x00000100)
+#define INTC_IPRH_INT41			(0x00000200)
+#define INTC_IPRH_INT42			(0x00000400)
+#define INTC_IPRH_INT43			(0x00000800)
+#define INTC_IPRH_INT44			(0x00001000)
+#define INTC_IPRH_INT45			(0x00002000)
+#define INTC_IPRH_INT46			(0x00004000)
+#define INTC_IPRH_INT47			(0x00008000)
+#define INTC_IPRH_INT48			(0x00010000)
+#define INTC_IPRH_INT49			(0x00020000)
+#define INTC_IPRH_INT50			(0x00040000)
+#define INTC_IPRH_INT51			(0x00080000)
+#define INTC_IPRH_INT52			(0x00100000)
+#define INTC_IPRH_INT53			(0x00200000)
+#define INTC_IPRH_INT54			(0x00400000)
+#define INTC_IPRH_INT55			(0x00800000)
+#define INTC_IPRH_INT56			(0x01000000)
+#define INTC_IPRH_INT57			(0x02000000)
+#define INTC_IPRH_INT58			(0x04000000)
+#define INTC_IPRH_INT59			(0x08000000)
+#define INTC_IPRH_INT60			(0x10000000)
+#define INTC_IPRH_INT61			(0x20000000)
+#define INTC_IPRH_INT62			(0x40000000)
+#define INTC_IPRH_INT63			(0x80000000)
+
+/* Bit definitions and macros for IPRL */
+#define INTC_IPRL_INT0			(0x00000001)
+#define INTC_IPRL_INT1			(0x00000002)
+#define INTC_IPRL_INT2			(0x00000004)
+#define INTC_IPRL_INT3			(0x00000008)
+#define INTC_IPRL_INT4			(0x00000010)
+#define INTC_IPRL_INT5			(0x00000020)
+#define INTC_IPRL_INT6			(0x00000040)
+#define INTC_IPRL_INT7			(0x00000080)
+#define INTC_IPRL_INT8			(0x00000100)
+#define INTC_IPRL_INT9			(0x00000200)
+#define INTC_IPRL_INT10			(0x00000400)
+#define INTC_IPRL_INT11			(0x00000800)
+#define INTC_IPRL_INT12			(0x00001000)
+#define INTC_IPRL_INT13			(0x00002000)
+#define INTC_IPRL_INT14			(0x00004000)
+#define INTC_IPRL_INT15			(0x00008000)
+#define INTC_IPRL_INT16			(0x00010000)
+#define INTC_IPRL_INT17			(0x00020000)
+#define INTC_IPRL_INT18			(0x00040000)
+#define INTC_IPRL_INT19			(0x00080000)
+#define INTC_IPRL_INT20			(0x00100000)
+#define INTC_IPRL_INT21			(0x00200000)
+#define INTC_IPRL_INT22			(0x00400000)
+#define INTC_IPRL_INT23			(0x00800000)
+#define INTC_IPRL_INT24			(0x01000000)
+#define INTC_IPRL_INT25			(0x02000000)
+#define INTC_IPRL_INT26			(0x04000000)
+#define INTC_IPRL_INT27			(0x08000000)
+#define INTC_IPRL_INT28			(0x10000000)
+#define INTC_IPRL_INT29			(0x20000000)
+#define INTC_IPRL_INT30			(0x40000000)
+#define INTC_IPRL_INT31			(0x80000000)
+
+/* Bit definitions and macros for IMRH */
+#define INTC_IMRH_INT_MASK32		(0x00000001)
+#define INTC_IMRH_INT_MASK33		(0x00000002)
+#define INTC_IMRH_INT_MASK34		(0x00000004)
+#define INTC_IMRH_INT_MASK35		(0x00000008)
+#define INTC_IMRH_INT_MASK36		(0x00000010)
+#define INTC_IMRH_INT_MASK37		(0x00000020)
+#define INTC_IMRH_INT_MASK38		(0x00000040)
+#define INTC_IMRH_INT_MASK39		(0x00000080)
+#define INTC_IMRH_INT_MASK40		(0x00000100)
+#define INTC_IMRH_INT_MASK41		(0x00000200)
+#define INTC_IMRH_INT_MASK42		(0x00000400)
+#define INTC_IMRH_INT_MASK43		(0x00000800)
+#define INTC_IMRH_INT_MASK44		(0x00001000)
+#define INTC_IMRH_INT_MASK45		(0x00002000)
+#define INTC_IMRH_INT_MASK46		(0x00004000)
+#define INTC_IMRH_INT_MASK47		(0x00008000)
+#define INTC_IMRH_INT_MASK48		(0x00010000)
+#define INTC_IMRH_INT_MASK49		(0x00020000)
+#define INTC_IMRH_INT_MASK50		(0x00040000)
+#define INTC_IMRH_INT_MASK51		(0x00080000)
+#define INTC_IMRH_INT_MASK52		(0x00100000)
+#define INTC_IMRH_INT_MASK53		(0x00200000)
+#define INTC_IMRH_INT_MASK54		(0x00400000)
+#define INTC_IMRH_INT_MASK55		(0x00800000)
+#define INTC_IMRH_INT_MASK56		(0x01000000)
+#define INTC_IMRH_INT_MASK57		(0x02000000)
+#define INTC_IMRH_INT_MASK58		(0x04000000)
+#define INTC_IMRH_INT_MASK59		(0x08000000)
+#define INTC_IMRH_INT_MASK60		(0x10000000)
+#define INTC_IMRH_INT_MASK61		(0x20000000)
+#define INTC_IMRH_INT_MASK62		(0x40000000)
+#define INTC_IMRH_INT_MASK63		(0x80000000)
+
+/* Bit definitions and macros for IMRL */
+#define INTC_IMRL_INT_MASK0		(0x00000001)
+#define INTC_IMRL_INT_MASK1		(0x00000002)
+#define INTC_IMRL_INT_MASK2		(0x00000004)
+#define INTC_IMRL_INT_MASK3		(0x00000008)
+#define INTC_IMRL_INT_MASK4		(0x00000010)
+#define INTC_IMRL_INT_MASK5		(0x00000020)
+#define INTC_IMRL_INT_MASK6		(0x00000040)
+#define INTC_IMRL_INT_MASK7		(0x00000080)
+#define INTC_IMRL_INT_MASK8		(0x00000100)
+#define INTC_IMRL_INT_MASK9		(0x00000200)
+#define INTC_IMRL_INT_MASK10		(0x00000400)
+#define INTC_IMRL_INT_MASK11		(0x00000800)
+#define INTC_IMRL_INT_MASK12		(0x00001000)
+#define INTC_IMRL_INT_MASK13		(0x00002000)
+#define INTC_IMRL_INT_MASK14		(0x00004000)
+#define INTC_IMRL_INT_MASK15		(0x00008000)
+#define INTC_IMRL_INT_MASK16		(0x00010000)
+#define INTC_IMRL_INT_MASK17		(0x00020000)
+#define INTC_IMRL_INT_MASK18		(0x00040000)
+#define INTC_IMRL_INT_MASK19		(0x00080000)
+#define INTC_IMRL_INT_MASK20		(0x00100000)
+#define INTC_IMRL_INT_MASK21		(0x00200000)
+#define INTC_IMRL_INT_MASK22		(0x00400000)
+#define INTC_IMRL_INT_MASK23		(0x00800000)
+#define INTC_IMRL_INT_MASK24		(0x01000000)
+#define INTC_IMRL_INT_MASK25		(0x02000000)
+#define INTC_IMRL_INT_MASK26		(0x04000000)
+#define INTC_IMRL_INT_MASK27		(0x08000000)
+#define INTC_IMRL_INT_MASK28		(0x10000000)
+#define INTC_IMRL_INT_MASK29		(0x20000000)
+#define INTC_IMRL_INT_MASK30		(0x40000000)
+#define INTC_IMRL_INT_MASK31		(0x80000000)
+
+/* Bit definitions and macros for INTFRCH */
+#define INTC_INTFRCH_INTFRC32		(0x00000001)
+#define INTC_INTFRCH_INTFRC33		(0x00000002)
+#define INTC_INTFRCH_INTFRC34		(0x00000004)
+#define INTC_INTFRCH_INTFRC35		(0x00000008)
+#define INTC_INTFRCH_INTFRC36		(0x00000010)
+#define INTC_INTFRCH_INTFRC37		(0x00000020)
+#define INTC_INTFRCH_INTFRC38		(0x00000040)
+#define INTC_INTFRCH_INTFRC39		(0x00000080)
+#define INTC_INTFRCH_INTFRC40		(0x00000100)
+#define INTC_INTFRCH_INTFRC41		(0x00000200)
+#define INTC_INTFRCH_INTFRC42		(0x00000400)
+#define INTC_INTFRCH_INTFRC43		(0x00000800)
+#define INTC_INTFRCH_INTFRC44		(0x00001000)
+#define INTC_INTFRCH_INTFRC45		(0x00002000)
+#define INTC_INTFRCH_INTFRC46		(0x00004000)
+#define INTC_INTFRCH_INTFRC47		(0x00008000)
+#define INTC_INTFRCH_INTFRC48		(0x00010000)
+#define INTC_INTFRCH_INTFRC49		(0x00020000)
+#define INTC_INTFRCH_INTFRC50		(0x00040000)
+#define INTC_INTFRCH_INTFRC51		(0x00080000)
+#define INTC_INTFRCH_INTFRC52		(0x00100000)
+#define INTC_INTFRCH_INTFRC53		(0x00200000)
+#define INTC_INTFRCH_INTFRC54		(0x00400000)
+#define INTC_INTFRCH_INTFRC55		(0x00800000)
+#define INTC_INTFRCH_INTFRC56		(0x01000000)
+#define INTC_INTFRCH_INTFRC57		(0x02000000)
+#define INTC_INTFRCH_INTFRC58		(0x04000000)
+#define INTC_INTFRCH_INTFRC59		(0x08000000)
+#define INTC_INTFRCH_INTFRC60		(0x10000000)
+#define INTC_INTFRCH_INTFRC61		(0x20000000)
+#define INTC_INTFRCH_INTFRC62		(0x40000000)
+#define INTC_INTFRCH_INTFRC63		(0x80000000)
+
+/* Bit definitions and macros for INTFRCL */
+#define INTC_INTFRCL_INTFRC0		(0x00000001)
+#define INTC_INTFRCL_INTFRC1		(0x00000002)
+#define INTC_INTFRCL_INTFRC2		(0x00000004)
+#define INTC_INTFRCL_INTFRC3		(0x00000008)
+#define INTC_INTFRCL_INTFRC4		(0x00000010)
+#define INTC_INTFRCL_INTFRC5		(0x00000020)
+#define INTC_INTFRCL_INTFRC6		(0x00000040)
+#define INTC_INTFRCL_INTFRC7		(0x00000080)
+#define INTC_INTFRCL_INTFRC8		(0x00000100)
+#define INTC_INTFRCL_INTFRC9		(0x00000200)
+#define INTC_INTFRCL_INTFRC10		(0x00000400)
+#define INTC_INTFRCL_INTFRC11		(0x00000800)
+#define INTC_INTFRCL_INTFRC12		(0x00001000)
+#define INTC_INTFRCL_INTFRC13		(0x00002000)
+#define INTC_INTFRCL_INTFRC14		(0x00004000)
+#define INTC_INTFRCL_INTFRC15		(0x00008000)
+#define INTC_INTFRCL_INTFRC16		(0x00010000)
+#define INTC_INTFRCL_INTFRC17		(0x00020000)
+#define INTC_INTFRCL_INTFRC18		(0x00040000)
+#define INTC_INTFRCL_INTFRC19		(0x00080000)
+#define INTC_INTFRCL_INTFRC20		(0x00100000)
+#define INTC_INTFRCL_INTFRC21		(0x00200000)
+#define INTC_INTFRCL_INTFRC22		(0x00400000)
+#define INTC_INTFRCL_INTFRC23		(0x00800000)
+#define INTC_INTFRCL_INTFRC24		(0x01000000)
+#define INTC_INTFRCL_INTFRC25		(0x02000000)
+#define INTC_INTFRCL_INTFRC26		(0x04000000)
+#define INTC_INTFRCL_INTFRC27		(0x08000000)
+#define INTC_INTFRCL_INTFRC28		(0x10000000)
+#define INTC_INTFRCL_INTFRC29		(0x20000000)
+#define INTC_INTFRCL_INTFRC30		(0x40000000)
+#define INTC_INTFRCL_INTFRC31		(0x80000000)
+
+/* Bit definitions and macros for ICONFIG */
+#define INTC_ICONFIG_EMASK		(0x0020)
+#define INTC_ICONFIG_ELVLPRI1		(0x0200)
+#define INTC_ICONFIG_ELVLPRI2		(0x0400)
+#define INTC_ICONFIG_ELVLPRI3		(0x0800)
+#define INTC_ICONFIG_ELVLPRI4		(0x1000)
+#define INTC_ICONFIG_ELVLPRI5		(0x2000)
+#define INTC_ICONFIG_ELVLPRI6		(0x4000)
+#define INTC_ICONFIG_ELVLPRI7		(0x8000)
+
+/* Bit definitions and macros for SIMR */
+#define INTC_SIMR_SIMR(x)		(((x)&0x7F))
+
+/* Bit definitions and macros for CIMR */
+#define INTC_CIMR_CIMR(x)		(((x)&0x7F))
+
+/* Bit definitions and macros for CLMASK */
+#define INTC_CLMASK_CLMASK(x)		(((x)&0x0F))
+
+/* Bit definitions and macros for SLMASK */
+#define INTC_SLMASK_SLMASK(x)		(((x)&0x0F))
+
+/* Bit definitions and macros for ICR group */
+#define INTC_ICR_IL(x)			(((x)&0x07))
+
+/*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT		(0x40)
+#define RCM_RCR_SOFTRST			(0x80)
+
+/* Bit definitions and macros for RSR */
+#define RCM_RSR_LOL			(0x01)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_SOFT			(0x20)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+
+/* Bit definitions and macros for CCR */
+#define CCM_CCR_DRAMSEL			(0x0100)
+#define CCM_CCR_CSC_MASK		(0xFF3F)
+#define CCM_CCR_CSC_FBCS5_CS4		(0x00C0)
+#define CCM_CCR_CSC_FBCS5_A22		(0x0080)
+#define CCM_CCR_CSC_FB_A23_A22		(0x0040)
+#define CCM_CCR_LIMP			(0x0020)
+#define CCM_CCR_LOAD			(0x0010)
+#define CCM_CCR_BOOTPS_MASK		(0xFFF3)
+#define CCM_CCR_BOOTPS_PS16		(0x0008)
+#define CCM_CCR_BOOTPS_PS8		(0x0004)
+#define CCM_CCR_BOOTPS_PS32		(0x0000)
+#define CCM_CCR_OSCMODE_OSCBYPASS	(0x0002)
+
+/* Bit definitions and macros for RCON */
+#define CCM_RCON_CSC_MASK		(0xFF3F)
+#define CCM_RCON_CSC_FBCS5_CS4		(0x00C0)
+#define CCM_RCON_CSC_FBCS5_A22		(0x0080)
+#define CCM_RCON_CSC_FB_A23_A22		(0x0040)
+#define CCM_RCON_LIMP			(0x0020)
+#define CCM_RCON_LOAD			(0x0010)
+#define CCM_RCON_BOOTPS_MASK		(0xFFF3)
+#define CCM_RCON_BOOTPS_PS16		(0x0008)
+#define CCM_RCON_BOOTPS_PS8		(0x0004)
+#define CCM_RCON_BOOTPS_PS32		(0x0000)
+#define CCM_RCON_OSCMODE_OSCBYPASS	(0x0002)
+
+/* Bit definitions and macros for CIR */
+#define CCM_CIR_PRN(x)			(((x)&0x003F))	/* Part revision number */
+#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)	/* Part identification number */
+#define CCM_CIR_PIN_MASK		(0xFFC0)
+#define CCM_CIR_PRN_MASK		(0x003F)
+#define CCM_CIR_PIN_MCF52277		(0x0000)
+
+/* Bit definitions and macros for MISCCR */
+#define CCM_MISCCR_RTCSRC		(0x4000)
+#define CCM_MISCCR_USBPUE		(0x2000)	/* USB transceiver pull-up */
+#define CCM_MISCCR_LIMP			(0x1000)	/* Limp mode enable */
+
+#define CCM_MISCCR_BME			(0x0800)	/* Bus monitor ext en bit */
+#define CCM_MISCCR_BMT_65536		(0)
+#define CCM_MISCCR_BMT_32768		(1)
+#define CCM_MISCCR_BMT_16384		(2)
+#define CCM_MISCCR_BMT_8192		(3)
+#define CCM_MISCCR_BMT_4096		(4)
+#define CCM_MISCCR_BMT_2048		(5)
+#define CCM_MISCCR_BMT_1024		(6)
+#define CCM_MISCCR_BMT_512		(7)
+
+#define CCM_MISCCR_SSIPUE		(0x0080)	/* SSI RXD/TXD pull enable */
+#define CCM_MISCCR_SSIPUS		(0x0040)	/* SSI RXD/TXD pull select */
+#define CCM_MISCCR_TIMDMA		(0x0020)	/* Timer DMA mux selection */
+#define CCM_MISCCR_SSISRC		(0x0010)	/* SSI clock source */
+#define CCM_MISCCR_LCDCHEN		(0x0004)	/* LCD Int CLK en */
+#define CCM_MISCCR_USBOC		(0x0002)	/* USB VBUS over-current sense pol */
+#define CCM_MISCCR_USBSRC		(0x0001)	/* USB clock source */
+
+/* Bit definitions and macros for CDR */
+#define CCM_CDR_USBDIV(x)		(((x)&0x0003)<<12)
+#define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)	/* Low power clk div */
+#define CCM_CDR_SSIDIV(x)		(((x)&0x00FF))	/* SSI oversampling clk div */
+
+/* Bit definitions and macros for UOCSR */
+#define CCM_UOCSR_DPPD			(0x2000)	/* D+ 15Kohm pull-down (rd-only) */
+#define CCM_UOCSR_DMPD			(0x1000)	/* D- 15Kohm pull-down (rd-only) */
+#define CCM_UOCSR_CRG_VBUS		(0x0400)	/* VBUS charge resistor enabled (rd-only) */
+#define CCM_UOCSR_DCR_VBUS		(0x0200)	/* VBUS discharge resistor en (rd-only) */
+#define CCM_UOCSR_DPPU			(0x0100)	/* D+ pull-up for FS enabled (rd-only) */
+#define CCM_UOCSR_AVLD			(0x0080)	/* A-peripheral valid indicator */
+#define CCM_UOCSR_BVLD			(0x0040)	/* B-peripheral valid indicator */
+#define CCM_UOCSR_VVLD			(0x0020)	/* VBUS valid indicator */
+#define CCM_UOCSR_SEND			(0x0010)	/* Session end */
+#define CCM_UOCSR_WKUP			(0x0004)	/* USB OTG controller wake-up event */
+#define CCM_UOCSR_UOMIE			(0x0002)	/* USB OTG misc interrupt en */
+#define CCM_UOCSR_XPDE			(0x0001)	/* On-chip transceiver pull-down en */
+
+/*********************************************************************
+* General Purpose I/O Module (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for PAR_BE */
+#define GPIO_PAR_BE_MASK		(0x0F)
+#define GPIO_PAR_BE_BE3_BE3		(0x08)
+#define GPIO_PAR_BE_BE3_GPIO		(0x00)
+#define GPIO_PAR_BE_BE2_BE2		(0x04)
+#define GPIO_PAR_BE_BE2_GPIO		(0x00)
+#define GPIO_PAR_BE_BE1_BE1		(0x02)
+#define GPIO_PAR_BE_BE1_GPIO		(0x00)
+#define GPIO_PAR_BE_BE0_BE0		(0x01)
+#define GPIO_PAR_BE_BE0_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_CS */
+#define GPIO_PAR_CS_CS3			(0x10)
+#define GPIO_PAR_CS_CS2			(0x08)
+#define GPIO_PAR_CS_CS1_FBCS1		(0x06)
+#define GPIO_PAR_CS_CS1_SDCS1		(0x04)
+#define GPIO_PAR_CS_CS1_GPIO		(0x00)
+#define GPIO_PAR_CS_CS0			(0x01)
+
+/* Bit definitions and macros for PAR_FBCTL */
+#define GPIO_PAR_FBCTL_OE		(0x80)
+#define GPIO_PAR_FBCTL_TA		(0x40)
+#define GPIO_PAR_FBCTL_RW		(0x20)
+#define GPIO_PAR_FBCTL_TS_MASK		(0xE7)
+#define GPIO_PAR_FBCTL_TS_FBTS		(0x18)
+#define GPIO_PAR_FBCTL_TS_DMAACK	(0x10)
+#define GPIO_PAR_FBCTL_TS_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_FECI2C */
+#define GPIO_PAR_I2C_SCL_MASK		(0xF3)
+#define GPIO_PAR_I2C_SCL_SCL		(0x0C)
+#define GPIO_PAR_I2C_SCL_CANTXD		(0x08)
+#define GPIO_PAR_I2C_SCL_U2TXD		(0x04)
+#define GPIO_PAR_I2C_SCL_GPIO		(0x00)
+
+#define GPIO_PAR_I2C_SDA_MASK		(0xFC)
+#define GPIO_PAR_I2C_SDA_SDA		(0x03)
+#define GPIO_PAR_I2C_SDA_CANRXD		(0x02)
+#define GPIO_PAR_I2C_SDA_U2RXD		(0x01)
+#define GPIO_PAR_I2C_SDA_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_UART */
+#define GPIO_PAR_UART_U1CTS_MASK	(0x3FFF)
+#define GPIO_PAR_UART_U1CTS_U1CTS	(0xC000)
+#define GPIO_PAR_UART_U1CTS_SSIBCLK	(0x8000)
+#define GPIO_PAR_UART_U1CTS_LCDCLS	(0x4000)
+#define GPIO_PAR_UART_U1CTS_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U1RTS_MASK	(0xCFFF)
+#define GPIO_PAR_UART_U1RTS_U1RTS	(0x3000)
+#define GPIO_PAR_UART_U1RTS_SSIFS	(0x2000)
+#define GPIO_PAR_UART_U1RTS_LCDPS	(0x1000)
+#define GPIO_PAR_UART_U1RTS_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U1RXD_MASK	(0xF3FF)
+#define GPIO_PAR_UART_U1RXD_U1RXD	(0x0C00)
+#define GPIO_PAR_UART_U1RXD_SSIRXD	(0x0800)
+#define GPIO_PAR_UART_U1RXD_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U1TXD_MASK	(0xFCFF)
+#define GPIO_PAR_UART_U1TXD_U1TXD	(0x0300)
+#define GPIO_PAR_UART_U1TXD_SSITXD	(0x0200)
+#define GPIO_PAR_UART_U1TXD_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U0CTS_MASK	(0xFF3F)
+#define GPIO_PAR_UART_U0CTS_U0CTS	(0x00C0)
+#define GPIO_PAR_UART_U0CTS_T1OUT	(0x0080)
+#define GPIO_PAR_UART_U0CTS_USBVBUSEN	(0x0040)
+#define GPIO_PAR_UART_U0CTS_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U0RTS_MASK	(0xFFCF)
+#define GPIO_PAR_UART_U0RTS_U0RTS	(0x0030)
+#define GPIO_PAR_UART_U0RTS_T1IN	(0x0020)
+#define GPIO_PAR_UART_U0RTS_USBVBUSOC	(0x0010)
+#define GPIO_PAR_UART_U0RTS_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U0RXD_MASK	(0xFFF3)
+#define GPIO_PAR_UART_U0RXD_U0RXD	(0x000C)
+#define GPIO_PAR_UART_U0RXD_CANRX	(0x0008)
+#define GPIO_PAR_UART_U0RXD_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U0TXD_MASK	(0xFFFC)
+#define GPIO_PAR_UART_U0TXD_U0TXD	(0x0003)
+#define GPIO_PAR_UART_U0TXD_CANTX	(0x0002)
+#define GPIO_PAR_UART_U0TXD_GPIO	(0x0000)
+
+/* Bit definitions and macros for PAR_DSPI */
+#define GPIO_PAR_DSPI_PCS0_MASK		(0x3F)
+#define GPIO_PAR_DSPI_PCS0_PCS0		(0x80)
+#define GPIO_PAR_DSPI_PCS0_U2RTS	(0x40)
+#define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)
+#define GPIO_PAR_DSPI_SIN_MASK		(0xCF)
+#define GPIO_PAR_DSPI_SIN_SIN		(0x30)
+#define GPIO_PAR_DSPI_SIN_U2RXD		(0x20)
+#define GPIO_PAR_DSPI_SIN_GPIO		(0x00)
+#define GPIO_PAR_DSPI_SOUT_MASK		(0xF3)
+#define GPIO_PAR_DSPI_SOUT_SOUT		(0x0C)
+#define GPIO_PAR_DSPI_SOUT_U2TXD	(0x08)
+#define GPIO_PAR_DSPI_SOUT_GPIO		(0x00)
+#define GPIO_PAR_DSPI_SCK_MASK		(0xFC)
+#define GPIO_PAR_DSPI_SCK_SCK		(0x03)
+#define GPIO_PAR_DSPI_SCK_U2CTS		(0x02)
+#define GPIO_PAR_DSPI_SCK_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_TIMER */
+#define GPIO_PAR_TIMER_T3IN_MASK	(0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
+#define GPIO_PAR_TIMER_T3IN_SSIMCLK	(0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T2IN_MASK	(0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
+#define GPIO_PAR_TIMER_T2IN_DSPIPCS2	(0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T1IN_MASK	(0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
+#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST	(0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T0IN_MASK	(0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
+#define GPIO_PAR_TIMER_T0IN_LCDREV	(0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
+
+/* Bit definitions and macros for GPIO_PAR_LCDCTL */
+#define GPIO_PAR_LCDCTL_ACDOE_MASK	(0xE7)
+#define GPIO_PAR_LCDCTL_ACDOE_ACDOE	(0x18)
+#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR	(0x10)
+#define GPIO_PAR_LCDCTL_ACDOE_GPIO	(0x00)
+#define GPIO_PAR_LCDCTL_FLM_VSYNC	(0x04)
+#define GPIO_PAR_LCDCTL_LP_HSYNC	(0x02)
+#define GPIO_PAR_LCDCTL_LSCLK		(0x01)
+
+/* Bit definitions and macros for PAR_IRQ */
+#define GPIO_PAR_IRQ_IRQ4_MASK		(0xF3)
+#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK	(0x0C)
+#define GPIO_PAR_IRQ_IRQ4_DMAREQ0	(0x08)
+#define GPIO_PAR_IRQ_IRQ4_GPIO		(0x00)
+#define GPIO_PAR_IRQ_IRQ1_MASK		(0xFC)
+#define GPIO_PAR_IRQ_IRQ1_PCIINT	(0x03)
+#define GPIO_PAR_IRQ_IRQ1_USBCLKIN	(0x02)
+#define GPIO_PAR_IRQ_IRQ1_SSICLKIN	(0x01)
+#define GPIO_PAR_IRQ_IRQ1_GPIO		(0x00)
+
+/* Bit definitions and macros for GPIO_PAR_LCDH */
+#define GPIO_PAR_LCDH_LD17_MASK		(0xFFFFF3FF)
+#define GPIO_PAR_LCDH_LD17_LD17		(0x00000C00)
+#define GPIO_PAR_LCDH_LD17_LD11		(0x00000800)
+#define GPIO_PAR_LCDH_LD17_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD16_MASK		(0xFFFFFCFF)
+#define GPIO_PAR_LCDH_LD16_LD16		(0x00000300)
+#define GPIO_PAR_LCDH_LD16_LD10		(0x00000200)
+#define GPIO_PAR_LCDH_LD16_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD15_MASK		(0xFFFFFF3F)
+#define GPIO_PAR_LCDH_LD15_LD15		(0x000000C0)
+#define GPIO_PAR_LCDH_LD15_LD9		(0x00000080)
+#define GPIO_PAR_LCDH_LD15_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD14_MASK		(0xFFFFFFCF)
+#define GPIO_PAR_LCDH_LD14_LD14		(0x00000030)
+#define GPIO_PAR_LCDH_LD14_LD8		(0x00000020)
+#define GPIO_PAR_LCDH_LD14_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD13_MASK		(0xFFFFFFF3)
+#define GPIO_PAR_LCDH_LD13_LD13		(0x0000000C)
+#define GPIO_PAR_LCDH_LD13_CANTX	(0x00000008)
+#define GPIO_PAR_LCDH_LD13_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD12_MASK		(0xFFFFFFFC)
+#define GPIO_PAR_LCDH_LD12_LD12		(0x00000003)
+#define GPIO_PAR_LCDH_LD12_CANRX	(0x00000002)
+#define GPIO_PAR_LCDH_LD12_GPIO		(0x00000000)
+
+/* Bit definitions and macros for GPIO_PAR_LCDL */
+#define GPIO_PAR_LCDL_LD11_MASK		(0x3FFFFFFF)
+#define GPIO_PAR_LCDL_LD11_LD11		(0xC0000000)
+#define GPIO_PAR_LCDL_LD11_LD7		(0x80000000)
+#define GPIO_PAR_LCDL_LD11_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD10_MASK		(0xCFFFFFFF)
+#define GPIO_PAR_LCDL_LD10_LD10		(0x30000000)
+#define GPIO_PAR_LCDL_LD10_LD6		(0x20000000)
+#define GPIO_PAR_LCDL_LD10_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD9_MASK		(0xF3FFFFFF)
+#define GPIO_PAR_LCDL_LD9_LD9		(0x0C000000)
+#define GPIO_PAR_LCDL_LD9_LD5		(0x08000000)
+#define GPIO_PAR_LCDL_LD9_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD8_MASK		(0xFCFFFFFF)
+#define GPIO_PAR_LCDL_LD8_LD8		(0x03000000)
+#define GPIO_PAR_LCDL_LD8_LD4		(0x02000000)
+#define GPIO_PAR_LCDL_LD8_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD7_MASK		(0xFF3FFFFF)
+#define GPIO_PAR_LCDL_LD7_LD7		(0x00C00000)
+#define GPIO_PAR_LCDL_LD7_PWM7		(0x00800000)
+#define GPIO_PAR_LCDL_LD7_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD6_MASK		(0xFFCFFFFF)
+#define GPIO_PAR_LCDL_LD6_LD6		(0x00300000)
+#define GPIO_PAR_LCDL_LD6_PWM5		(0x00200000)
+#define GPIO_PAR_LCDL_LD6_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD5_MASK		(0xFFF3FFFF)
+#define GPIO_PAR_LCDL_LD5_LD5		(0x000C0000)
+#define GPIO_PAR_LCDL_LD5_LD3		(0x00080000)
+#define GPIO_PAR_LCDL_LD5_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD4_MASK		(0xFFFCFFFF)
+#define GPIO_PAR_LCDL_LD4_LD4		(0x00030000)
+#define GPIO_PAR_LCDL_LD4_LD2		(0x00020000)
+#define GPIO_PAR_LCDL_LD4_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD3_MASK		(0xFFFF3FFF)
+#define GPIO_PAR_LCDL_LD3_LD3		(0x0000C000)
+#define GPIO_PAR_LCDL_LD3_LD1		(0x00008000)
+#define GPIO_PAR_LCDL_LD3_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD2_MASK		(0xFFFFCFFF)
+#define GPIO_PAR_LCDL_LD2_LD2		(0x00003000)
+#define GPIO_PAR_LCDL_LD2_LD0		(0x00002000)
+#define GPIO_PAR_LCDL_LD2_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD1_MASK		(0xFFFFF3FF)
+#define GPIO_PAR_LCDL_LD1_LD1		(0x00000C00)
+#define GPIO_PAR_LCDL_LD1_PWM3		(0x00000800)
+#define GPIO_PAR_LCDL_LD1_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD0_MASK		(0xFFFFFCFF)
+#define GPIO_PAR_LCDL_LD0_LD0		(0x00000300)
+#define GPIO_PAR_LCDL_LD0_PWM1		(0x00000200)
+#define GPIO_PAR_LCDL_LD0_GPIO		(0x00000000)
+
+/* Bit definitions and macros for MSCR_FB */
+#define GPIO_MSCR_FB_DUPPER_MASK	(0xCF)
+#define GPIO_MSCR_FB_DUPPER_25V_33V	(0x30)
+#define GPIO_MSCR_FB_DUPPER_FULL_18V	(0x20)
+#define GPIO_MSCR_FB_DUPPER_OD		(0x10)
+#define GPIO_MSCR_FB_DUPPER_HALF_18V	(0x00)
+
+#define GPIO_MSCR_FB_DLOWER_MASK	(0xF3)
+#define GPIO_MSCR_FB_DLOWER_25V_33V	(0x0C)
+#define GPIO_MSCR_FB_DLOWER_FULL_18V	(0x08)
+#define GPIO_MSCR_FB_DLOWER_OD		(0x04)
+#define GPIO_MSCR_FB_DLOWER_HALF_18V	(0x00)
+
+#define GPIO_MSCR_FB_ADDRCTL_MASK	(0xFC)
+#define GPIO_MSCR_FB_ADDRCTL_25V_33V	(0x03)
+#define GPIO_MSCR_FB_ADDRCTL_FULL_18V	(0x02)
+#define GPIO_MSCR_FB_ADDRCTL_OD		(0x01)
+#define GPIO_MSCR_FB_ADDRCTL_HALF_18V	(0x00)
+
+/* Bit definitions and macros for MSCR_SDRAM */
+#define GPIO_MSCR_SDRAM_SDCLKB_MASK	(0xCF)
+#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V	(0x30)
+#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V	(0x20)
+#define GPIO_MSCR_SDRAM_SDCLKB_OD	(0x10)
+#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V	(0x00)
+
+#define GPIO_MSCR_SDRAM_SDCLK_MASK	(0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_25V_33V	(0x0C)
+#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V	(0x08)
+#define GPIO_MSCR_SDRAM_SDCLK_OPD	(0x04)
+#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V	(0x00)
+
+#define GPIO_MSCR_SDRAM_SDCTL_MASK	(0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_25V_33V	(0x03)
+#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V	(0x02)
+#define GPIO_MSCR_SDRAM_SDCTL_OPD	(0x01)
+#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V	(0x00)
+
+/* Bit definitions and macros for Drive Strength Control */
+#define DSCR_LOAD_50PF	(0x03)
+#define DSCR_LOAD_30PF	(0x02)
+#define DSCR_LOAD_20PF	(0x01)
+#define DSCR_LOAD_10PF	(0x00)
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+
+/* Bit definitions and macros for SDMR */
+#define SDRAMC_SDMR_DDR2_AD(x)		(((x)&0x00003FFF))	/* Address for DDR2 */
+#define SDRAMC_SDMR_CMD			(0x00010000)	/* Command */
+#define SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)	/* Address */
+#define SDRAMC_SDMR_BK(x)		(((x)&0x00000003)<<30)	/* Bank Address */
+#define SDRAMC_SDMR_BK_LMR		(0x00000000)
+#define SDRAMC_SDMR_BK_LEMR		(0x40000000)
+
+/* Bit definitions and macros for SDCR */
+#define SDRAMC_SDCR_DPD			(0x00000001)	/* Deep Power-Down Mode */
+#define SDRAMC_SDCR_IPALL		(0x00000002)	/* Initiate Precharge All */
+#define SDRAMC_SDCR_IREF		(0x00000004)	/* Initiate Refresh */
+#define SDRAMC_SDCR_DQS_OE(x)		(((x)&0x00000003)<<10)	/* DQS Output Enable */
+#define SDRAMC_SDCR_MEM_PS		(0x00002000)	/* Data Port Size */
+#define SDRAMC_SDCR_REF_CNT(x)		(((x)&0x0000003F)<<16)	/* Periodic Refresh Counter */
+#define SDRAMC_SDCR_OE_RULE		(0x00400000)	/* Drive Rule Selection */
+#define SDRAMC_SDCR_ADDR_MUX(x)		(((x)&0x00000003)<<24)	/* Internal Address Mux Select */
+#define SDRAMC_SDCR_DDR2_MODE		(0x08000000)	/* DDR2 Mode Select */
+#define SDRAMC_SDCR_REF_EN		(0x10000000)	/* Refresh Enable */
+#define SDRAMC_SDCR_DDR_MODE		(0x20000000)	/* DDR Mode Select */
+#define SDRAMC_SDCR_CKE			(0x40000000)	/* Clock Enable */
+#define SDRAMC_SDCR_MODE_EN		(0x80000000)	/* SDRAM Mode Register Programming Enable */
+#define SDRAMC_SDCR_DQS_OE_BOTH		(0x00000C000)
+
+/* Bit definitions and macros for SDCFG1 */
+#define SDRAMC_SDCFG1_WT_LAT(x)		(((x)&0x00000007)<<4)	/* Write Latency */
+#define SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)	/* Refresh to active delay */
+#define SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)	/* Precharge to active delay */
+#define SDRAMC_SDCFG1_ACT2RW(x)		(((x)&0x00000007)<<16)	/* Active to read/write delay */
+#define SDRAMC_SDCFG1_RD_LAT(x)		(((x)&0x0000000F)<<20)	/* Read CAS Latency */
+#define SDRAMC_SDCFG1_SWT2RWP(x)	(((x)&0x00000007)<<24)	/* Single write to read/write/precharge delay */
+#define SDRAMC_SDCFG1_SRD2RWP(x)	(((x)&0x0000000F)<<28)	/* Single read to read/write/precharge delay */
+
+/* Bit definitions and macros for SDCFG2 */
+#define SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)	/* Burst Length */
+#define SDRAMC_SDCFG2_BRD2W(x)		(((x)&0x0000000F)<<20)	/* Burst read to write delay */
+#define SDRAMC_SDCFG2_BWT2RWP(x)	(((x)&0x0000000F)<<24)	/* Burst write to read/write/precharge delay */
+#define SDRAMC_SDCFG2_BRD2RP(x)		(((x)&0x0000000F)<<28)	/* Burst read to read/precharge delay */
+
+/* Bit definitions and macros for SDCS group */
+#define SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F))	/* Chip-Select Size */
+#define SDRAMC_SDCS_CSBA(x)		(((x)&0x00000FFF)<<20)	/* Chip-Select Base Address */
+#define SDRAMC_SDCS_BA(x)		((x)&0xFFF00000)
+#define SDRAMC_SDCS_CSSZ_DISABLE	(0x00000000)
+#define SDRAMC_SDCS_CSSZ_1MBYTE		(0x00000013)
+#define SDRAMC_SDCS_CSSZ_2MBYTE		(0x00000014)
+#define SDRAMC_SDCS_CSSZ_4MBYTE		(0x00000015)
+#define SDRAMC_SDCS_CSSZ_8MBYTE		(0x00000016)
+#define SDRAMC_SDCS_CSSZ_16MBYTE	(0x00000017)
+#define SDRAMC_SDCS_CSSZ_32MBYTE	(0x00000018)
+#define SDRAMC_SDCS_CSSZ_64MBYTE	(0x00000019)
+#define SDRAMC_SDCS_CSSZ_128MBYTE	(0x0000001A)
+#define SDRAMC_SDCS_CSSZ_256MBYTE	(0x0000001B)
+#define SDRAMC_SDCS_CSSZ_512MBYTE	(0x0000001C)
+#define SDRAMC_SDCS_CSSZ_1GBYTE		(0x0000001D)
+#define SDRAMC_SDCS_CSSZ_2GBYTE		(0x0000001E)
+#define SDRAMC_SDCS_CSSZ_4GBYTE		(0x0000001F)
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+
+/* Bit definitions and macros for PCR */
+#define PLL_PCR_OUTDIV1(x)		(((x)&0x0000000F))	/* Output divider for CPU clock frequency */
+#define PLL_PCR_OUTDIV2(x)		(((x)&0x0000000F)<<4)	/* Output divider for bus/flexbus clock frequency */
+#define PLL_PCR_OUTDIV3(x)		(((x)&0x0000000F)<<8)	/* Output divider for SDRAM clock frequency */
+#define PLL_PCR_OUTDIV5(x)		(((x)&0x0000000F)<<16)	/* Output divider for USB clock frequency */
+#define PLL_PCR_PFDR(x)			(((x)&0x000000FF)<<24)	/* Feedback divider for VCO frequency */
+#define PLL_PCR_PFDR_MASK		(0x000F0000)
+#define PLL_PCR_OUTDIV5_MASK		(0x000F0000)
+#define PLL_PCR_OUTDIV3_MASK		(0x00000F00)
+#define PLL_PCR_OUTDIV2_MASK		(0x000000F0)
+#define PLL_PCR_OUTDIV1_MASK		(0x0000000F)
+
+/* Bit definitions and macros for PSR */
+#define PLL_PSR_LOCKS			(0x00000001)	/* PLL lost lock - sticky */
+#define PLL_PSR_LOCK			(0x00000002)	/* PLL lock status */
+#define PLL_PSR_LOLIRQ			(0x00000004)	/* PLL loss-of-lock interrupt enable */
+#define PLL_PSR_LOLRE			(0x00000008)	/* PLL loss-of-lock reset enable */
+
+/********************************************************************/
+
+#endif				/* __MCF5227X__ */
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
index 3f05651..c1669dc 100644
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@@ -1118,6 +1118,7 @@
 #define GPIO_PCLRR_LCDCTLL7		(0x80)
 
 /* Bit definitions and macros for GPIO_PAR_FEC */
+#ifdef CONFIG_M5329
 #define GPIO_PAR_FEC_MII(x)		(((x)&0x03)<<0)
 #define GPIO_PAR_FEC_7W(x)		(((x)&0x03)<<2)
 #define GPIO_PAR_FEC_7W_GPIO		(0x00)
@@ -1126,6 +1127,10 @@
 #define GPIO_PAR_FEC_MII_GPIO		(0x00)
 #define GPIO_PAR_FEC_MII_UART		(0x01)
 #define GPIO_PAR_FEC_MII_FEC		(0x03)
+#else
+#define GPIO_PAR_FEC_7W_FEC		(0x08)
+#define GPIO_PAR_FEC_MII_FEC		(0x02)
+#endif
 
 /* Bit definitions and macros for GPIO_PAR_PWM */
 #define GPIO_PAR_PWM1(x)		(((x)&0x03)<<0)
@@ -1315,168 +1320,6 @@
 /* Bit definitions and macros for GPIO_DSCR_IRQ */
 #define GPIO_DSCR_IRQ_DSE(x)		((x)&0x03)
 
-/* not done yet */
-/*********************************************************************
-* LCD Controller (LCDC)
-*********************************************************************/
-/* Bit definitions and macros for LCDC_LSSAR */
-#define LCDC_LSSAR_SSA(x)		(((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for LCDC_LSR */
-#define LCDC_LSR_YMAX(x)		(((x)&0x000003FF)<<0)
-#define LCDC_LSR_XMAX(x)		(((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for LCDC_LVPWR */
-#define LCDC_LVPWR_VPW(x)		(((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for LCDC_LCPR */
-#define LCDC_LCPR_CYP(x)		(((x)&0x000003FF)<<0)
-#define LCDC_LCPR_CXP(x)		(((x)&0x000003FF)<<16)
-#define LCDC_LCPR_OP			(0x10000000)
-#define LCDC_LCPR_CC(x)			(((x)&0x00000003)<<30)
-#define LCDC_LCPR_CC_TRANSPARENT	(0x00000000)
-#define LCDC_LCPR_CC_OR			(0x40000000)
-#define LCDC_LCPR_CC_XOR		(0x80000000)
-#define LCDC_LCPR_CC_AND		(0xC0000000)
-#define LCDC_LCPR_OP_ON			(0x10000000)
-#define LCDC_LCPR_OP_OFF		(0x00000000)
-
-/* Bit definitions and macros for LCDC_LCWHBR */
-#define LCDC_LCWHBR_BD(x)		(((x)&0x000000FF)<<0)
-#define LCDC_LCWHBR_CH(x)		(((x)&0x0000001F)<<16)
-#define LCDC_LCWHBR_CW(x)		(((x)&0x0000001F)<<24)
-#define LCDC_LCWHBR_BK_EN		(0x80000000)
-#define LCDC_LCWHBR_BK_EN_ON		(0x80000000)
-#define LCDC_LCWHBR_BK_EN_OFF		(0x00000000)
-
-/* Bit definitions and macros for LCDC_LCCMR */
-#define LCDC_LCCMR_CUR_COL_B(x)		(((x)&0x0000003F)<<0)
-#define LCDC_LCCMR_CUR_COL_G(x)		(((x)&0x0000003F)<<6)
-#define LCDC_LCCMR_CUR_COL_R(x)		(((x)&0x0000003F)<<12)
-
-/* Bit definitions and macros for LCDC_LPCR */
-#define LCDC_LPCR_PCD(x)		(((x)&0x0000003F)<<0)
-#define LCDC_LPCR_SHARP			(0x00000040)
-#define LCDC_LPCR_SCLKSEL		(0x00000080)
-#define LCDC_LPCR_ACD(x)		(((x)&0x0000007F)<<8)
-#define LCDC_LPCR_ACDSEL		(0x00008000)
-#define LCDC_LPCR_REV_VS		(0x00010000)
-#define LCDC_LPCR_SWAP_SEL		(0x00020000)
-#define LCDC_LPCR_ENDSEL		(0x00040000)
-#define LCDC_LPCR_SCLKIDLE		(0x00080000)
-#define LCDC_LPCR_OEPOL			(0x00100000)
-#define LCDC_LPCR_CLKPOL		(0x00200000)
-#define LCDC_LPCR_LPPOL			(0x00400000)
-#define LCDC_LPCR_FLM			(0x00800000)
-#define LCDC_LPCR_PIXPOL		(0x01000000)
-#define LCDC_LPCR_BPIX(x)		(((x)&0x00000007)<<25)
-#define LCDC_LPCR_PBSIZ(x)		(((x)&0x00000003)<<28)
-#define LCDC_LPCR_COLOR			(0x40000000)
-#define LCDC_LPCR_TFT			(0x80000000)
-#define LCDC_LPCR_MODE_MONOCHROME	(0x00000000)
-#define LCDC_LPCR_MODE_CSTN		(0x40000000)
-#define LCDC_LPCR_MODE_TFT		(0xC0000000)
-#define LCDC_LPCR_PBSIZ_1		(0x00000000)
-#define LCDC_LPCR_PBSIZ_2		(0x10000000)
-#define LCDC_LPCR_PBSIZ_4		(0x20000000)
-#define LCDC_LPCR_PBSIZ_8		(0x30000000)
-#define LCDC_LPCR_BPIX_1bpp		(0x00000000)
-#define LCDC_LPCR_BPIX_2bpp		(0x02000000)
-#define LCDC_LPCR_BPIX_4bpp		(0x04000000)
-#define LCDC_LPCR_BPIX_8bpp		(0x06000000)
-#define LCDC_LPCR_BPIX_12bpp		(0x08000000)
-#define LCDC_LPCR_BPIX_16bpp		(0x0A000000)
-#define LCDC_LPCR_BPIX_18bpp		(0x0C000000)
-
-#define LCDC_LPCR_PANEL_TYPE(x)		(((x)&0x00000003)<<30)
-
-/* Bit definitions and macros for LCDC_LHCR */
-#define LCDC_LHCR_H_WAIT_2(x)		(((x)&0x000000FF)<<0)
-#define LCDC_LHCR_H_WAIT_1(x)		(((x)&0x000000FF)<<8)
-#define LCDC_LHCR_H_WIDTH(x)		(((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for LCDC_LVCR */
-#define LCDC_LVCR_V_WAIT_2(x)		(((x)&0x000000FF)<<0)
-#define LCDC_LVCR_V_WAIT_1(x)		(((x)&0x000000FF)<<8)
-#define LCDC_LVCR_V_WIDTH(x)		(((x)&0x0000003F)<<26)
-
-/* Bit definitions and macros for LCDC_LPOR */
-#define LCDC_LPOR_POS(x)		(((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for LCDC_LPCCR */
-#define LCDC_LPCCR_PW(x)		(((x)&0x000000FF)<<0)
-#define LCDC_LPCCR_CC_EN		(0x00000100)
-#define LCDC_LPCCR_SCR(x)		(((x)&0x00000003)<<9)
-#define LCDC_LPCCR_LDMSK		(0x00008000)
-#define LCDC_LPCCR_CLS_HI_WIDTH(x)	(((x)&0x000001FF)<<16)
-#define LCDC_LPCCR_SCR_LINEPULSE	(0x00000000)
-#define LCDC_LPCCR_SCR_PIXELCLK		(0x00002000)
-#define LCDC_LPCCR_SCR_LCDCLOCK		(0x00004000)
-
-/* Bit definitions and macros for LCDC_LDCR */
-#define LCDC_LDCR_TM(x)			(((x)&0x0000001F)<<0)
-#define LCDC_LDCR_HM(x)			(((x)&0x0000001F)<<16)
-#define LCDC_LDCR_BURST			(0x80000000)
-
-/* Bit definitions and macros for LCDC_LRMCR */
-#define LCDC_LRMCR_SEL_REF		(0x00000001)
-
-/* Bit definitions and macros for LCDC_LICR */
-#define LCDC_LICR_INTCON		(0x00000001)
-#define LCDC_LICR_INTSYN		(0x00000004)
-#define LCDC_LICR_GW_INT_CON		(0x00000010)
-
-/* Bit definitions and macros for LCDC_LIER */
-#define LCDC_LIER_BOF_EN		(0x00000001)
-#define LCDC_LIER_EOF_EN		(0x00000002)
-#define LCDC_LIER_ERR_RES_EN		(0x00000004)
-#define LCDC_LIER_UDR_ERR_EN		(0x00000008)
-#define LCDC_LIER_GW_BOF_EN		(0x00000010)
-#define LCDC_LIER_GW_EOF_EN		(0x00000020)
-#define LCDC_LIER_GW_ERR_RES_EN		(0x00000040)
-#define LCDC_LIER_GW_UDR_ERR_EN		(0x00000080)
-
-/* Bit definitions and macros for LCDC_LISR */
-#define LCDC_LISR_BOF			(0x00000001)
-#define LCDC_LISR_EOF			(0x00000002)
-#define LCDC_LISR_ERR_RES		(0x00000004)
-#define LCDC_LISR_UDR_ERR		(0x00000008)
-#define LCDC_LISR_GW_BOF		(0x00000010)
-#define LCDC_LISR_GW_EOF		(0x00000020)
-#define LCDC_LISR_GW_ERR_RES		(0x00000040)
-#define LCDC_LISR_GW_UDR_ERR		(0x00000080)
-
-/* Bit definitions and macros for LCDC_LGWSAR */
-#define LCDC_LGWSAR_GWSA(x)		(((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for LCDC_LGWSR */
-#define LCDC_LGWSR_GWH(x)		(((x)&0x000003FF)<<0)
-#define LCDC_LGWSR_GWW(x)		(((x)&0x0000003F)<<20)
-
-/* Bit definitions and macros for LCDC_LGWVPWR */
-#define LCDC_LGWVPWR_GWVPW(x)		(((x)&0x000003FF)<<0)
-
-/* Bit definitions and macros for LCDC_LGWPOR */
-#define LCDC_LGWPOR_GWPO(x)		(((x)&0x0000001F)<<0)
-
-/* Bit definitions and macros for LCDC_LGWPR */
-#define LCDC_LGWPR_GWYP(x)		(((x)&0x000003FF)<<0)
-#define LCDC_LGWPR_GWXP(x)		(((x)&0x000003FF)<<16)
-
-/* Bit definitions and macros for LCDC_LGWCR */
-#define LCDC_LGWCR_GWCKB(x)		(((x)&0x0000003F)<<0)
-#define LCDC_LGWCR_GWCKG(x)		(((x)&0x0000003F)<<6)
-#define LCDC_LGWCR_GWCKR(x)		(((x)&0x0000003F)<<12)
-#define LCDC_LGWCR_GW_RVS		(0x00200000)
-#define LCDC_LGWCR_GWE			(0x00400000)
-#define LCDC_LGWCR_GWCKE		(0x00800000)
-#define LCDC_LGWCR_GWAV(x)		(((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for LCDC_LGWDCR */
-#define LCDC_LGWDCR_GWTM(x)		(((x)&0x0000001F)<<0)
-#define LCDC_LGWDCR_GWHM(x)		(((x)&0x0000001F)<<16)
-#define LCDC_LGWDCR_GWBT		(0x80000000)
-
 /*********************************************************************
 * SDRAM Controller (SDRAMC)
 *********************************************************************/
@@ -1541,125 +1384,6 @@
 #define SDRAMC_SDCS_CSSZ_DIABLE		(0x00000000)
 
 /*********************************************************************
-* Synchronous Serial Interface (SSI)
-*********************************************************************/
-/* Bit definitions and macros for SSI_CR */
-#define SSI_CR_CIS			(0x00000200)
-#define SSI_CR_TCH			(0x00000100)
-#define SSI_CR_MCE			(0x00000080)
-#define SSI_CR_I2S_SLAVE		(0x00000040)
-#define SSI_CR_I2S_MASTER		(0x00000020)
-#define SSI_CR_I2S_NORMAL		(0x00000000)
-#define SSI_CR_SYN			(0x00000010)
-#define SSI_CR_NET			(0x00000008)
-#define SSI_CR_RE			(0x00000004)
-#define SSI_CR_TE			(0x00000002)
-#define SSI_CR_SSI_EN			(0x00000001)
-
-/* Bit definitions and macros for SSI_ISR */
-#define SSI_ISR_CMDAU			(0x00040000)
-#define SSI_ISR_CMDDU			(0x00020000)
-#define SSI_ISR_RXT			(0x00010000)
-#define SSI_ISR_RDR1			(0x00008000)
-#define SSI_ISR_RDR0			(0x00004000)
-#define SSI_ISR_TDE1			(0x00002000)
-#define SSI_ISR_TDE0			(0x00001000)
-#define SSI_ISR_ROE1			(0x00000800)
-#define SSI_ISR_ROE0			(0x00000400)
-#define SSI_ISR_TUE1			(0x00000200)
-#define SSI_ISR_TUE0			(0x00000100)
-#define SSI_ISR_TFS			(0x00000080)
-#define SSI_ISR_RFS			(0x00000040)
-#define SSI_ISR_TLS			(0x00000020)
-#define SSI_ISR_RLS			(0x00000010)
-#define SSI_ISR_RFF1			(0x00000008)
-#define SSI_ISR_RFF0			(0x00000004)
-#define SSI_ISR_TFE1			(0x00000002)
-#define SSI_ISR_TFE0			(0x00000001)
-
-/* Bit definitions and macros for SSI_IER */
-#define SSI_IER_RDMAE			(0x00400000)
-#define SSI_IER_RIE			(0x00200000)
-#define SSI_IER_TDMAE			(0x00100000)
-#define SSI_IER_TIE			(0x00080000)
-#define SSI_IER_CMDAU			(0x00040000)
-#define SSI_IER_CMDU			(0x00020000)
-#define SSI_IER_RXT			(0x00010000)
-#define SSI_IER_RDR1			(0x00008000)
-#define SSI_IER_RDR0			(0x00004000)
-#define SSI_IER_TDE1			(0x00002000)
-#define SSI_IER_TDE0			(0x00001000)
-#define SSI_IER_ROE1			(0x00000800)
-#define SSI_IER_ROE0			(0x00000400)
-#define SSI_IER_TUE1			(0x00000200)
-#define SSI_IER_TUE0			(0x00000100)
-#define SSI_IER_TFS			(0x00000080)
-#define SSI_IER_RFS			(0x00000040)
-#define SSI_IER_TLS			(0x00000020)
-#define SSI_IER_RLS			(0x00000010)
-#define SSI_IER_RFF1			(0x00000008)
-#define SSI_IER_RFF0			(0x00000004)
-#define SSI_IER_TFE1			(0x00000002)
-#define SSI_IER_TFE0			(0x00000001)
-
-/* Bit definitions and macros for SSI_TCR */
-#define SSI_TCR_TXBIT0			(0x00000200)
-#define SSI_TCR_TFEN1			(0x00000100)
-#define SSI_TCR_TFEN0			(0x00000080)
-#define SSI_TCR_TFDIR			(0x00000040)
-#define SSI_TCR_TXDIR			(0x00000020)
-#define SSI_TCR_TSHFD			(0x00000010)
-#define SSI_TCR_TSCKP			(0x00000008)
-#define SSI_TCR_TFSI			(0x00000004)
-#define SSI_TCR_TFSL			(0x00000002)
-#define SSI_TCR_TEFS			(0x00000001)
-
-/* Bit definitions and macros for SSI_RCR */
-#define SSI_RCR_RXEXT			(0x00000400)
-#define SSI_RCR_RXBIT0			(0x00000200)
-#define SSI_RCR_RFEN1			(0x00000100)
-#define SSI_RCR_RFEN0			(0x00000080)
-#define SSI_RCR_RSHFD			(0x00000010)
-#define SSI_RCR_RSCKP			(0x00000008)
-#define SSI_RCR_RFSI			(0x00000004)
-#define SSI_RCR_RFSL			(0x00000002)
-#define SSI_RCR_REFS			(0x00000001)
-
-/* Bit definitions and macros for SSI_CCR */
-#define SSI_CCR_DIV2			(0x00040000)
-#define SSI_CCR_PSR			(0x00020000)
-#define SSI_CCR_WL(x)			(((x)&0x0000000F)<<13)
-#define SSI_CCR_DC(x)			(((x)&0x0000001F)<<8)
-#define SSI_CCR_PM(x)			((x)&0x000000FF)
-
-/* Bit definitions and macros for SSI_FCSR */
-#define SSI_FCSR_RFCNT1(x)		(((x)&0x0000000F)<<28)
-#define SSI_FCSR_TFCNT1(x)		(((x)&0x0000000F)<<24)
-#define SSI_FCSR_RFWM1(x)		(((x)&0x0000000F)<<20)
-#define SSI_FCSR_TFWM1(x)		(((x)&0x0000000F)<<16)
-#define SSI_FCSR_RFCNT0(x)		(((x)&0x0000000F)<<12)
-#define SSI_FCSR_TFCNT0(x)		(((x)&0x0000000F)<<8)
-#define SSI_FCSR_RFWM0(x)		(((x)&0x0000000F)<<4)
-#define SSI_FCSR_TFWM0(x)		((x)&0x0000000F)
-
-/* Bit definitions and macros for SSI_ACR */
-#define SSI_ACR_FRDIV(x)		(((x)&0x0000003F)<<5)
-#define SSI_ACR_WR			(0x00000010)
-#define SSI_ACR_RD			(0x00000008)
-#define SSI_ACR_TIF			(0x00000004)
-#define SSI_ACR_FV			(0x00000002)
-#define SSI_ACR_AC97EN			(0x00000001)
-
-/* Bit definitions and macros for SSI_ACADD */
-#define SSI_ACADD_SSI_ACADD(x)		((x)&0x0007FFFF)
-
-/* Bit definitions and macros for SSI_ACDAT */
-#define SSI_ACDAT_SSI_ACDAT(x)		((x)&0x0007FFFF)
-
-/* Bit definitions and macros for SSI_ATAG */
-#define SSI_ATAG_DDI_ATAG(x)		((x)&0x0000FFFF)
-
-/*********************************************************************
 * Phase Locked Loop (PLL)
 *********************************************************************/
 /* Bit definitions and macros for PLL_PODR */
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h
index b2bfb69..7fcf4ef 100644
--- a/include/asm-m68k/m5445x.h
+++ b/include/asm-m68k/m5445x.h
@@ -27,84 +27,6 @@
 #define __MCF5445X__
 
 /*********************************************************************
-* Cross-bar switch (XBS)
-*********************************************************************/
-
-/* Bit definitions and macros for PRS group */
-#define XBS_PRS_M0(x)			(((x)&0x00000007))	/* Core */
-#define XBS_PRS_M1(x)			(((x)&0x00000007)<<4)	/* eDMA */
-#define XBS_PRS_M2(x)			(((x)&0x00000007)<<8)	/* FEC0 */
-#define XBS_PRS_M3(x)			(((x)&0x00000007)<<12)	/* FEC1 */
-#define XBS_PRS_M5(x)			(((x)&0x00000007)<<20)	/* PCI controller */
-#define XBS_PRS_M6(x)			(((x)&0x00000007)<<24)	/* USB OTG */
-#define XBS_PRS_M7(x)			(((x)&0x00000007)<<28)	/* Serial Boot */
-
-/* Bit definitions and macros for CRS group */
-#define XBS_CRS_PARK(x)			(((x)&0x00000007))	/* Master parking ctrl */
-#define XBS_CRS_PCTL(x)			(((x)&0x00000003)<<4)	/* Parking mode ctrl */
-#define XBS_CRS_ARB			(0x00000100)	/* Arbitration Mode */
-#define XBS_CRS_RO			(0x80000000)	/* Read Only */
-
-#define XBS_CRS_PCTL_PARK_FIELD		(0)
-#define XBS_CRS_PCTL_PARK_ON_LAST	(1)
-#define XBS_CRS_PCTL_PARK_NONE		(2)
-#define XBS_CRS_PCTL_PARK_CORE		(0)
-#define XBS_CRS_PCTL_PARK_EDMA		(1)
-#define XBS_CRS_PCTL_PARK_FEC0		(2)
-#define XBS_CRS_PCTL_PARK_FEC1		(3)
-#define XBS_CRS_PCTL_PARK_PCI		(5)
-#define XBS_CRS_PCTL_PARK_USB		(6)
-#define XBS_CRS_PCTL_PARK_SBF		(7)
-
-/*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-
-/* Bit definitions and macros for CSAR group */
-#define FBCS_CSAR_BA(x)			((x)&0xFFFF0000)
-
-/* Bit definitions and macros for CSMR group */
-#define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
-#define FBCS_CSMR_WP			(0x00000100)	/* Write protect */
-#define FBCS_CSMR_BAM(x)		(((x)&0x0000FFFF)<<16)	/* Base address mask */
-#define FBCS_CSMR_BAM_4G		(0xFFFF0000)
-#define FBCS_CSMR_BAM_2G		(0x7FFF0000)
-#define FBCS_CSMR_BAM_1G		(0x3FFF0000)
-#define FBCS_CSMR_BAM_1024M		(0x3FFF0000)
-#define FBCS_CSMR_BAM_512M		(0x1FFF0000)
-#define FBCS_CSMR_BAM_256M		(0x0FFF0000)
-#define FBCS_CSMR_BAM_128M		(0x07FF0000)
-#define FBCS_CSMR_BAM_64M		(0x03FF0000)
-#define FBCS_CSMR_BAM_32M		(0x01FF0000)
-#define FBCS_CSMR_BAM_16M		(0x00FF0000)
-#define FBCS_CSMR_BAM_8M		(0x007F0000)
-#define FBCS_CSMR_BAM_4M		(0x003F0000)
-#define FBCS_CSMR_BAM_2M		(0x001F0000)
-#define FBCS_CSMR_BAM_1M		(0x000F0000)
-#define FBCS_CSMR_BAM_1024K		(0x000F0000)
-#define FBCS_CSMR_BAM_512K		(0x00070000)
-#define FBCS_CSMR_BAM_256K		(0x00030000)
-#define FBCS_CSMR_BAM_128K		(0x00010000)
-#define FBCS_CSMR_BAM_64K		(0x00000000)
-
-/* Bit definitions and macros for CSCR group */
-#define FBCS_CSCR_BSTW			(0x00000008)	/* Burst-write enable */
-#define FBCS_CSCR_BSTR			(0x00000010)	/* Burst-read enable */
-#define FBCS_CSCR_BEM			(0x00000020)	/* Byte-enable mode */
-#define FBCS_CSCR_PS(x)			(((x)&0x00000003)<<6)	/* Port size */
-#define FBCS_CSCR_AA			(0x00000100)	/* Auto-acknowledge */
-#define FBCS_CSCR_WS(x)			(((x)&0x0000003F)<<10)	/* Wait states */
-#define FBCS_CSCR_WRAH(x)		(((x)&0x00000003)<<16)	/* Write address hold or deselect */
-#define FBCS_CSCR_RDAH(x)		(((x)&0x00000003)<<18)	/* Read address hold or deselect */
-#define FBCS_CSCR_ASET(x)		(((x)&0x00000003)<<20)	/* Address setup */
-#define FBCS_CSCR_SWSEN			(0x00800000)	/* Secondary wait state enable */
-#define FBCS_CSCR_SWS(x)		(((x)&0x0000003F)<<26)	/* Secondary wait states */
-
-#define FBCS_CSCR_PS_8			(0x00000040)
-#define FBCS_CSCR_PS_16			(0x00000080)
-#define FBCS_CSCR_PS_32			(0x00000000)
-
-/*********************************************************************
 * Interrupt Controller (INTC)
 *********************************************************************/
 #define INT0_LO_RSVD0			(0)
@@ -422,106 +344,6 @@
 #define INTC_ICR_IL(x)			(((x)&0x07))
 
 /*********************************************************************
-* DMA Serial Peripheral Interface (DSPI)
-*********************************************************************/
-
-/* Bit definitions and macros for DMCR */
-#define DSPI_DMCR_HALT			(0x00000001)
-#define DSPI_DMCR_SMPL_PT(x)		(((x)&0x00000003)<<8)
-#define DSPI_DMCR_CRXF			(0x00000400)
-#define DSPI_DMCR_CTXF			(0x00000800)
-#define DSPI_DMCR_DRXF			(0x00001000)
-#define DSPI_DMCR_DTXF			(0x00002000)
-#define DSPI_DMCR_CSIS0			(0x00010000)
-#define DSPI_DMCR_CSIS2			(0x00040000)
-#define DSPI_DMCR_CSIS3			(0x00080000)
-#define DSPI_DMCR_CSIS5			(0x00200000)
-#define DSPI_DMCR_ROOE			(0x01000000)
-#define DSPI_DMCR_PCSSE			(0x02000000)
-#define DSPI_DMCR_MTFE			(0x04000000)
-#define DSPI_DMCR_FRZ			(0x08000000)
-#define DSPI_DMCR_DCONF(x)		(((x)&0x00000003)<<28)
-#define DSPI_DMCR_CSCK			(0x40000000)
-#define DSPI_DMCR_MSTR			(0x80000000)
-
-/* Bit definitions and macros for DTCR */
-#define DSPI_DTCR_SPI_TCNT(x)		(((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for DCTAR group */
-#define DSPI_DCTAR_BR(x)		(((x)&0x0000000F))
-#define DSPI_DCTAR_DT(x)		(((x)&0x0000000F)<<4)
-#define DSPI_DCTAR_ASC(x)		(((x)&0x0000000F)<<8)
-#define DSPI_DCTAR_CSSCK(x)		(((x)&0x0000000F)<<12)
-#define DSPI_DCTAR_PBR(x)		(((x)&0x00000003)<<16)
-#define DSPI_DCTAR_PDT(x)		(((x)&0x00000003)<<18)
-#define DSPI_DCTAR_PASC(x)		(((x)&0x00000003)<<20)
-#define DSPI_DCTAR_PCSSCK(x)		(((x)&0x00000003)<<22)
-#define DSPI_DCTAR_LSBFE		(0x01000000)
-#define DSPI_DCTAR_CPHA			(0x02000000)
-#define DSPI_DCTAR_CPOL			(0x04000000)
-#define DSPI_DCTAR_TRSZ(x)		(((x)&0x0000000F)<<27)
-#define DSPI_DCTAR_PCSSCK_1CLK		(0x00000000)
-#define DSPI_DCTAR_PCSSCK_3CLK		(0x00400000)
-#define DSPI_DCTAR_PCSSCK_5CLK		(0x00800000)
-#define DSPI_DCTAR_PCSSCK_7CLK		(0x00A00000)
-#define DSPI_DCTAR_PASC_1CLK		(0x00000000)
-#define DSPI_DCTAR_PASC_3CLK		(0x00100000)
-#define DSPI_DCTAR_PASC_5CLK		(0x00200000)
-#define DSPI_DCTAR_PASC_7CLK		(0x00300000)
-#define DSPI_DCTAR_PDT_1CLK		(0x00000000)
-#define DSPI_DCTAR_PDT_3CLK		(0x00040000)
-#define DSPI_DCTAR_PDT_5CLK		(0x00080000)
-#define DSPI_DCTAR_PDT_7CLK		(0x000A0000)
-#define DSPI_DCTAR_PBR_1CLK		(0x00000000)
-#define DSPI_DCTAR_PBR_3CLK		(0x00010000)
-#define DSPI_DCTAR_PBR_5CLK		(0x00020000)
-#define DSPI_DCTAR_PBR_7CLK		(0x00030000)
-
-/* Bit definitions and macros for DSR */
-#define DSPI_DSR_RXPTR(x)		(((x)&0x0000000F))
-#define DSPI_DSR_RXCTR(x)		(((x)&0x0000000F)<<4)
-#define DSPI_DSR_TXPTR(x)		(((x)&0x0000000F)<<8)
-#define DSPI_DSR_TXCTR(x)		(((x)&0x0000000F)<<12)
-#define DSPI_DSR_RFDF			(0x00020000)
-#define DSPI_DSR_RFOF			(0x00080000)
-#define DSPI_DSR_TFFF			(0x02000000)
-#define DSPI_DSR_TFUF			(0x08000000)
-#define DSPI_DSR_EOQF			(0x10000000)
-#define DSPI_DSR_TXRXS			(0x40000000)
-#define DSPI_DSR_TCF			(0x80000000)
-
-/* Bit definitions and macros for DIRSR */
-#define DSPI_DIRSR_RFDFS		(0x00010000)
-#define DSPI_DIRSR_RFDFE		(0x00020000)
-#define DSPI_DIRSR_RFOFE		(0x00080000)
-#define DSPI_DIRSR_TFFFS		(0x01000000)
-#define DSPI_DIRSR_TFFFE		(0x02000000)
-#define DSPI_DIRSR_TFUFE		(0x08000000)
-#define DSPI_DIRSR_EOQFE		(0x10000000)
-#define DSPI_DIRSR_TCFE			(0x80000000)
-
-/* Bit definitions and macros for DTFR */
-#define DSPI_DTFR_TXDATA(x)		(((x)&0x0000FFFF))
-#define DSPI_DTFR_CS0			(0x00010000)
-#define DSPI_DTFR_CS2			(0x00040000)
-#define DSPI_DTFR_CS3			(0x00080000)
-#define DSPI_DTFR_CS5			(0x00200000)
-#define DSPI_DTFR_CTCNT			(0x04000000)
-#define DSPI_DTFR_EOQ			(0x08000000)
-#define DSPI_DTFR_CTAS(x)		(((x)&0x00000007)<<28)
-#define DSPI_DTFR_CONT			(0x80000000)
-
-/* Bit definitions and macros for DRFR */
-#define DSPI_DRFR_RXDATA(x)		(((x)&0x0000FFFF))
-
-/* Bit definitions and macros for DTFDR group */
-#define DSPI_DTFDR_TXDATA(x)		(((x)&0x0000FFFF))
-#define DSPI_DTFDR_TXCMD(x)		(((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for DRFDR group */
-#define DSPI_DRFDR_RXDATA(x)		(((x)&0x0000FFFF))
-
-/*********************************************************************
 * Edge Port Module (EPORT)
 *********************************************************************/
 
@@ -1298,127 +1120,6 @@
 #define SDRAMC_SDCS_CSSZ_4GBYTE		(0x0000001F)
 
 /*********************************************************************
-* Synchronous Serial Interface (SSI)
-*********************************************************************/
-
-/* Bit definitions and macros for CR */
-#define SSI_CR_SSI_EN			(0x00000001)
-#define SSI_CR_TE			(0x00000002)
-#define SSI_CR_RE			(0x00000004)
-#define SSI_CR_NET			(0x00000008)
-#define SSI_CR_SYN			(0x00000010)
-#define SSI_CR_I2S(x)			(((x)&0x00000003)<<5)
-#define SSI_CR_MCE			(0x00000080)
-#define SSI_CR_TCH			(0x00000100)
-#define SSI_CR_CIS			(0x00000200)
-#define SSI_CR_I2S_NORMAL		(0x00000000)
-#define SSI_CR_I2S_MASTER		(0x00000020)
-#define SSI_CR_I2S_SLAVE		(0x00000040)
-
-/* Bit definitions and macros for ISR */
-#define SSI_ISR_TFE0			(0x00000001)
-#define SSI_ISR_TFE1			(0x00000002)
-#define SSI_ISR_RFF0			(0x00000004)
-#define SSI_ISR_RFF1			(0x00000008)
-#define SSI_ISR_RLS			(0x00000010)
-#define SSI_ISR_TLS			(0x00000020)
-#define SSI_ISR_RFS			(0x00000040)
-#define SSI_ISR_TFS			(0x00000080)
-#define SSI_ISR_TUE0			(0x00000100)
-#define SSI_ISR_TUE1			(0x00000200)
-#define SSI_ISR_ROE0			(0x00000400)
-#define SSI_ISR_ROE1			(0x00000800)
-#define SSI_ISR_TDE0			(0x00001000)
-#define SSI_ISR_TDE1			(0x00002000)
-#define SSI_ISR_RDR0			(0x00004000)
-#define SSI_ISR_RDR1			(0x00008000)
-#define SSI_ISR_RXT			(0x00010000)
-#define SSI_ISR_CMDDU			(0x00020000)
-#define SSI_ISR_CMDAU			(0x00040000)
-
-/* Bit definitions and macros for IER */
-#define SSI_IER_TFE0			(0x00000001)
-#define SSI_IER_TFE1			(0x00000002)
-#define SSI_IER_RFF0			(0x00000004)
-#define SSI_IER_RFF1			(0x00000008)
-#define SSI_IER_RLS			(0x00000010)
-#define SSI_IER_TLS			(0x00000020)
-#define SSI_IER_RFS			(0x00000040)
-#define SSI_IER_TFS			(0x00000080)
-#define SSI_IER_TUE0			(0x00000100)
-#define SSI_IER_TUE1			(0x00000200)
-#define SSI_IER_ROE0			(0x00000400)
-#define SSI_IER_ROE1			(0x00000800)
-#define SSI_IER_TDE0			(0x00001000)
-#define SSI_IER_TDE1			(0x00002000)
-#define SSI_IER_RDR0			(0x00004000)
-#define SSI_IER_RDR1			(0x00008000)
-#define SSI_IER_RXT			(0x00010000)
-#define SSI_IER_CMDU			(0x00020000)
-#define SSI_IER_CMDAU			(0x00040000)
-#define SSI_IER_TIE			(0x00080000)
-#define SSI_IER_TDMAE			(0x00100000)
-#define SSI_IER_RIE			(0x00200000)
-#define SSI_IER_RDMAE			(0x00400000)
-
-/* Bit definitions and macros for TCR */
-#define SSI_TCR_TEFS			(0x00000001)
-#define SSI_TCR_TFSL			(0x00000002)
-#define SSI_TCR_TFSI			(0x00000004)
-#define SSI_TCR_TSCKP			(0x00000008)
-#define SSI_TCR_TSHFD			(0x00000010)
-#define SSI_TCR_TXDIR			(0x00000020)
-#define SSI_TCR_TFDIR			(0x00000040)
-#define SSI_TCR_TFEN0			(0x00000080)
-#define SSI_TCR_TFEN1			(0x00000100)
-#define SSI_TCR_TXBIT0			(0x00000200)
-
-/* Bit definitions and macros for RCR */
-#define SSI_RCR_REFS			(0x00000001)
-#define SSI_RCR_RFSL			(0x00000002)
-#define SSI_RCR_RFSI			(0x00000004)
-#define SSI_RCR_RSCKP			(0x00000008)
-#define SSI_RCR_RSHFD			(0x00000010)
-#define SSI_RCR_RFEN0			(0x00000080)
-#define SSI_RCR_RFEN1			(0x00000100)
-#define SSI_RCR_RXBIT0			(0x00000200)
-#define SSI_RCR_RXEXT			(0x00000400)
-
-/* Bit definitions and macros for CCR */
-#define SSI_CCR_PM(x)			(((x)&0x000000FF))
-#define SSI_CCR_DC(x)			(((x)&0x0000001F)<<8)
-#define SSI_CCR_WL(x)			(((x)&0x0000000F)<<13)
-#define SSI_CCR_PSR			(0x00020000)
-#define SSI_CCR_DIV2			(0x00040000)
-
-/* Bit definitions and macros for FCSR */
-#define SSI_FCSR_TFWM0(x)		(((x)&0x0000000F))
-#define SSI_FCSR_RFWM0(x)		(((x)&0x0000000F)<<4)
-#define SSI_FCSR_TFCNT0(x)		(((x)&0x0000000F)<<8)
-#define SSI_FCSR_RFCNT0(x)		(((x)&0x0000000F)<<12)
-#define SSI_FCSR_TFWM1(x)		(((x)&0x0000000F)<<16)
-#define SSI_FCSR_RFWM1(x)		(((x)&0x0000000F)<<20)
-#define SSI_FCSR_TFCNT1(x)		(((x)&0x0000000F)<<24)
-#define SSI_FCSR_RFCNT1(x)		(((x)&0x0000000F)<<28)
-
-/* Bit definitions and macros for ACR */
-#define SSI_ACR_AC97EN			(0x00000001)
-#define SSI_ACR_FV			(0x00000002)
-#define SSI_ACR_TIF			(0x00000004)
-#define SSI_ACR_RD			(0x00000008)
-#define SSI_ACR_WR			(0x00000010)
-#define SSI_ACR_FRDIV(x)		(((x)&0x0000003F)<<5)
-
-/* Bit definitions and macros for ACADD */
-#define SSI_ACADD_SSI_ACADD(x)		(((x)&0x0007FFFF))
-
-/* Bit definitions and macros for ACDAT */
-#define SSI_ACDAT_SSI_ACDAT(x)		(((x)&0x0007FFFF))
-
-/* Bit definitions and macros for ATAG */
-#define SSI_ATAG_DDI_ATAG(x)		(((x)&0x0000FFFF))
-
-/*********************************************************************
 * Phase Locked Loop (PLL)
 *********************************************************************/
 
@@ -1503,13 +1204,13 @@
 #define PCI_TCR1_P			(0x00010000)	/* Prefetch reads */
 #define PCI_TCR1_WCD			(0x00000100)	/* Write combine disable */
 
-#define PCI_TCR1_B5E			(0x00002000)	/*  */
-#define PCI_TCR1_B4E			(0x00001000)	/*  */
-#define PCI_TCR1_B3E			(0x00000800)	/*  */
-#define PCI_TCR1_B2E			(0x00000400)	/*  */
-#define PCI_TCR1_B1E			(0x00000200)	/*  */
-#define PCI_TCR1_B0E			(0x00000100)	/*  */
-#define PCI_TCR1_CR			(0x00000001)	/*  */
+#define PCI_TCR2_B5E			(0x00002000)	/*  */
+#define PCI_TCR2_B4E			(0x00001000)	/*  */
+#define PCI_TCR2_B3E			(0x00000800)	/*  */
+#define PCI_TCR2_B2E			(0x00000400)	/*  */
+#define PCI_TCR2_B1E			(0x00000200)	/*  */
+#define PCI_TCR2_B0E			(0x00000100)	/*  */
+#define PCI_TCR2_CR			(0x00000001)	/*  */
 
 #define PCI_TBATR_BAT(x)		((x & 0xFFF) << 20)
 #define PCI_TBATR_EN			(0x00000001)	/* Enable */
@@ -1533,8 +1234,7 @@
 #define PCI_ICR_REE			(0x04000000)	/* Retry error enable */
 #define PCI_ICR_IAE			(0x02000000)	/* Initiator abort enable */
 #define PCI_ICR_TAE			(0x01000000)	/* Target abort enable */
-
-#define PCI_IDR_DEVID			(
+#define PCI_ICR_MAXRETRY(x)		((x) & 0x000000FF)
 
 /********************************************************************/
 
diff --git a/include/asm-m68k/m547x_8x.h b/include/asm-m68k/m547x_8x.h
new file mode 100644
index 0000000..2db8df2
--- /dev/null
+++ b/include/asm-m68k/m547x_8x.h
@@ -0,0 +1,502 @@
+/*
+ * mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef mcf547x_8x_h
+#define mcf547x_8x_h
+
+/*********************************************************************
+* XLB Arbiter (XLB)
+*********************************************************************/
+/* Bit definitions and macros for XARB_CFG */
+#define XARB_CFG_AT			(0x00000002)
+#define XARB_CFG_DT			(0x00000004)
+#define XARB_CFG_BA			(0x00000008)
+#define XARB_CFG_PM(x)			(((x)&0x00000003)<<5)
+#define XARB_CFG_SP(x)			(((x)&0x00000007)<<8)
+#define XARB_CFG_PLDIS			(0x80000000)
+
+/* Bit definitions and macros for XARB_SR */
+#define XARB_SR_AT			(0x00000001)
+#define XARB_SR_DT			(0x00000002)
+#define XARB_SR_BA			(0x00000004)
+#define XARB_SR_TTM			(0x00000008)
+#define XARB_SR_ECW			(0x00000010)
+#define XARB_SR_TTR			(0x00000020)
+#define XARB_SR_TTA			(0x00000040)
+#define XARB_SR_MM			(0x00000080)
+#define XARB_SR_SEA			(0x00000100)
+
+/* Bit definitions and macros for XARB_IMR */
+#define XARB_IMR_ATE			(0x00000001)
+#define XARB_IMR_DTE			(0x00000002)
+#define XARB_IMR_BAE			(0x00000004)
+#define XARB_IMR_TTME			(0x00000008)
+#define XARB_IMR_ECWE			(0x00000010)
+#define XARB_IMR_TTRE			(0x00000020)
+#define XARB_IMR_TTAE			(0x00000040)
+#define XARB_IMR_MME			(0x00000080)
+#define XARB_IMR_SEAE			(0x00000100)
+
+/* Bit definitions and macros for XARB_SIGCAP */
+#define XARB_SIGCAP_TT(x)		((x)&0x0000001F)
+#define XARB_SIGCAP_TBST		(0x00000020)
+#define XARB_SIGCAP_TSIZ(x)		(((x)&0x00000007)<<7)
+
+/* Bit definitions and macros for XARB_PRIEN */
+#define XARB_PRIEN_M0			(0x00000001)
+#define XARB_PRIEN_M2			(0x00000004)
+#define XARB_PRIEN_M3			(0x00000008)
+
+/* Bit definitions and macros for XARB_PRI */
+#define XARB_PRI_M0P(x)			(((x)&0x00000007)<<0)
+#define XARB_PRI_M2P(x)			(((x)&0x00000007)<<8)
+#define XARB_PRI_M3P(x)			(((x)&0x00000007)<<12)
+
+/*********************************************************************
+* General Purpose I/O (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for GPIO_PAR_FBCTL */
+#define GPIO_PAR_FBCTL_TS(x)		(((x)&0x0003)<<0)
+#define GPIO_PAR_FBCTL_TA		(0x0004)
+#define GPIO_PAR_FBCTL_RWB(x)		(((x)&0x0003)<<4)
+#define GPIO_PAR_FBCTL_OE		(0x0040)
+#define GPIO_PAR_FBCTL_BWE0		(0x0100)
+#define GPIO_PAR_FBCTL_BWE1		(0x0400)
+#define GPIO_PAR_FBCTL_BWE2		(0x1000)
+#define GPIO_PAR_FBCTL_BWE3		(0x4000)
+#define GPIO_PAR_FBCTL_TS_GPIO		(0)
+#define GPIO_PAR_FBCTL_TS_TBST		(2)
+#define GPIO_PAR_FBCTL_TS_TS		(3)
+#define GPIO_PAR_FBCTL_RWB_GPIO		(0x0000)
+#define GPIO_PAR_FBCTL_RWB_TBST		(0x0020)
+#define GPIO_PAR_FBCTL_RWB_RWB		(0x0030)
+
+/* Bit definitions and macros for GPIO_PAR_FBCS */
+#define GPIO_PAR_FBCS_CS1		(0x02)
+#define GPIO_PAR_FBCS_CS2		(0x04)
+#define GPIO_PAR_FBCS_CS3		(0x08)
+#define GPIO_PAR_FBCS_CS4		(0x10)
+#define GPIO_PAR_FBCS_CS5		(0x20)
+
+/* Bit definitions and macros for GPIO_PAR_DMA */
+#define GPIO_PAR_DMA_DREQ0(x)		(((x)&0x03)<<0)
+#define GPIO_PAR_DMA_DREQ1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_DMA_DACK0(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_DMA_DACK1(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_DMA_DACKx_GPIO		(0)
+#define GPIO_PAR_DMA_DACKx_TOUT		(2)
+#define GPIO_PAR_DMA_DACKx_DACK		(3)
+#define GPIO_PAR_DMA_DREQx_GPIO		(0)
+#define GPIO_PAR_DMA_DREQx_TIN		(2)
+#define GPIO_PAR_DMA_DREQx_DREQ		(3)
+
+/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
+#define GPIO_PAR_FECI2CIRQ_IRQ5		(0x0001)
+#define GPIO_PAR_FECI2CIRQ_IRQ6		(0x0002)
+#define GPIO_PAR_FECI2CIRQ_SCL		(0x0004)
+#define GPIO_PAR_FECI2CIRQ_SDA		(0x0008)
+#define GPIO_PAR_FECI2CIRQ_E1MDC(x)	(((x)&0x0003)<<6)
+#define GPIO_PAR_FECI2CIRQ_E1MDIO(x)	(((x)&0x0003)<<8)
+#define GPIO_PAR_FECI2CIRQ_E1MII	(0x0400)
+#define GPIO_PAR_FECI2CIRQ_E17		(0x0800)
+#define GPIO_PAR_FECI2CIRQ_E0MDC	(0x1000)
+#define GPIO_PAR_FECI2CIRQ_E0MDIO	(0x2000)
+#define GPIO_PAR_FECI2CIRQ_E0MII	(0x4000)
+#define GPIO_PAR_FECI2CIRQ_E07		(0x8000)
+#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX	(0x0000)
+#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA	(0x0200)
+#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO	(0x0300)
+#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX	(0x0000)
+#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL	(0x0080)
+#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC	(0x00C0)
+
+/* Bit definitions and macros for GPIO_PAR_PCIBG */
+#define GPIO_PAR_PCIBG_PCIBG0(x)	(((x)&0x0003)<<0)
+#define GPIO_PAR_PCIBG_PCIBG1(x)	(((x)&0x0003)<<2)
+#define GPIO_PAR_PCIBG_PCIBG2(x)	(((x)&0x0003)<<4)
+#define GPIO_PAR_PCIBG_PCIBG3(x)	(((x)&0x0003)<<6)
+#define GPIO_PAR_PCIBG_PCIBG4(x)	(((x)&0x0003)<<8)
+
+/* Bit definitions and macros for GPIO_PAR_PCIBR */
+#define GPIO_PAR_PCIBR_PCIBR0(x)	(((x)&0x0003)<<0)
+#define GPIO_PAR_PCIBR_PCIBR1(x)	(((x)&0x0003)<<2)
+#define GPIO_PAR_PCIBR_PCIBR2(x)	(((x)&0x0003)<<4)
+#define GPIO_PAR_PCIBR_PCIBR3(x)	(((x)&0x0003)<<6)
+#define GPIO_PAR_PCIBR_PCIBR4(x)	(((x)&0x0003)<<8)
+
+/* Bit definitions and macros for GPIO_PAR_PSC3 */
+#define GPIO_PAR_PSC3_TXD3		(0x04)
+#define GPIO_PAR_PSC3_RXD3		(0x08)
+#define GPIO_PAR_PSC3_RTS3(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_PSC3_CTS3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_PSC3_CTS3_GPIO		(0x00)
+#define GPIO_PAR_PSC3_CTS3_BCLK		(0x80)
+#define GPIO_PAR_PSC3_CTS3_CTS		(0xC0)
+#define GPIO_PAR_PSC3_RTS3_GPIO		(0x00)
+#define GPIO_PAR_PSC3_RTS3_FSYNC	(0x20)
+#define GPIO_PAR_PSC3_RTS3_RTS		(0x30)
+#define GPIO_PAR_PSC3_CTS2_CANRX	(0x40)
+
+/* Bit definitions and macros for GPIO_PAR_PSC2 */
+#define GPIO_PAR_PSC2_TXD2		(0x04)
+#define GPIO_PAR_PSC2_RXD2		(0x08)
+#define GPIO_PAR_PSC2_RTS2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_PSC2_CTS2(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_PSC2_CTS2_GPIO		(0x00)
+#define GPIO_PAR_PSC2_CTS2_BCLK		(0x80)
+#define GPIO_PAR_PSC2_CTS2_CTS		(0xC0)
+#define GPIO_PAR_PSC2_RTS2_GPIO		(0x00)
+#define GPIO_PAR_PSC2_RTS2_CANTX	(0x10)
+#define GPIO_PAR_PSC2_RTS2_FSYNC	(0x20)
+#define GPIO_PAR_PSC2_RTS2_RTS		(0x30)
+
+/* Bit definitions and macros for GPIO_PAR_PSC1 */
+#define GPIO_PAR_PSC1_TXD1		(0x04)
+#define GPIO_PAR_PSC1_RXD1		(0x08)
+#define GPIO_PAR_PSC1_RTS1(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_PSC1_CTS1(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_PSC1_CTS1_GPIO		(0x00)
+#define GPIO_PAR_PSC1_CTS1_BCLK		(0x80)
+#define GPIO_PAR_PSC1_CTS1_CTS		(0xC0)
+#define GPIO_PAR_PSC1_RTS1_GPIO		(0x00)
+#define GPIO_PAR_PSC1_RTS1_FSYNC	(0x20)
+#define GPIO_PAR_PSC1_RTS1_RTS		(0x30)
+
+/* Bit definitions and macros for GPIO_PAR_PSC0 */
+#define GPIO_PAR_PSC0_TXD0		(0x04)
+#define GPIO_PAR_PSC0_RXD0		(0x08)
+#define GPIO_PAR_PSC0_RTS0(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_PSC0_CTS0(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_PSC0_CTS0_GPIO		(0x00)
+#define GPIO_PAR_PSC0_CTS0_BCLK		(0x80)
+#define GPIO_PAR_PSC0_CTS0_CTS		(0xC0)
+#define GPIO_PAR_PSC0_RTS0_GPIO		(0x00)
+#define GPIO_PAR_PSC0_RTS0_FSYNC	(0x20)
+#define GPIO_PAR_PSC0_RTS0_RTS		(0x30)
+
+/* Bit definitions and macros for GPIO_PAR_DSPI */
+#define GPIO_PAR_DSPI_SOUT(x)		(((x)&0x0003)<<0)
+#define GPIO_PAR_DSPI_SIN(x)		(((x)&0x0003)<<2)
+#define GPIO_PAR_DSPI_SCK(x)		(((x)&0x0003)<<4)
+#define GPIO_PAR_DSPI_CS0(x)		(((x)&0x0003)<<6)
+#define GPIO_PAR_DSPI_CS2(x)		(((x)&0x0003)<<8)
+#define GPIO_PAR_DSPI_CS3(x)		(((x)&0x0003)<<10)
+#define GPIO_PAR_DSPI_CS5		(0x1000)
+#define GPIO_PAR_DSPI_CS3_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_CS3_CANTX		(0x0400)
+#define GPIO_PAR_DSPI_CS3_TOUT		(0x0800)
+#define GPIO_PAR_DSPI_CS3_DSPICS	(0x0C00)
+#define GPIO_PAR_DSPI_CS2_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_CS2_CANTX		(0x0100)
+#define GPIO_PAR_DSPI_CS2_TOUT		(0x0200)
+#define GPIO_PAR_DSPI_CS2_DSPICS	(0x0300)
+#define GPIO_PAR_DSPI_CS0_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_CS0_FSYNC		(0x0040)
+#define GPIO_PAR_DSPI_CS0_RTS		(0x0080)
+#define GPIO_PAR_DSPI_CS0_DSPICS	(0x00C0)
+#define GPIO_PAR_DSPI_SCK_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_SCK_BCLK		(0x0010)
+#define GPIO_PAR_DSPI_SCK_CTS		(0x0020)
+#define GPIO_PAR_DSPI_SCK_SCK		(0x0030)
+#define GPIO_PAR_DSPI_SIN_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_SIN_RXD		(0x0008)
+#define GPIO_PAR_DSPI_SIN_SIN		(0x000C)
+#define GPIO_PAR_DSPI_SOUT_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_SOUT_TXD		(0x0002)
+#define GPIO_PAR_DSPI_SOUT_SOUT		(0x0003)
+
+/* Bit definitions and macros for GPIO_PAR_TIMER */
+#define GPIO_PAR_TIMER_TOUT2		(0x01)
+#define GPIO_PAR_TIMER_TIN2(x)		(((x)&0x03)<<1)
+#define GPIO_PAR_TIMER_TOUT3		(0x08)
+#define GPIO_PAR_TIMER_TIN3(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_TIN3_CANRX	(0x00)
+#define GPIO_PAR_TIMER_TIN3_IRQ		(0x20)
+#define GPIO_PAR_TIMER_TIN3_TIN		(0x30)
+#define GPIO_PAR_TIMER_TIN2_CANRX	(0x00)
+#define GPIO_PAR_TIMER_TIN2_IRQ		(0x04)
+#define GPIO_PAR_TIMER_TIN2_TIN		(0x06)
+
+/*********************************************************************
+* Slice Timer (SLT)
+*********************************************************************/
+#define SLT_CR_RUN			(0x04000000)
+#define SLT_CR_IEN			(0x02000000)
+#define SLT_CR_TEN			(0x01000000)
+
+#define SLT_SR_BE			(0x02000000)
+#define SLT_SR_ST			(0x01000000)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EP0ISR			(15)
+#define INT0_LO_EP1ISR			(16)
+#define INT0_LO_EP2ISR			(17)
+#define INT0_LO_EP3ISR			(18)
+#define INT0_LO_EP4ISR			(19)
+#define INT0_LO_EP5ISR			(20)
+#define INT0_LO_EP6ISR			(21)
+#define INT0_LO_USBISR			(22)
+#define INT0_LO_USBAISR			(23)
+#define INT0_LO_USB			(24)
+#define INT1_LO_DSPI_RFOF_TFUF		(25)
+#define INT1_LO_DSPI_RFOF		(26)
+#define INT1_LO_DSPI_RFDF		(27)
+#define INT1_LO_DSPI_TFUF		(28)
+#define INT1_LO_DSPI_TCF		(29)
+#define INT1_LO_DSPI_TFFF		(30)
+#define INT1_LO_DSPI_EOQF		(31)
+
+#define INT0_HI_UART3			(32)
+#define INT0_HI_UART2			(33)
+#define INT0_HI_UART1			(34)
+#define INT0_HI_UART0			(35)
+#define INT0_HI_COMMTIM_TC		(36)
+#define INT0_HI_SEC			(37)
+#define INT0_HI_FEC1			(38)
+#define INT0_HI_FEC0			(39)
+#define INT0_HI_I2C			(40)
+#define INT0_HI_PCIARB			(41)
+#define INT0_HI_CBPCI			(42)
+#define INT0_HI_XLBPCI			(43)
+#define INT0_HI_XLBARB			(47)
+#define INT0_HI_DMA			(48)
+#define INT0_HI_CAN0_ERROR		(49)
+#define INT0_HI_CAN0_BUSOFF		(50)
+#define INT0_HI_CAN0_MBOR		(51)
+#define INT0_HI_SLT1			(53)
+#define INT0_HI_SLT0			(54)
+#define INT0_HI_CAN1_ERROR		(55)
+#define INT0_HI_CAN1_BUSOFF		(56)
+#define INT0_HI_CAN1_MBOR		(57)
+#define INT0_HI_GPT3			(59)
+#define INT0_HI_GPT2			(60)
+#define INT0_HI_GPT1			(61)
+#define INT0_HI_GPT0			(62)
+
+/* Bit definitions and macros for IPRH */
+#define INTC_IPRH_INT32			(0x00000001)
+#define INTC_IPRH_INT33			(0x00000002)
+#define INTC_IPRH_INT34			(0x00000004)
+#define INTC_IPRH_INT35			(0x00000008)
+#define INTC_IPRH_INT36			(0x00000010)
+#define INTC_IPRH_INT37			(0x00000020)
+#define INTC_IPRH_INT38			(0x00000040)
+#define INTC_IPRH_INT39			(0x00000080)
+#define INTC_IPRH_INT40			(0x00000100)
+#define INTC_IPRH_INT41			(0x00000200)
+#define INTC_IPRH_INT42			(0x00000400)
+#define INTC_IPRH_INT43			(0x00000800)
+#define INTC_IPRH_INT44			(0x00001000)
+#define INTC_IPRH_INT45			(0x00002000)
+#define INTC_IPRH_INT46			(0x00004000)
+#define INTC_IPRH_INT47			(0x00008000)
+#define INTC_IPRH_INT48			(0x00010000)
+#define INTC_IPRH_INT49			(0x00020000)
+#define INTC_IPRH_INT50			(0x00040000)
+#define INTC_IPRH_INT51			(0x00080000)
+#define INTC_IPRH_INT52			(0x00100000)
+#define INTC_IPRH_INT53			(0x00200000)
+#define INTC_IPRH_INT54			(0x00400000)
+#define INTC_IPRH_INT55			(0x00800000)
+#define INTC_IPRH_INT56			(0x01000000)
+#define INTC_IPRH_INT57			(0x02000000)
+#define INTC_IPRH_INT58			(0x04000000)
+#define INTC_IPRH_INT59			(0x08000000)
+#define INTC_IPRH_INT60			(0x10000000)
+#define INTC_IPRH_INT61			(0x20000000)
+#define INTC_IPRH_INT62			(0x40000000)
+#define INTC_IPRH_INT63			(0x80000000)
+
+/* Bit definitions and macros for IPRL */
+#define INTC_IPRL_INT0			(0x00000001)
+#define INTC_IPRL_INT1			(0x00000002)
+#define INTC_IPRL_INT2			(0x00000004)
+#define INTC_IPRL_INT3			(0x00000008)
+#define INTC_IPRL_INT4			(0x00000010)
+#define INTC_IPRL_INT5			(0x00000020)
+#define INTC_IPRL_INT6			(0x00000040)
+#define INTC_IPRL_INT7			(0x00000080)
+#define INTC_IPRL_INT8			(0x00000100)
+#define INTC_IPRL_INT9			(0x00000200)
+#define INTC_IPRL_INT10			(0x00000400)
+#define INTC_IPRL_INT11			(0x00000800)
+#define INTC_IPRL_INT12			(0x00001000)
+#define INTC_IPRL_INT13			(0x00002000)
+#define INTC_IPRL_INT14			(0x00004000)
+#define INTC_IPRL_INT15			(0x00008000)
+#define INTC_IPRL_INT16			(0x00010000)
+#define INTC_IPRL_INT17			(0x00020000)
+#define INTC_IPRL_INT18			(0x00040000)
+#define INTC_IPRL_INT19			(0x00080000)
+#define INTC_IPRL_INT20			(0x00100000)
+#define INTC_IPRL_INT21			(0x00200000)
+#define INTC_IPRL_INT22			(0x00400000)
+#define INTC_IPRL_INT23			(0x00800000)
+#define INTC_IPRL_INT24			(0x01000000)
+#define INTC_IPRL_INT25			(0x02000000)
+#define INTC_IPRL_INT26			(0x04000000)
+#define INTC_IPRL_INT27			(0x08000000)
+#define INTC_IPRL_INT28			(0x10000000)
+#define INTC_IPRL_INT29			(0x20000000)
+#define INTC_IPRL_INT30			(0x40000000)
+#define INTC_IPRL_INT31			(0x80000000)
+
+/*********************************************************************
+* General Purpose Timers (GPTMR)
+*********************************************************************/
+/* Enable and Mode Select */
+#define GPT_OCT(x)			(x & 0x3)<<4	/* Output Compare Type */
+#define GPT_ICT(x)			(x & 0x3)	/* Input Capture Type */
+#define GPT_CTRL_WDEN			0x80		/* Watchdog Enable */
+#define GPT_CTRL_CE			0x10		/* Counter Enable */
+#define GPT_CTRL_STPCNT			0x04		/* Stop continous */
+#define GPT_CTRL_ODRAIN			0x02		/* Open Drain */
+#define GPT_CTRL_INTEN			0x01		/* Interrupt Enable */
+#define GPT_MODE_GPIO(x)		(x & 0x3)<<4	/* Gpio Mode Type */
+#define GPT_TMS_ICT			0x01		/* Input Capture Enable */
+#define GPT_TMS_OCT			0x02		/* Output Capture Enable */
+#define GPT_TMS_PWM			0x03		/* PWM Capture Enable */
+#define GPT_TMS_SGPIO			0x04		/* PWM Capture Enable */
+
+#define GPT_PWM_WIDTH(x)		(x & 0xffff)
+
+/* Status */
+#define GPT_STA_CAPTURE(x)		(x & 0xffff)
+
+#define GPT_OVFPIN_OVF(x)		(x & 0x70)
+#define GPT_OVFPIN_PIN			0x01
+
+#define GPT_INT_TEXP			0x08
+#define GPT_INT_PWMP			0x04
+#define GPT_INT_COMP			0x02
+#define GPT_INT_CAPT			0x01
+
+/*********************************************************************
+* PCI
+*********************************************************************/
+
+/* Bit definitions and macros for SCR */
+#define PCI_SCR_PE			(0x80000000)	/* Parity Error detected */
+#define PCI_SCR_SE			(0x40000000)	/* System error signalled */
+#define PCI_SCR_MA			(0x20000000)	/* Master aboart received */
+#define PCI_SCR_TR			(0x10000000)	/* Target abort received */
+#define PCI_SCR_TS			(0x08000000)	/* Target abort signalled */
+#define PCI_SCR_DT			(0x06000000)	/* PCI_DEVSEL timing */
+#define PCI_SCR_DP			(0x01000000)	/* Master data parity err */
+#define PCI_SCR_FC			(0x00800000)	/* Fast back-to-back */
+#define PCI_SCR_R			(0x00400000)	/* Reserved */
+#define PCI_SCR_66M			(0x00200000)	/* 66Mhz */
+#define PCI_SCR_C			(0x00100000)	/* Capabilities list */
+#define PCI_SCR_F			(0x00000200)	/* Fast back-to-back enable */
+#define PCI_SCR_S			(0x00000100)	/* SERR enable */
+#define PCI_SCR_ST			(0x00000080)	/* Addr and Data stepping */
+#define PCI_SCR_PER			(0x00000040)	/* Parity error response */
+#define PCI_SCR_V			(0x00000020)	/* VGA palette snoop enable */
+#define PCI_SCR_MW			(0x00000010)	/* Memory write and invalidate enable */
+#define PCI_SCR_SP			(0x00000008)	/* Special cycle monitor or ignore */
+#define PCI_SCR_B			(0x00000004)	/* Bus master enable */
+#define PCI_SCR_M			(0x00000002)	/* Memory access control */
+#define PCI_SCR_IO			(0x00000001)	/* I/O access control */
+
+#define PCI_CR1_BIST(x)			((x & 0xFF) << 24)	/* Built in self test */
+#define PCI_CR1_HDR(x)			((x & 0xFF) << 16)	/* Header type */
+#define PCI_CR1_LTMR(x)			((x & 0xF8) << 8)	/* Latency timer */
+#define PCI_CR1_CLS(x)			(x & 0x0F)		/* Cache line size */
+
+#define PCI_BAR_BAR0(x)			(x & 0xFFFC0000)
+#define PCI_BAR_BAR1(x)			(x & 0xC0000000)
+#define PCI_BAR_PREF			(0x00000004)	/* Prefetchable access */
+#define PCI_BAR_RANGE			(0x00000002)	/* Fixed to 00 */
+#define PCI_BAR_IO_M			(0x00000001)	/* IO / memory space */
+
+#define PCI_CR2_MAXLAT(x)		((x & 0xFF) << 24)	/* Maximum latency */
+#define PCI_CR2_MINGNT(x)		((x & 0xFF) << 16)	/* Minimum grant */
+#define PCI_CR2_INTPIN(x)		((x & 0xFF) << 8)	/* Interrupt Pin */
+#define PCI_CR2_INTLIN(x)		(x & 0xFF)	/* Interrupt Line */
+
+#define PCI_GSCR_DRD			(0x80000000)	/* Delayed read discarded */
+#define PCI_GSCR_PE			(0x20000000)	/* PCI_PERR detected */
+#define PCI_GSCR_SE			(0x10000000)	/* SERR detected */
+#define PCI_GSCR_ER			(0x08000000)	/* Error response detected */
+#define PCI_GSCR_DRDE			(0x00008000)	/* Delayed read discarded enable */
+#define PCI_GSCR_PEE			(0x00002000)	/* PERR detected interrupt enable */
+#define PCI_GSCR_SEE			(0x00001000)	/* SERR detected interrupt enable */
+#define PCI_GSCR_PR			(0x00000001)	/* PCI reset */
+
+#define PCI_TCR1_LD			(0x01000000)	/* Latency rule disable */
+#define PCI_TCR1_PID			(0x00020000)	/* Prefetch invalidate and disable */
+#define PCI_TCR1_P			(0x00010000)	/* Prefetch reads */
+#define PCI_TCR1_WCD			(0x00000100)	/* Write combine disable */
+
+#define PCI_TCR1_B5E			(0x00002000)	/*  */
+#define PCI_TCR1_B4E			(0x00001000)	/*  */
+#define PCI_TCR1_B3E			(0x00000800)	/*  */
+#define PCI_TCR1_B2E			(0x00000400)	/*  */
+#define PCI_TCR1_B1E			(0x00000200)	/*  */
+#define PCI_TCR1_B0E			(0x00000100)	/*  */
+#define PCI_TCR1_CR			(0x00000001)	/*  */
+
+#define PCI_TBATR_BAT0(x)		(x & 0xFFFC0000)
+#define PCI_TBATR_BAT1(x)		(x & 0xC0000000)
+#define PCI_TBATR_EN			(0x00000001)	/* Enable */
+
+#define PCI_IWCR_W0C_IO			(0x08000000)	/* Windows Maps to PCI I/O */
+#define PCI_IWCR_W0C_PRC_RDMUL		(0x04000000)	/* PCI Memory Read multiple */
+#define PCI_IWCR_W0C_PRC_RDLN		(0x02000000)	/* PCI Memory Read line */
+#define PCI_IWCR_W0C_PRC_RD		(0x00000000)	/* PCI Memory Read */
+#define PCI_IWCR_W0C_EN			(0x01000000)	/* Enable - Register initialize */
+#define PCI_IWCR_W1C_IO			(0x00080000)	/* Windows Maps to PCI I/O */
+#define PCI_IWCR_W1C_PRC_RDMUL		(0x00040000)	/* PCI Memory Read multiple */
+#define PCI_IWCR_W1C_PRC_RDLN		(0x00020000)	/* PCI Memory Read line */
+#define PCI_IWCR_W1C_PRC_RD		(0x00000000)	/* PCI Memory Read */
+#define PCI_IWCR_W1C_EN			(0x00010000)	/* Enable - Register initialize */
+#define PCI_IWCR_W2C_IO			(0x00000800)	/* Windows Maps to PCI I/O */
+#define PCI_IWCR_W2C_PRC_RDMUL		(0x00000400)	/* PCI Memory Read multiple */
+#define PCI_IWCR_W2C_PRC_RDLN		(0x00000200)	/* PCI Memory Read line */
+#define PCI_IWCR_W2C_PRC_RD		(0x00000000)	/* PCI Memory Read */
+#define PCI_IWCR_W2C_EN			(0x00000100)	/* Enable - Register initialize */
+
+#define PCI_ICR_REE			(0x04000000)	/* Retry error enable */
+#define PCI_ICR_IAE			(0x02000000)	/* Initiator abort enable */
+#define PCI_ICR_TAE			(0x01000000)	/* Target abort enable */
+#define PCI_ICR_MAXRETRY(x)		((x) & 0x000000FF)
+
+#define PCIARB_ACR_DS			(0x80000000)
+#define PCIARB_ARC_EXTMINTEN(x)		(((x)&0x1F) << 17)
+#define PCIARB_ARC_INTMINTEN		(0x00010000)
+#define PCIARB_ARC_EXTMPRI(x)		(((x)&0x1F) << 1)
+#define PCIARB_ARC_INTMPRI		(0x00000001)
+
+#endif				/* mcf547x_8x_h */
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
new file mode 100644
index 0000000..ab574d5
--- /dev/null
+++ b/include/configs/M52277EVB.h
@@ -0,0 +1,251 @@
+/*
+ * Configuation settings for the Freescale MCF52277 EVB board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M52277EVB_H
+#define _M52277EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5227x		/* define processor family */
+#define CONFIG_M52277		/* define processor type */
+#define CONFIG_M52277EVB	/* M52277EVB board */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_REGINFO
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_BMP
+
+#define CONFIG_HOSTNAME		M52277EVB
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0"	\
+	"loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0"	\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off 0 0x3ffff;"		\
+	"era 0 3ffff;"				\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+
+/* LCD */
+#ifdef CONFIG_CMD_BMP
+#define CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_LCD_LOGO
+#define CONFIG_SHARP_LQ035Q7DH06
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CFG_USB_EHCI_REGS_BASE		0xFC0B0000
+#define CFG_USB_EHCI_CPU_INIT
+#endif
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CFG_RTC_OSCILLATOR	(32 * CFG_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
+#define CFG_I2C_SPEED		80000	/* I2C speed and slave address  */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_OFFSET		0x58000
+#define CFG_IMMR		CFG_MBAR
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CFG_INPUT_CLKSRC	16000000
+
+#define CONFIG_PRAM		512	/* 512 KB */
+
+#define CFG_PROMPT		"-> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 0x10000)
+
+#define CFG_HZ			1000
+
+#define CFG_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x80000000
+#define CFG_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL	0x21
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x40000000
+#define CFG_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CFG_SDRAM_CFG1		0x43711630
+#define CFG_SDRAM_CFG2		0x56670000
+#define CFG_SDRAM_CTRL		0xE1092000
+#define CFG_SDRAM_EMOD		0x81810000
+#define CFG_SDRAM_MODE		0x00CD0000
+
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CFG_BOOTPARAMS_LEN	64*1024
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OVERWRITE	1
+#undef CFG_ENV_IS_EMBEDDED
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_BASE		CFG_CS0_BASE
+#define CFG_FLASH0_BASE		CFG_CS0_BASE
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x8000)
+#define CFG_ENV_SECT_SIZE	0x8000
+
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+#	define CFG_FLASH_CFI_DRIVER	1
+#	define CFG_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CFG_FLASH_CHECKSUM
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#	define CONFIG_JFFS2_DEV		"nor0"
+#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CFG_FLASH0_BASE + 0x40000)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE		16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+#define CFG_CS0_BASE		0x00000000
+#define CFG_CS0_MASK		0x00FF0001
+#define CFG_CS0_CTRL		0x00001FA0
+
+#endif				/* _M52277EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 47d74a3..e956739 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -213,7 +213,7 @@
 
 #ifdef NANDFLASH_SIZE
 #	define CFG_MAX_NAND_DEVICE	1
-#	define CFG_NAND_BASE		(CFG_CS2_BASE << 16)
+#	define CFG_NAND_BASE		CFG_CS2_BASE
 #	define CFG_NAND_SIZE		1
 #	define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
 #	define NAND_MAX_CHIPS		1
@@ -224,7 +224,7 @@
 #	define CONFIG_JFFS2_PART_OFFSET	0x00000000
 #endif
 
-#define CFG_FLASH_BASE		(CFG_CS0_BASE << 16)
+#define CFG_FLASH_BASE		CFG_CS0_BASE
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -254,12 +254,12 @@
 #define CFG_CS0_MASK		0x007f0001
 #define CFG_CS0_CTRL		0x00001fa0
 
-#define CFG_CS1_BASE		0x1000
+#define CFG_CS1_BASE		0x10000000
 #define CFG_CS1_MASK		0x001f0001
 #define CFG_CS1_CTRL		0x002A3780
 
 #ifdef NANDFLASH_SIZE
-#define CFG_CS2_BASE		0x2000
+#define CFG_CS2_BASE		0x20000000
 #define CFG_CS2_MASK		((NANDFLASH_SIZE << 20) | 1)
 #define CFG_CS2_CTRL		0x00001f60
 #endif
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
new file mode 100644
index 0000000..6bfffa1
--- /dev/null
+++ b/include/configs/M5373EVB.h
@@ -0,0 +1,267 @@
+/*
+ * Configuation settings for the Freescale MCF5373 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5373EVB_H
+#define _M5373EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF532x		/* define processor family */
+#define CONFIG_M5373		/* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef NANDFLASH_SIZE
+#      define CONFIG_CMD_NAND
+#endif
+
+#define CFG_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_NET_MULTI		1
+#	define CONFIG_MII		1
+#	define CFG_DISCOVER_PHY
+#	define CFG_RX_ETH_BUFFER	8
+#	define CFG_FAULT_ECHO_LINK_DOWN
+
+#	define CFG_FEC0_PINMUX		0
+#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP 	50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CFG_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CFG_FAULT_ECHO_LINK_DOWN
+#			define CFG_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C		/* I2C with hw support */
+#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CFG_I2C_SPEED		80000
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_OFFSET		0x58000
+#define CFG_IMMR		CFG_MBAR
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M5373EVB
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"			\
+	"loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0"	\
+	"u-boot=u-boot.bin\0"	\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"	\
+	"prog=prot off 0 2ffff;"	\
+	"era 0 2ffff;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"	\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CFG_PROMPT		"-> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CFG_LOAD_ADDR		0x40010000
+
+#define CFG_HZ			1000
+#define CFG_CLK			80000000
+#define CFG_CPU_CLK		CFG_CLK * 3
+
+#define CFG_MBAR		0xFC000000
+
+#define CFG_LATCH_ADDR		(CFG_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x80000000
+#define CFG_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL	0x221
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x40000000
+#define CFG_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CFG_SDRAM_CFG1		0x53722730
+#define CFG_SDRAM_CFG2		0x56670000
+#define CFG_SDRAM_CTRL		0xE1092000
+#define CFG_SDRAM_EMOD		0x40010000
+#define CFG_SDRAM_MODE		0x018D0000
+
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN	64*1024
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+#	define CFG_FLASH_CFI_DRIVER	1
+#	define CFG_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#ifdef NANDFLASH_SIZE
+#	define CFG_MAX_NAND_DEVICE	1
+#	define CFG_NAND_BASE		CFG_CS2_BASE
+#	define CFG_NAND_SIZE		1
+#	define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#	define NAND_MAX_CHIPS		1
+#	define NAND_ALLOW_ERASE_ALL	1
+#	define CONFIG_JFFS2_NAND	1
+#	define CONFIG_JFFS2_DEV		"nand0"
+#	define CONFIG_JFFS2_PART_SIZE	(CFG_CS2_MASK & ~1)
+#	define CONFIG_JFFS2_PART_OFFSET	0x00000000
+#endif
+
+#define CFG_FLASH_BASE		CFG_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_IS_EMBEDDED	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE		0
+#define CFG_CS0_MASK		0x007f0001
+#define CFG_CS0_CTRL		0x00001fa0
+
+#define CFG_CS1_BASE		0x10000000
+#define CFG_CS1_MASK		0x001f0001
+#define CFG_CS1_CTRL		0x002A3780
+
+#ifdef NANDFLASH_SIZE
+#define CFG_CS2_BASE		0x20000000
+#define CFG_CS2_MASK		((NANDFLASH_SIZE << 20) | 1)
+#define CFG_CS2_CTRL		0x00001f60
+#endif
+
+#endif				/* _M5373EVB_H */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 211f11d..581c794 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -176,6 +176,10 @@
 /* PCI */
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_SKIPPCI_HOSTBRIDGE
+
+#define CFG_PCI_CACHE_LINE_SIZE	4
 
 #define CFG_PCI_MEM_BUS		0xA0000000
 #define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BUS
@@ -192,9 +196,7 @@
 
 /* FPGA - Spartan 2 */
 /* experiment
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_FPGA		CFG_SPARTAN3
 #define CONFIG_FPGA_COUNT	1
 #define CFG_FPGA_PROG_FEEDBACK
 #define CFG_FPGA_CHECK_CTRLC
@@ -286,9 +288,9 @@
 #	define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
 #	define CFG_ENV_SECT_SIZE	0x2000
 #else
-#	define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#	define CFG_FLASH0_BASE		CFG_CS1_BASE
-#	define CFG_FLASH1_BASE		CFG_CS0_BASE
+#	define CFG_FLASH_BASE		CFG_CS0_BASE
+#	define CFG_FLASH0_BASE		CFG_CS0_BASE
+#	define CFG_FLASH1_BASE		CFG_CS1_BASE
 #	define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
 #	define CFG_ENV_SECT_SIZE	0x20000
 #endif
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
new file mode 100644
index 0000000..84c2105
--- /dev/null
+++ b/include/configs/M5475EVB.h
@@ -0,0 +1,311 @@
+/*
+ * Configuation settings for the Freescale MCF5475 board.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5475EVB_H
+#define _M5475EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF547x_8x	/* define processor family */
+#define CONFIG_M547x		/* define processor type */
+#define CONFIG_M5475		/* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_USB
+
+#define CONFIG_SLTTMR
+
+#define CONFIG_FSLDMAFEC
+#ifdef CONFIG_FSLDMAFEC
+#	define CONFIG_NET_MULTI		1
+#	define CONFIG_MII		1
+#	define CONFIG_HAS_ETH1
+
+#	define CFG_DISCOVER_PHY
+#	define CFG_RX_ETH_BUFFER	32
+#	define CFG_TX_ETH_BUFFER	48
+#	define CFG_FAULT_ECHO_LINK_DOWN
+
+#	define CFG_FEC0_PINMUX		0
+#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CFG_FEC1_PINMUX		0
+#	define CFG_FEC1_MIIBASE		CFG_FEC0_IOBASE
+
+#	define MCFFEC_TOUT_LOOP 	50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CFG_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CFG_FAULT_ECHO_LINK_DOWN
+#			define CFG_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CFG_DISCOVER_PHY */
+
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#endif
+
+#ifdef CONFIG_CMD_USB
+#	define CONFIG_USB_OHCI_NEW
+#	define CONFIG_USB_STORAGE
+
+#	ifndef CONFIG_CMD_PCI
+#		define CONFIG_CMD_PCI
+#	endif
+#	define CONFIG_PCI_OHCI
+#	define CONFIG_DOS_PARTITION
+
+#	undef CFG_USB_OHCI_BOARD_INIT
+#	undef CFG_USB_OHCI_CPU_INIT
+#	define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#	define CFG_USB_OHCI_SLOT_NAME		"isp1561"
+#	define CFG_OHCI_SWAP_REG_ACCESS
+#endif
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C		/* I2C with hw support */
+#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CFG_I2C_SPEED		80000
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_OFFSET		0x00008F00
+#define CFG_IMMR		CFG_MBAR
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_SKIPPCI_HOSTBRIDGE
+
+#define CFG_PCI_CACHE_LINE_SIZE	8
+
+#define CFG_PCI_MEM_BUS		0x80000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BUS
+#define CFG_PCI_MEM_SIZE	0x10000000
+
+#define CFG_PCI_IO_BUS		0x71000000
+#define CFG_PCI_IO_PHYS		CFG_PCI_IO_BUS
+#define CFG_PCI_IO_SIZE		0x01000000
+
+#define CFG_PCI_CFG_BUS		0x70000000
+#define CFG_PCI_CFG_PHYS	CFG_PCI_CFG_BUS
+#define CFG_PCI_CFG_SIZE	0x01000000
+#endif
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M547xEVB
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off bank 1;"			\
+	"era ff800000 ff82ffff;"		\
+	"cp.b ${loadaddr} ff800000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CFG_PROMPT		"-> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CFG_LOAD_ADDR		0x00010000
+
+#define CFG_HZ			1000
+#define CFG_CLK			CFG_BUSCLK
+#define CFG_CPU_CLK		CFG_CLK * 2
+
+#define CFG_MBAR		0xF0000000
+#define CFG_INTSRAM		(CFG_MBAR + 0x10000)
+#define CFG_INTSRAMSZ		0x8000
+
+/*#define CFG_LATCH_ADDR		(CFG_CS1_BASE + 0x80000)*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0xF2000000
+#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL	0x21
+#define CFG_INIT_RAM1_ADDR	(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
+#define CFG_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
+#define CFG_INIT_RAM1_CTRL	0x21
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_CFG1		0x73711630
+#define CFG_SDRAM_CFG2		0x46370000
+#define CFG_SDRAM_CTRL		0xE10B0000
+#define CFG_SDRAM_EMOD		0x40010000
+#define CFG_SDRAM_MODE		0x018D0000
+#define CFG_SDRAM_DRVSTRENGTH	0x000002AA
+#ifdef CFG_DRAMSZ1
+#	define CFG_SDRAM_SIZE	(CFG_DRAMSZ + CFG_DRAMSZ1)
+#else
+#	define CFG_SDRAM_SIZE	CFG_DRAMSZ
+#endif
+
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN	64*1024
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+#	define CFG_FLASH_BASE		(CFG_CS0_BASE)
+#	define CFG_FLASH_CFI_DRIVER	1
+#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CFG_NOR1SZ
+#	define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CFG_FLASH_SIZE		((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
+#	define CFG_FLASH_BANKS_LIST	{ CFG_CS0_BASE, CFG_CS1_BASE }
+#else
+#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CFG_FLASH_SIZE		(CFG_BOOTSZ << 20)
+#endif
+#endif
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET		0x2000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_IS_EMBEDDED	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - NOR Flash
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE		0xFF800000
+#define CFG_CS0_MASK		(((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CFG_CS0_CTRL		0x00101980
+
+#ifdef CFG_NOR1SZ
+#define CFG_CS1_BASE		0xF8000000
+#define CFG_CS1_MASK		(((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CFG_CS1_CTRL		0x00000D80
+#endif
+
+#endif				/* _M5475EVB_H */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
new file mode 100644
index 0000000..e9e5ee9
--- /dev/null
+++ b/include/configs/M5485EVB.h
@@ -0,0 +1,296 @@
+/*
+ * Configuation settings for the Freescale MCF5485 FireEngine board.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5485EVB_H
+#define _M5485EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF547x_8x	/* define processor family */
+#define CONFIG_M548x		/* define processor type */
+#define CONFIG_M5485		/* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_USB
+
+#define CONFIG_SLTTMR
+
+#define CONFIG_FSLDMAFEC
+#ifdef CONFIG_FSLDMAFEC
+#	define CONFIG_NET_MULTI		1
+#	define CONFIG_MII		1
+#	define CONFIG_HAS_ETH1
+
+#	define CFG_DISCOVER_PHY
+#	define CFG_RX_ETH_BUFFER	32
+#	define CFG_TX_ETH_BUFFER	48
+#	define CFG_FAULT_ECHO_LINK_DOWN
+
+#	define CFG_FEC0_PINMUX		0
+#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CFG_FEC1_PINMUX		0
+#	define CFG_FEC1_MIIBASE		CFG_FEC0_IOBASE
+
+#	define MCFFEC_TOUT_LOOP 	50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CFG_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CFG_FAULT_ECHO_LINK_DOWN
+#			define CFG_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CFG_DISCOVER_PHY */
+
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#endif
+
+#ifdef CONFIG_CMD_USB
+#	define CONFIG_USB_STORAGE
+#	define CONFIG_DOS_PARTITION
+#	define CONFIG_USB_OHCI_NEW
+#	ifndef CONFIG_CMD_PCI
+#		define CONFIG_CMD_PCI
+#	endif
+/*#	define CONFIG_PCI_OHCI*/
+#	define CFG_USB_OHCI_REGS_BASE		0x80041000
+#	define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#	define CFG_USB_OHCI_SLOT_NAME		"isp1561"
+#	define CFG_OHCI_SWAP_REG_ACCESS
+#endif
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C		/* I2C with hw support */
+#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CFG_I2C_SPEED		80000
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_OFFSET		0x00008F00
+#define CFG_IMMR		CFG_MBAR
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+
+#define CFG_PCI_MEM_BUS		0x80000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BUS
+#define CFG_PCI_MEM_SIZE	0x10000000
+
+#define CFG_PCI_IO_BUS		0x71000000
+#define CFG_PCI_IO_PHYS		CFG_PCI_IO_BUS
+#define CFG_PCI_IO_SIZE		0x01000000
+
+#define CFG_PCI_CFG_BUS		0x70000000
+#define CFG_PCI_CFG_PHYS	CFG_PCI_CFG_BUS
+#define CFG_PCI_CFG_SIZE	0x01000000
+#endif
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#define CONFIG_HOSTNAME		M548xEVB
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off bank 1;"			\
+	"era ff800000 ff82ffff;"		\
+	"cp.b ${loadaddr} ff800000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CFG_PROMPT		"-> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CFG_LOAD_ADDR		0x00010000
+
+#define CFG_HZ			1000
+#define CFG_CLK			CFG_BUSCLK
+#define CFG_CPU_CLK		CFG_CLK * 2
+
+#define CFG_MBAR		0xF0000000
+#define CFG_INTSRAM		(CFG_MBAR + 0x10000)
+#define CFG_INTSRAMSZ		0x8000
+
+/*#define CFG_LATCH_ADDR		(CFG_CS1_BASE + 0x80000)*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0xF2000000
+#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL	0x21
+#define CFG_INIT_RAM1_ADDR	(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
+#define CFG_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
+#define CFG_INIT_RAM1_CTRL	0x21
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_CFG1		0x73711630
+#define CFG_SDRAM_CFG2		0x46370000
+#define CFG_SDRAM_CTRL		0xE10B0000
+#define CFG_SDRAM_EMOD		0x40010000
+#define CFG_SDRAM_MODE		0x018D0000
+#define CFG_SDRAM_DRVSTRENGTH	0x000002AA
+#ifdef CFG_DRAMSZ1
+#	define CFG_SDRAM_SIZE	(CFG_DRAMSZ + CFG_DRAMSZ1)
+#else
+#	define CFG_SDRAM_SIZE	CFG_DRAMSZ
+#endif
+
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN	64*1024
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+#	define CFG_FLASH_BASE		(CFG_CS0_BASE)
+#	define CFG_FLASH_CFI_DRIVER	1
+#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CFG_NOR1SZ
+#	define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CFG_FLASH_SIZE		((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
+#	define CFG_FLASH_BANKS_LIST	{ CFG_CS0_BASE, CFG_CS1_BASE }
+#else
+#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CFG_FLASH_SIZE		(CFG_BOOTSZ << 20)
+#endif
+#endif
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET		0x2000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_IS_EMBEDDED	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - NOR Flash
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE		0xFF800000
+#define CFG_CS0_MASK		(((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CFG_CS0_CTRL		0x00101980
+
+#ifdef CFG_NOR1SZ
+#define CFG_CS1_BASE		0xF8000000
+#define CFG_CS1_MASK		(((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CFG_CS1_CTRL		0x00000D80
+#endif
+
+#endif				/* _M5485EVB_H */
diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index 43f97c4..9159206 100644
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c
@@ -313,6 +313,16 @@ board_init_f (ulong bootflag)
 	debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
 #endif /* CONFIG_PRAM */
 
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem (addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_LCD */
+
 	/*
 	 * reserve memory for U-Boot code, data & bss
 	 * round down to next 4 kB limit
diff --git a/net/eth.c b/net/eth.c
index 316e817..4a9e1e6 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -61,6 +61,7 @@ extern int uec_initialize(int);
 extern int bfin_EMAC_initialize(bd_t *);
 extern int atstk1000_eth_initialize(bd_t *);
 extern int mcffec_initialize(bd_t*);
+extern int mcdmafec_initialize(bd_t*);
 
 #ifdef CONFIG_API
 extern void (*push_packet)(volatile void *, int);
@@ -275,6 +276,9 @@ int eth_initialize(bd_t *bis)
 #if defined(CONFIG_MCFFEC)
 	mcffec_initialize(bis);
 #endif
+#if defined(CONFIG_FSLDMAFEC)
+	mcdmafec_initialize(bis);
+#endif
 
 	if (!eth_devices) {
 		puts ("No ethernet found.\n");