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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-10-15 15:01:11 +0200 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-11-25 11:32:31 +0100 |
| commit | d8d29a4489c72ed8cbeafa42ea5c06e26b80a2e5 (patch) | |
| tree | 084769b0e016fec5459d89bb5f4d8bf5992b3abf | |
| parent | 29e5c027889ed583fd04d87927e714201b47a225 (diff) | |
| download | u-boot-d8d29a4489c72ed8cbeafa42ea5c06e26b80a2e5.zip u-boot-d8d29a4489c72ed8cbeafa42ea5c06e26b80a2e5.tar.gz u-boot-d8d29a4489c72ed8cbeafa42ea5c06e26b80a2e5.tar.bz2 | |
reset: stm32: Add support of MCU HOLD BOOT
Handle the register RCC_MP_GCR without SET/CLR registers
but with a direct access to bit BOOT_MCU:
- deassert => set the bit: The MCU will not be in HOLD_BOOT
- assert => clear the bit: The MCU will be set in HOLD_BOOT
With this patch the RCC driver handles the MCU_HOLD_BOOT_R value
added in binding stm32mp1-resets.h
Cc: Fabien DESSENNE <fabien.dessenne@st.com>
Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| -rw-r--r-- | drivers/reset/stm32-reset.c | 17 | ||||
| -rw-r--r-- | include/dt-bindings/reset/stm32mp1-resets.h | 1 |
2 files changed, 14 insertions, 4 deletions
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c index 64a11cf..20c36a9 100644 --- a/drivers/reset/stm32-reset.c +++ b/drivers/reset/stm32-reset.c @@ -14,6 +14,9 @@ #include <asm/io.h> #include <linux/bitops.h> +/* offset of register without set/clear management */ +#define RCC_MP_GCR_OFFSET 0x10C + /* reset clear offset for STM32MP RCC */ #define RCC_CL 0x4 @@ -40,8 +43,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl) reset_ctl->id, bank, offset); if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) - /* reset assert is done in rcc set register */ - writel(BIT(offset), priv->base + bank); + if (bank != RCC_MP_GCR_OFFSET) + /* reset assert is done in rcc set register */ + writel(BIT(offset), priv->base + bank); + else + clrbits_le32(priv->base + bank, BIT(offset)); else setbits_le32(priv->base + bank, BIT(offset)); @@ -57,8 +63,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl) reset_ctl->id, bank, offset); if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) - /* reset deassert is done in rcc clr register */ - writel(BIT(offset), priv->base + bank + RCC_CL); + if (bank != RCC_MP_GCR_OFFSET) + /* reset deassert is done in rcc clr register */ + writel(BIT(offset), priv->base + bank + RCC_CL); + else + setbits_le32(priv->base + bank, BIT(offset)); else clrbits_le32(priv->base + bank, BIT(offset)); diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index f0c3aae..702da37 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_STM32MP1_RESET_H_ #define _DT_BINDINGS_STM32MP1_RESET_H_ +#define MCU_HOLD_BOOT_R 2144 #define LTDC_R 3072 #define DSI_R 3076 #define DDRPERFM_R 3080 |