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authorSimon Glass <sjg@chromium.org>2019-02-16 20:24:49 -0700
committerBin Meng <bmeng.cn@gmail.com>2019-02-20 15:25:30 +0800
commitc882163b09b8a2c52e3dd8acd7d296d6d06d1f2e (patch)
tree11000150b6e532a79124e845948330992fb76a24
parent2cd2bc20c4db41d34e735c29b63a9c0b01f8039e (diff)
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x86: sandbox: pch: Add a CONFIG option for PCH
At present this uclass is selected only on x86. In order to add a test for it, it must also support sandbox. Create a new CONFIG_PCH option and enable it on x86 and sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-rw-r--r--arch/Kconfig2
-rw-r--r--drivers/Kconfig2
-rw-r--r--drivers/Makefile3
-rw-r--r--drivers/pch/Kconfig9
4 files changed, 15 insertions, 1 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index 35e2712..d9afe26 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -117,6 +117,7 @@ config SANDBOX
imply VIRTIO_BLK
imply VIRTIO_NET
imply DM_SOUND
+ imply PCH
config SH
bool "SuperH architecture"
@@ -160,6 +161,7 @@ config X86
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
+ imply PCH
config XTENSA
bool "Xtensa architecture"
diff --git a/drivers/Kconfig b/drivers/Kconfig
index e9fbadd..f24351a 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -64,6 +64,8 @@ source "drivers/nvme/Kconfig"
source "drivers/pci/Kconfig"
+source "drivers/pch/Kconfig"
+
source "drivers/pcmcia/Kconfig"
source "drivers/phy/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index eca023a..a7bba3e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -86,7 +86,8 @@ obj-y += misc/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NVME) += nvme/
obj-y += pcmcia/
-obj-$(CONFIG_X86) += pch/
+obj-y += dfu/
+obj-$(CONFIG_PCH) += pch/
obj-y += phy/allwinner/
obj-y += phy/marvell/
obj-y += rtc/
diff --git a/drivers/pch/Kconfig b/drivers/pch/Kconfig
new file mode 100644
index 0000000..18f006d
--- /dev/null
+++ b/drivers/pch/Kconfig
@@ -0,0 +1,9 @@
+config PCH
+ bool "Enable Platform-controller Hub (PCH) support"
+ depends on X86 || SANDBOX
+ help
+ Most x86 chips include a PCH which is responsible for handling
+ parts of the system not handled by that CPU. It supersedes the
+ northbridge / southbridge architecture that was previously used. The
+ PCH allows for higher performance since the memory functions are
+ handled in the CPU.