diff options
| author | stroese <stroese> | 2003-04-04 16:00:33 +0000 |
|---|---|---|
| committer | stroese <stroese> | 2003-04-04 16:00:33 +0000 |
| commit | baa3d528fe8f03c89bd9006819797db675632703 (patch) | |
| tree | ba95ea2851dae5995d9a2c5f6241112eb699173d | |
| parent | c1551ea817c0a094b3e5c9573e5dcf4ca8204de6 (diff) | |
| download | u-boot-baa3d528fe8f03c89bd9006819797db675632703.zip u-boot-baa3d528fe8f03c89bd9006819797db675632703.tar.gz u-boot-baa3d528fe8f03c89bd9006819797db675632703.tar.bz2 | |
Changed PPC405GPr version from A to B.
| -rw-r--r-- | cpu/ppc4xx/cpu.c | 6 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu_init.c | 2 | ||||
| -rw-r--r-- | cpu/ppc4xx/speed.c | 2 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 8aaffb1..8532d28 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -67,7 +67,7 @@ int checkcpu (void) #if CONFIG_405GP puts("IBM PowerPC 405GP"); - if (pvr == PVR_405GPR_RA) { + if (pvr == PVR_405GPR_RB) { putc('r'); } puts(" Rev. "); @@ -77,6 +77,7 @@ int checkcpu (void) #endif switch (pvr) { case PVR_405GP_RB: + case PVR_405GPR_RB: putc('B'); break; case PVR_405GP_RC: @@ -94,7 +95,6 @@ int checkcpu (void) break; #endif case PVR_405CR_RA: - case PVR_405GPR_RA: putc('A'); break; case PVR_405CR_RB: @@ -122,7 +122,7 @@ int checkcpu (void) printf("external PCI arbiter enabled\n"); #endif - if ((pvr | 0x00000001) == PVR_405GPR_RA) { + if ((pvr | 0x00000001) == PVR_405GPR_RB) { printf(" 16 kB I-Cache 16 kB D-Cache"); } else { printf(" 16 kB I-Cache 8 kB D-Cache"); diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 9bf180f..1d149bc 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -149,7 +149,7 @@ int cpu_init_r (void) * Set edge conditioning circuitry on PPC405GPr * for compatibility to existing PPC405GP designs. */ - if ((pvr & 0xfffffff0) == (PVR_405GPR_RA & 0xfffffff0)) { + if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { mtdcr(ecr, 0x60606000); } diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 4541529..f075e3a 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -87,7 +87,7 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) /* * Check if PPC405GPr used (mask minor revision field) */ - if ((pvr & 0xfffffff0) == (PVR_405GPR_RA & 0xfffffff0)) { + if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { /* * Determine FWD_DIV B (only PPC405GPr with new mode strapping). */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 6639959..dc04a8f 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -462,7 +462,7 @@ #define PVR_405CR_RA 0x40110041 #define PVR_405CR_RB 0x401100C5 #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ -#define PVR_405GPR_RA 0x50910951 +#define PVR_405GPR_RB 0x50910951 #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_601 0x00010000 |