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| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-03-24 19:35:37 +0100 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-04-04 20:01:57 -0600 |
| commit | ba3bf3879ecb10e3da0892fe42d13ae19ca2439f (patch) | |
| tree | 89194f9408ccef85e1378820bbd11b6694357bf4 | |
| parent | ca0ab2736e47e48d0eea365dd9a57b1cc253ae60 (diff) | |
| download | u-boot-ba3bf3879ecb10e3da0892fe42d13ae19ca2439f.zip u-boot-ba3bf3879ecb10e3da0892fe42d13ae19ca2439f.tar.gz u-boot-ba3bf3879ecb10e3da0892fe42d13ae19ca2439f.tar.bz2 | |
rockchip: clk: rk3399: 24MHz is not a power of 2
The clock driver for the RK3399 mistakenly used (24 * 2^20) where it
should have used (24 * 10^6) in a few calculations.
This commits fixes this.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 1ac4ff4..ff3cc37 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -667,7 +667,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT == CLK_EMMC_PLL_SEL_24M) - return DIV_TO_RATE(24*1024*1024, div); + return DIV_TO_RATE(24*1000*1000, div); else return DIV_TO_RATE(GPLL_HZ, div); } @@ -685,7 +685,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, if (src_clk_div > 127) { /* use 24MHz source for 400KHz clock */ - src_clk_div = 24*1024*1024 / set_rate; + src_clk_div = 24*1000*1000 / set_rate; rk_clrsetreg(&cru->clksel_con[16], CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | |