imx: zmx25: Convert to iomux-v3

There is no change of behavior, even if some pad control values could probably
be simplified.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

1 files changed, 72 insertions, 71 deletions

diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c
index 4f37c59..087d856 100644
--- a/board/syteco/zmx25/zmx25.c
+++ b/board/syteco/zmx25/zmx25.c
@@ -32,91 +32,85 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux-mx25.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init()
 {
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	struct iomuxc_pad_input_select *inputselect;
-	u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
-	u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
-	u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
-	u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
-	u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
-	u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
+	static const iomux_v3_cfg_t sdhc1_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t dig_out_pads[] = {
+		MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
+		MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
+		NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
+		NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
+	};
+
+	static const iomux_v3_cfg_t led_pads[] = {
+		MX25_PAD_CSI_D9__GPIO_4_21,
+		MX25_PAD_CSI_D4__GPIO_1_29,
+	};
+
+	static const iomux_v3_cfg_t can_pads[] = {
+		NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t i2c3_pads[] = {
+		MX25_PAD_CSPI1_SS1__I2C3_DAT,
+		MX25_PAD_GPIO_E__I2C3_CLK,
+	};
 
 	icache_enable();
 
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
-
-	/* Setup of core volatage selection pin to run at 1.4V */
-	writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
+	/* Setup of core voltage selection pin to run at 1.4V */
+	imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
 	gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
 
-	/* Setup of input daisy chains for SD card pins*/
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
-	writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
+	/* Setup of SD card pins*/
+	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 
 	/* Setup of digital output for USB power and OC */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
+	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
 	gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
 
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
+	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
 	gpio_direction_input(IMX_GPIO_NR(1, 18));
 
 	/* Setup of digital output control pins */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
-
-	writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
-	writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
+	imx_iomux_v3_setup_multiple_pads(dig_out_pads,
+						ARRAY_SIZE(dig_out_pads));
 
 	/* Switch both output drivers off */
 	gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
 	gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
 
-	/* Setup of key input pin GPIO2[29]*/
-	writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
-	writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
+	/* Setup of key input pin */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
 	gpio_direction_input(IMX_GPIO_NR(2, 29));
 
 	/* Setup of status LED outputs */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d9);	/* GPIO4[21] */
-	writel(gpio_mux_mode5, &muxctl->pad_csi_d4);	/* GPIO1[29] */
+	imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
 
 	/* Switch both LEDs off */
 	gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
 	gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
 
 	/* Setup of CAN1 and CAN2 signals */
-	writel(gpio_mux_mode6, &muxctl->pad_gpio_a);	/* CAN1 TX */
-	writel(gpio_mux_mode6, &muxctl->pad_gpio_b);	/* CAN1 RX */
-	writel(gpio_mux_mode6, &muxctl->pad_gpio_c);	/* CAN2 TX */
-	writel(gpio_mux_mode6, &muxctl->pad_gpio_d);	/* CAN2 RX */
-
-	/* Setup of input daisy chains for CAN signals*/
-	writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
-	writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
+	imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
 
 	/* Setup of I2C3 signals */
-	writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1);	/* I2C3 SDA */
-	writel(gpio_mux_mode1, &muxctl->pad_gpio_e);	/* I2C3 SCL */
-
-	/* Setup of input daisy chains for I2C3 signals*/
-	writel(input_select1, &inputselect->i2c3_ipp_sda_in);	/* I2C3 SDA */
-	writel(input_select2, &inputselect->i2c3_ipp_scl_in);	/* I2C3 SCL */
+	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
@@ -128,25 +122,32 @@ int board_late_init(void)
 	const char *e;
 
 #ifdef CONFIG_FEC_MXC
-	struct iomuxc_mux_ctl *muxctl;
-	u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
-	u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
-
-	/*
-	 * fec pin init is generic
-	 */
-	mx25_fec_init_pins();
-
-	/*
-	 * Set up LAN-RESET and FEC_RX_ERR
-	 *
-	 * LAN-RESET:  GPIO3[16] is ALT 5 mode of pin U20
-	 * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
-	 */
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-
-	writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
-	writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ *	0 for no pull
+ * or:
+ *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL	0
+
+	static const iomux_v3_cfg_t fec_pads[] = {
+		MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+		MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+		MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+		NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+		MX25_PAD_FEC_MDIO__FEC_MDIO,
+		MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
+
+		MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
+		MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 
 	/* assert PHY reset (low) */
 	gpio_direction_output(IMX_GPIO_NR(3, 16), 0);