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| author | Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> | 2024-01-28 12:07:46 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@edgeble.ai> | 2024-01-29 19:34:17 +0530 |
| commit | b4b0228db8408af56472ceeae279693073ed2204 (patch) | |
| tree | 57859cc37112f1bfaf680e9c3928605d957abf36 | |
| parent | 18e61f23787cb426dc2dd2fda1fa7e288110643e (diff) | |
| download | u-boot-b4b0228db8408af56472ceeae279693073ed2204.zip u-boot-b4b0228db8408af56472ceeae279693073ed2204.tar.gz u-boot-b4b0228db8408af56472ceeae279693073ed2204.tar.bz2 | |
spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data
The current implementation encounters issues when testing data ranging
from 0 to 8 bytes. This was confirmed through testing with both ISSI
(IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode.
Upon investigation, it was observed that utilizing the
"SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in
STIG mode results in a read failure, leading to a compare test failure.
To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized
instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode.
This is based on patch series:
https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.com/
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| -rw-r--r-- | drivers/spi/cadence_ospi_versal.c | 3 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.h | 4 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 3 |
3 files changed, 7 insertions, 3 deletions
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index e02a3b3..c2be307 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -18,9 +18,6 @@ #include "cadence_qspi.h" #include <dt-bindings/power/xlnx-versal-power.h> -#define CMD_4BYTE_READ 0x13 -#define CMD_4BYTE_FAST_READ 0x0C - int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op) { diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 12825f8..693474a 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -33,6 +33,10 @@ #define CQSPI_DUMMY_BYTES_MAX 4 #define CQSPI_DUMMY_CLKS_MAX 31 +#define CMD_4BYTE_FAST_READ 0x0C +#define CMD_4BYTE_OCTAL_READ 0x7c +#define CMD_4BYTE_READ 0x13 + /**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) ****************************************************************************/ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index d033184..fb90532 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -469,6 +469,9 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, else opcode = op->cmd.opcode; + if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr) + opcode = CMD_4BYTE_FAST_READ; + reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; /* Set up dummy cycles. */ |