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| author | Ravi Minnikanti <rminnikanti@marvell.com> | 2024-04-27 09:15:28 -0700 |
|---|---|---|
| committer | Dario Binacchi <dario.binacchi@amarulasolutions.com> | 2024-06-17 09:43:45 +0200 |
| commit | aad8aa56d96b1305ae5a9708b604b2f2a4e97c4e (patch) | |
| tree | 16b8c51ca89dace00b5513e1b79071bb86184194 | |
| parent | 2978e716b2d6682514903920cc61758707c0a5c5 (diff) | |
| download | u-boot-aad8aa56d96b1305ae5a9708b604b2f2a4e97c4e.zip u-boot-aad8aa56d96b1305ae5a9708b604b2f2a4e97c4e.tar.gz u-boot-aad8aa56d96b1305ae5a9708b604b2f2a4e97c4e.tar.bz2 | |
mtd: nand: pxa3xx: Incorrect bitflip return on page read
Once a page is read with higher bitflips all subsequent reads
are returning the same bitflip value even though they have none.
max_bitflip variable is not being reset to 0 across page reads.
This is causing problems like incorrectly
marking erase blocks bad by UBI and causing read failures.
Verified the change with both MTD reads and UBI.
This change is inline with other NFC drivers.
Sample error log where a block is marked bad incorrectly:
ubi0: fixable bit-flip detected at PEB 125
ubi0: run torture test for PEB 125
ubi0: fixable bit-flip detected at PEB 125
ubi0 error: torture_peb: read problems on freshly erased PEB 125,
must be bad
ubi0 error: erase_worker: failed to erase PEB 125, error -5
ubi0: mark PEB 125 as bad
Link: https://lore.kernel.org/all/ea0422cd-a8e6-3c36-f551-a0142893301b@marvell.com
Signed-off-by: rminnikanti <rminnikanti@marvell.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: rminnikanti <rminnikanti@marvell.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
| -rw-r--r-- | drivers/mtd/nand/raw/pxa3xx_nand.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 1d9a6d1..d2a4faa 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -800,6 +800,11 @@ static void prepare_start_command(struct pxa3xx_nand_info *info, int command) info->ecc_err_cnt = 0; info->ndcb3 = 0; info->need_wait = 0; + /* + * Reset max_bitflips to zero. Once command is complete, + * max_bitflips for this READ is returned in ecc.read_page() + */ + info->max_bitflips = 0; switch (command) { case NAND_CMD_READ0: |