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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-09-12 11:12:53 +0200 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2020-12-04 13:21:15 -0700 |
| commit | a6094e1b0a8e1707ad43c5911b8cf902d98951a4 (patch) | |
| tree | f5ad1881688e245730ff9bde8a5abcc00aeb56f6 | |
| parent | bfe682e9ddbd8d13903f5e51452d8bff07706f85 (diff) | |
| download | u-boot-a6094e1b0a8e1707ad43c5911b8cf902d98951a4.zip u-boot-a6094e1b0a8e1707ad43c5911b8cf902d98951a4.tar.gz u-boot-a6094e1b0a8e1707ad43c5911b8cf902d98951a4.tar.bz2 | |
colibri_t30: fix spi1 and uart2/3 resp. uartb/c pinmuxing
Fix SPI1 and UART2/3 resp. UARTB/C pinmuxing.
Note: The former was illegally muxing multiple SoC balls onto the same
internal SoC signal which caused rather strange behaviour regarding
the RS232 serial transceiver ForceOFF# pins as available on Iris.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
| -rw-r--r-- | board/toradex/colibri_t30/pinmux-config-colibri_t30.h | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index 6181b50..c583583 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -181,13 +181,14 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), @@ -270,10 +271,10 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, INPUT), /* LAN_RESET */ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT), |