rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

diff options

author	Bin Meng <bmeng.cn@gmail.com>	2017-08-09 00:21:54 -0700
committer	Marek Vasut <marex@denx.de>	2017-08-21 11:30:44 +0200
commit	a11a5b8ad9d7bfd37e7abbbaecc536f86eabc2d2 (patch)
tree	8bef6d9667258bcad2384941d52cab535481bed1
parent	2d7cb5b426e7e0cdf684d7f8029ad132d7a8d383 (diff)
download	u-boot-a11a5b8ad9d7bfd37e7abbbaecc536f86eabc2d2.zip u-boot-a11a5b8ad9d7bfd37e7abbbaecc536f86eabc2d2.tar.gz u-boot-a11a5b8ad9d7bfd37e7abbbaecc536f86eabc2d2.tar.bz2

usb: ehci: Convert CONFIG_USB_EHCI_PCI to Kconfig

This converts CONFIG_USB_EHCI_PCI to a Kconfig option, and updates all boards that use it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Diffstat

-rw-r--r--

configs/MPC8544DS_defconfig

-rw-r--r--

configs/MPC8572DS_36BIT_defconfig

-rw-r--r--

configs/MPC8572DS_defconfig

-rw-r--r--

drivers/usb/host/Kconfig

-rw-r--r--

include/configs/MPC8544DS.h

-rw-r--r--

include/configs/MPC8572DS.h

-rw-r--r--

include/configs/efi-x86.h

-rw-r--r--

include/configs/x86-common.h

-rw-r--r--

scripts/config_whitelist.txt

9 files changed, 9 insertions, 5 deletions

/* CPU data for m32c. THIS FILE IS MACHINE GENERATED WITH CGEN. Copyright 1996-2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #include "sysdep.h" #include <stdio.h> #include <stdarg.h> #include "ansidecl.h" #include "bfd.h" #include "symcat.h" #include "m32c-desc.h" #include "m32c-opc.h" #include "opintl.h" #include "libiberty.h" #include "xregex.h" /* Attributes. */ static const CGEN_ATTR_ENTRY bool_attr[] = { { "#f", 0 }, { "#t", 1 }, { 0, 0 } }; static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = { { "base", MACH_BASE }, { "m16c", MACH_M16C }, { "m32c", MACH_M32C }, { "max", MACH_MAX }, { 0, 0 } }; static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = { { "m16c", ISA_M16C }, { "m32c", ISA_M32C }, { "max", ISA_MAX }, { 0, 0 } }; const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "ISA", & ISA_attr[0], & ISA_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, { "RESERVED", &bool_attr[0], &bool_attr[0] }, { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, { "SIGNED", &bool_attr[0], &bool_attr[0] }, { 0, 0, 0 } }; const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "ISA", & ISA_attr[0], & ISA_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, { "PC", &bool_attr[0], &bool_attr[0] }, { "PROFILE", &bool_attr[0], &bool_attr[0] }, { 0, 0, 0 } }; const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "ISA", & ISA_attr[0], & ISA_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, { "SIGNED", &bool_attr[0], &bool_attr[0] }, { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, { "RELAX", &bool_attr[0], &bool_attr[0] }, { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, { 0, 0, 0 } }; const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "ISA", & ISA_attr[0], & ISA_attr[0] }, { "ALIAS", &bool_attr[0], &bool_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, { "COND-CTI", &bool_attr[0], &bool_attr[0] }, { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, { "RELAXED", &bool_attr[0], &bool_attr[0] }, { "NO-DIS", &bool_attr[0], &bool_attr[0] }, { "PBB", &bool_attr[0], &bool_attr[0] }, { 0, 0, 0 } }; /* Instruction set variants. */ static const CGEN_ISA m32c_cgen_isa_table[] = { { "m16c", 32, 32, 8, 56 }, { "m32c", 32, 32, 8, 80 }, { 0, 0, 0, 0, 0 } }; /* Machine variants. */ static const CGEN_MACH m32c_cgen_mach_table[] = { { "m16c", "m16c", MACH_M16C, 0 }, { "m32c", "m32c", MACH_M32C, 0 }, { 0, 0, 0, 0 } }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] = { { "r0", 0, {0, {0}}, 0, 0 }, { "r1", 1, {0, {0}}, 0, 0 }, { "r2", 2, {0, {0}}, 0, 0 }, { "r3", 3, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr = { & m32c_cgen_opval_h_gr_entries[0], 4, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] = { { "r0l", 0, {0, {0}}, 0, 0 }, { "r0h", 1, {0, {0}}, 0, 0 }, { "r1l", 2, {0, {0}}, 0, 0 }, { "r1h", 3, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_QI = { & m32c_cgen_opval_h_gr_QI_entries[0], 4, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] = { { "r0", 0, {0, {0}}, 0, 0 }, { "r1", 1, {0, {0}}, 0, 0 }, { "r2", 2, {0, {0}}, 0, 0 }, { "r3", 3, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_HI = { & m32c_cgen_opval_h_gr_HI_entries[0], 4, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] = { { "r2r0", 0, {0, {0}}, 0, 0 }, { "r3r1", 1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_SI = { & m32c_cgen_opval_h_gr_SI_entries[0], 2, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] = { { "r0l", 0, {0, {0}}, 0, 0 }, { "r1l", 1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI = { & m32c_cgen_opval_h_gr_ext_QI_entries[0], 2, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] = { { "r0", 0, {0, {0}}, 0, 0 }, { "r1", 1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI = { & m32c_cgen_opval_h_gr_ext_HI_entries[0], 2, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] = { { "r0l", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0l = { & m32c_cgen_opval_h_r0l_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] = { { "r0h", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0h = { & m32c_cgen_opval_h_r0h_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] = { { "r1l", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1l = { & m32c_cgen_opval_h_r1l_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] = { { "r1h", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1h = { & m32c_cgen_opval_h_r1h_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] = { { "r0", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0 = { & m32c_cgen_opval_h_r0_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] = { { "r1", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1 = { & m32c_cgen_opval_h_r1_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] = { { "r2", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r2 = { & m32c_cgen_opval_h_r2_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] = { { "r3", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r3 = { & m32c_cgen_opval_h_r3_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] = { { "r0l", 0, {0, {0}}, 0, 0 }, { "r0h", 1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h = { & m32c_cgen_opval_h_r0l_r0h_entries[0], 2, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] = { { "r2r0", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r2r0 = { & m32c_cgen_opval_h_r2r0_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] = { { "r3r1", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r3r1 = { & m32c_cgen_opval_h_r3r1_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] = { { "r1r2r0", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 = { & m32c_cgen_opval_h_r1r2r0_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] = { { "a0", 0, {0, {0}}, 0, 0 }, { "a1", 1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar = { & m32c_cgen_opval_h_ar_entries[0], 2, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] = { { "a0", 0, {0, {0}}, 0, 0 }, { "a1", 1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar_QI = { & m32c_cgen_opval_h_ar_QI_entries[0], 2, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] = { { "a0", 0, {0, {0}}, 0, 0 }, { "a1", 1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar_HI = { & m32c_cgen_opval_h_ar_HI_entries[0], 2, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] = { { "a1a0", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar_SI = { & m32c_cgen_opval_h_ar_SI_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] = { { "a0", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_a0 = { & m32c_cgen_opval_h_a0_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] = { { "a1", 1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_a1 = { & m32c_cgen_opval_h_a1_entries[0], 1, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] = { { "geu", 0, {0, {0}}, 0, 0 }, { "c", 0, {0, {0}}, 0, 0 }, { "gtu", 1, {0, {0}}, 0, 0 }, { "eq", 2, {0, {0}}, 0, 0 }, { "z", 2, {0, {0}}, 0, 0 }, { "n", 3, {0, {0}}, 0, 0 }, { "le", 4, {0, {0}}, 0, 0 }, { "o", 5, {0, {0}}, 0, 0 }, { "ge", 6, {0, {0}}, 0, 0 }, { "ltu", 248, {0, {0}}, 0, 0 }, { "nc", 248, {0, {0}}, 0, 0 }, { "leu", 249, {0, {0}}, 0, 0 }, { "ne", 250, {0, {0}}, 0, 0 }, { "nz", 250, {0, {0}}, 0, 0 }, { "pz", 251, {0, {0}}, 0, 0 }, { "gt", 252, {0, {0}}, 0, 0 }, { "no", 253, {0, {0}}, 0, 0 }, { "lt", 254, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16 = { & m32c_cgen_opval_h_cond16_entries[0], 18, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] = { { "geu", 0, {0, {0}}, 0, 0 }, { "c", 0, {0, {0}}, 0, 0 }, { "gtu", 1, {0, {0}}, 0, 0 }, { "eq", 2, {0, {0}}, 0, 0 }, { "z", 2, {0, {0}}, 0, 0 }, { "n", 3, {0, {0}}, 0, 0 }, { "ltu", 4, {0, {0}}, 0, 0 }, { "nc", 4, {0, {0}}, 0, 0 }, { "leu", 5, {0, {0}}, 0, 0 }, { "ne", 6, {0, {0}}, 0, 0 }, { "nz", 6, {0, {0}}, 0, 0 }, { "pz", 7, {0, {0}}, 0, 0 }, { "le", 8, {0, {0}}, 0, 0 }, { "o", 9, {0, {0}}, 0, 0 }, { "ge", 10, {0, {0}}, 0, 0 }, { "gt", 12, {0, {0}}, 0, 0 }, { "no", 13, {0, {0}}, 0, 0 }, { "lt", 14, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16c = { & m32c_cgen_opval_h_cond16c_entries[0], 18, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] = { { "le", 8, {0, {0}}, 0, 0 }, { "o", 9, {0, {0}}, 0, 0 }, { "ge", 10, {0, {0}}, 0, 0 }, { "gt", 12, {0, {0}}, 0, 0 }, { "no", 13, {0, {0}}, 0, 0 }, { "lt", 14, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16j = { & m32c_cgen_opval_h_cond16j_entries[0], 6, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] = { { "geu", 0, {0, {0}}, 0, 0 }, { "c", 0, {0, {0}}, 0, 0 }, { "gtu", 1, {0, {0}}, 0, 0 }, { "eq", 2, {0, {0}}, 0, 0 }, { "z", 2, {0, {0}}, 0, 0 }, { "n", 3, {0, {0}}, 0, 0 }, { "ltu", 4, {0, {0}}, 0, 0 }, { "nc", 4, {0, {0}}, 0, 0 }, { "leu", 5, {0, {0}}, 0, 0 }, { "ne", 6, {0, {0}}, 0, 0 }, { "nz", 6, {0, {0}}, 0, 0 }, { "pz", 7, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 = { & m32c_cgen_opval_h_cond16j_5_entries[0], 12, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] = { { "ltu", 0, {0, {0}}, 0, 0 }, { "nc", 0, {0, {0}}, 0, 0 }, { "leu", 1, {0, {0}}, 0, 0 }, { "ne", 2, {0, {0}}, 0, 0 }, { "nz", 2, {0, {0}}, 0, 0 }, { "pz", 3, {0, {0}}, 0, 0 }, { "no", 4, {0, {0}}, 0, 0 }, { "gt", 5, {0, {0}}, 0, 0 }, { "ge", 6, {0, {0}}, 0, 0 }, { "geu", 8, {0, {0}}, 0, 0 }, { "c", 8, {0, {0}}, 0, 0 }, { "gtu", 9, {0, {0}}, 0, 0 }, { "eq", 10, {0, {0}}, 0, 0 }, { "z", 10, {0, {0}}, 0, 0 }, { "n", 11, {0, {0}}, 0, 0 }, { "o", 12, {0, {0}}, 0, 0 }, { "le", 13, {0, {0}}, 0, 0 }, { "lt", 14, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond32 = { & m32c_cgen_opval_h_cond32_entries[0], 18, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] = { { "dct0", 0, {0, {0}}, 0, 0 }, { "dct1", 1, {0, {0}}, 0, 0 }, { "flg", 2, {0, {0}}, 0, 0 }, { "svf", 3, {0, {0}}, 0, 0 }, { "drc0", 4, {0, {0}}, 0, 0 }, { "drc1", 5, {0, {0}}, 0, 0 }, { "dmd0", 6, {0, {0}}, 0, 0 }, { "dmd1", 7, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 = { & m32c_cgen_opval_h_cr1_32_entries[0], 8, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] = { { "intb", 0, {0, {0}}, 0, 0 }, { "sp", 1, {0, {0}}, 0, 0 }, { "sb", 2, {0, {0}}, 0, 0 }, { "fb", 3, {0, {0}}, 0, 0 }, { "svp", 4, {0, {0}}, 0, 0 }, { "vct", 5, {0, {0}}, 0, 0 }, { "isp", 7, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 = { & m32c_cgen_opval_h_cr2_32_entries[0], 7, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] = { { "dma0", 2, {0, {0}}, 0, 0 }, { "dma1", 3, {0, {0}}, 0, 0 }, { "dra0", 4, {0, {0}}, 0, 0 }, { "dra1", 5, {0, {0}}, 0, 0 }, { "dsa0", 6, {0, {0}}, 0, 0 }, { "dsa1", 7, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 = { & m32c_cgen_opval_h_cr3_32_entries[0], 6, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] = { { "intbl", 1, {0, {0}}, 0, 0 }, { "intbh", 2, {0, {0}}, 0, 0 }, { "flg", 3, {0, {0}}, 0, 0 }, { "isp", 4, {0, {0}}, 0, 0 }, { "sp", 5, {0, {0}}, 0, 0 }, { "sb", 6, {0, {0}}, 0, 0 }, { "fb", 7, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr_16 = { & m32c_cgen_opval_h_cr_16_entries[0], 7, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] = { { "c", 0, {0, {0}}, 0, 0 }, { "d", 1, {0, {0}}, 0, 0 }, { "z", 2, {0, {0}}, 0, 0 }, { "s", 3, {0, {0}}, 0, 0 }, { "b", 4, {0, {0}}, 0, 0 }, { "o", 5, {0, {0}}, 0, 0 }, { "i", 6, {0, {0}}, 0, 0 }, { "u", 7, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_flags = { & m32c_cgen_opval_h_flags_entries[0], 8, 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] = { { "1", 0, {0, {0}}, 0, 0 }, { "2", 1, {0, {0}}, 0, 0 }, { "3", 2, {0, {0}}, 0, 0 }, { "4", 3, {0, {0}}, 0, 0 }, { "5", 4, {0, {0}}, 0, 0 }, { "6", 5, {0, {0}}, 0, 0 }, { "7", 6, {0, {0}}, 0, 0 }, { "8", 7, {0, {0}}, 0, 0 }, { "-1", -8, {0, {0}}, 0, 0 }, { "-2", -7, {0, {0}}, 0, 0 }, { "-3", -6, {0, {0}}, 0, 0 }, { "-4", -5, {0, {0}}, 0, 0 }, { "-5", -4, {0, {0}}, 0, 0 }, { "-6", -3, {0, {0}}, 0, 0 }, { "-7", -2, {0, {0}}, 0, 0 }, { "-8", -1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_shimm = { & m32c_cgen_opval_h_shimm_entries[0], 16, 0, 0, 0, 0, "" }; /* The hardware table. */ #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define A(a) (1 << CGEN_HW_##a) #else #define A(a) (1 << CGEN_HW_/**/a) #endif const CGEN_HW_ENTRY m32c_cgen_hw_table[] = { { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } }; #undef A /* The instruction field table. */ #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define A(a) (1 << CGEN_IFLD_##a) #else #define A(a) (1 << CGEN_IFLD_/**/a) #endif const CGEN_IFLD m32c_cgen_ifld_table[] = { { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_8_S24, "f-dsp-8-s24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { 0, 0, 0, 0, 0, 0, {0, {0}} } }; #undef A /* multi ifield declarations */ const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD []; /* multi ifield definitions */ const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_U8] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO16_S] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_1] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [] = { { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_1_3] } }, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } }, { 0, { (const PTR) 0 } } }; /* The operand table. */ #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define A(a) (1 << CGEN_OPERAND_##a) #else #define A(a) (1 << CGEN_OPERAND_/**/a) #endif #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define OPERAND(op) M32C_OPERAND_##op #else #define OPERAND(op) M32C_OPERAND_/**/op #endif const CGEN_OPERAND m32c_cgen_operand_table[] = { /* pc: program counter */ { "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* Src16RnQI: general register QI view */ { "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Src16RnHI: general register QH view */ { "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Src32RnUnprefixedQI: general register QI view */ { "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32RnUnprefixedHI: general register HI view */ { "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32RnUnprefixedSI: general register SI view */ { "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32RnPrefixedQI: general register QI view */ { "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32RnPrefixedHI: general register HI view */ { "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32RnPrefixedSI: general register SI view */ { "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src16An: address register */ { "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Src16AnQI: address register QI view */ { "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Src16AnHI: address register HI view */ { "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Src32AnUnprefixed: address register */ { "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32AnUnprefixedQI: address register QI view */ { "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32AnUnprefixedHI: address register HI view */ { "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32AnUnprefixedSI: address register SI view */ { "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32AnPrefixed: address register */ { "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32AnPrefixedQI: address register QI view */ { "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32AnPrefixedHI: address register HI view */ { "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Src32AnPrefixedSI: address register SI view */ { "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst16RnQI: general register QI view */ { "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst16RnHI: general register HI view */ { "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst16RnSI: general register SI view */ { "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst16RnExtQI: general register QI/HI view for 'ext' insns */ { "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst32R0QI-S: general register QI view */ { "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32R0HI-S: general register HI view */ { "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32RnUnprefixedQI: general register QI view */ { "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32RnUnprefixedHI: general register HI view */ { "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32RnUnprefixedSI: general register SI view */ { "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32RnExtUnprefixedQI: general register QI view */ { "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32RnExtUnprefixedHI: general register HI view */ { "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32RnPrefixedQI: general register QI view */ { "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32RnPrefixedHI: general register HI view */ { "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32RnPrefixedSI: general register SI view */ { "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst16RnQI-S: general register QI view */ { "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst16AnQI-S: address register QI view */ { "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Bit16Rn: general register bit view */ { "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Bit32RnPrefixed: general register bit view */ { "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Bit32RnUnprefixed: general register bit view */ { "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* R0: r0 */ { "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* R1: r1 */ { "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* R2: r2 */ { "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* R3: r3 */ { "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* R0l: r0l */ { "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* R0h: r0h */ { "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* R2R0: r2r0 */ { "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* R3R1: r3r1 */ { "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* R1R2R0: r1r2r0 */ { "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dst16An: address register */ { "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst16AnQI: address register QI view */ { "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst16AnHI: address register HI view */ { "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst16AnSI: address register SI view */ { "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst16An-S: address register HI view */ { "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dst32AnUnprefixed: address register */ { "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32AnUnprefixedQI: address register QI view */ { "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32AnUnprefixedHI: address register HI view */ { "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32AnUnprefixedSI: address register SI view */ { "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32AnExtUnprefixed: address register */ { "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32AnPrefixed: address register */ { "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32AnPrefixedQI: address register QI view */ { "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32AnPrefixedHI: address register HI view */ { "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Dst32AnPrefixedSI: address register SI view */ { "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Bit16An: address register bit view */ { "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Bit32AnPrefixed: address register bit */ { "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Bit32AnUnprefixed: address register bit */ { "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* A0: a0 */ { "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* A1: a1 */ { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* sb: SB register */ { "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* fb: FB register */ { "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* sp: SP register */ { "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */ { "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Regsetpop: popm regset */ { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Regsetpush: pushm regset */ { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Rn16-push-S: r0[lh] */ { "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* An16-push-S: a[01] */ { "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } }, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, /* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */ { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */ { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */ { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */ { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-8-s24: signed 24 bit displacement at offset 8 bits */ { "Dsp-8-s24", M32C_OPERAND_DSP_8_S24, HW_H_SINT, 8, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S24] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */ { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */ { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */ { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */ { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */ { "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */ { "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */ { "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */ { "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */ { "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */ { "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16, { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */ { "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */ { "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */ { "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */ { "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16, { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */ { "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */ { "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */ { "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */ { "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */ { "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */ { "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */ { "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */ { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */ { "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */ { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */ { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */ { "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */ { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */ { "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */ { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */ { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-8-s4: signed 4 bit immediate at offset 8 bits */ { "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */ { "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-8-QI: signed 8 bit immediate at offset 8 bits */ { "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-8-HI: signed 16 bit immediate at offset 8 bits */ { "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-12-s4: signed 4 bit immediate at offset 12 bits */ { "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */ { "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-13-u3: signed 3 bit immediate at offset 13 bits */ { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-20-s4: signed 4 bit immediate at offset 20 bits */ { "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */ { "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-16-QI: signed 8 bit immediate at offset 16 bits */ { "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-16-HI: signed 16 bit immediate at offset 16 bits */ { "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-16-SI: signed 32 bit immediate at offset 16 bits */ { "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32, { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-24-QI: signed 8 bit immediate at offset 24 bits */ { "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-24-HI: signed 16 bit immediate at offset 24 bits */ { "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16, { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-24-SI: signed 32 bit immediate at offset 24 bits */ { "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32, { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-32-QI: signed 8 bit immediate at offset 32 bits */ { "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-32-SI: signed 32 bit immediate at offset 32 bits */ { "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-32-HI: signed 16 bit immediate at offset 32 bits */ { "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-40-QI: signed 8 bit immediate at offset 40 bits */ { "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-40-HI: signed 16 bit immediate at offset 40 bits */ { "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-40-SI: signed 32 bit immediate at offset 40 bits */ { "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32, { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-48-QI: signed 8 bit immediate at offset 48 bits */ { "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-48-HI: signed 16 bit immediate at offset 48 bits */ { "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-48-SI: signed 32 bit immediate at offset 48 bits */ { "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32, { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-56-QI: signed 8 bit immediate at offset 56 bits */ { "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-56-HI: signed 16 bit immediate at offset 56 bits */ { "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16, { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-64-HI: signed 16 bit immediate at offset 64 bits */ { "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm1-S: signed 1 bit immediate for short format binary insns */ { "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } }, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* Imm3-S: signed 3 bit immediate for short format binary insns */ { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3, { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* Bitno16R: bit number for indexing registers */ { "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* Bitno32Prefixed: bit number for indexing objects */ { "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* Bitno32Unprefixed: bit number for indexing objects */ { "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */ { "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */ { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */ { "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */ { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11, { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */ { "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11, { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */ { "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11, { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */ { "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19, { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */ { "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19, { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */ { "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27, { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */ { "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11, { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */ { "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11, { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */ { "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19, { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */ { "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19, { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */ { "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27, { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* Lab-5-3: 3 bit label */ { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } }, { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab32-jmp-s: 3 bit label */ { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3, { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } }, { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-8-8: 8 bit label */ { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } }, { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-8-16: 16 bit label */ { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } }, { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-8-24: 24 bit label */ { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } }, { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-16-8: 8 bit label */ { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } }, { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-24-8: 8 bit label */ { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-32-8: 8 bit label */ { "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-40-8: 8 bit label */ { "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* sbit: negative bit */ { "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* obit: overflow bit */ { "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* zbit: zero bit */ { "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* cbit: carry bit */ { "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* ubit: stack ptr select bit */ { "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* ibit: interrupt enable bit */ { "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* bbit: reg bank select bit */ { "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* dbit: debug bit */ { "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* cond16-16: condition */ { "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* cond16-24: condition */ { "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* cond16-32: condition */ { "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* cond32-16: condition */ { "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cond32-24: condition */ { "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cond32-32: condition */ { "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cond32-40: condition */ { "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cond16c: condition */ { "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* cond16j: condition */ { "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* cond16j5: condition */ { "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* cond32: condition */ { "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4, { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cond32j: condition */ { "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4, { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sccond32: scCND condition */ { "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* flags16: flags */ { "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* flags32: flags */ { "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cr16: control */ { "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* cr1-Unprefixed-32: control */ { "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cr1-Prefixed-32: control */ { "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cr2-32: control */ { "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cr3-Unprefixed-32: control */ { "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* cr3-Prefixed-32: control */ { "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* Z: Suffix for zero format insns */ { "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* S: Suffix for short format insns */ { "S", M32C_OPERAND_S, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Q: Suffix for quick format insns */ { "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* G: Suffix for general format insns */ { "G", M32C_OPERAND_G, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* X: Empty suffix */ { "X", M32C_OPERAND_X, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* size: any size specifier */ { "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* BitIndex: Bit Index for the next insn */ { "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* SrcIndex: Source Index for the next insn */ { "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* DstIndex: Destination Index for the next insn */ { "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* NoRemainder: Place holder for when the remainder is not kept */ { "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0, { 0, { (const PTR) 0 } }, { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } }, /* src16-Rn-direct-QI: m16c Rn direct source QI */ /* src16-Rn-direct-HI: m16c Rn direct source HI */ /* src32-Rn-direct-Unprefixed-QI: m32c Rn direct source QI */ /* src32-Rn-direct-Prefixed-QI: m32c Rn direct source QI */ /* src32-Rn-direct-Unprefixed-HI: m32c Rn direct source HI */ /* src32-Rn-direct-Prefixed-HI: m32c Rn direct source HI */ /* src32-Rn-direct-Unprefixed-SI: m32c Rn direct source SI */ /* src32-Rn-direct-Prefixed-SI: m32c Rn direct source SI */ /* src16-An-direct-QI: m16c An direct destination QI */ /* src16-An-direct-HI: m16c An direct destination HI */ /* src32-An-direct-Unprefixed-QI: m32c An direct destination QI */ /* src32-An-direct-Unprefixed-HI: m32c An direct destination HI */ /* src32-An-direct-Unprefixed-SI: m32c An direct destination SI */ /* src32-An-direct-Prefixed-QI: m32c An direct destination QI */ /* src32-An-direct-Prefixed-HI: m32c An direct destination HI */ /* src32-An-direct-Prefixed-SI: m32c An direct destination SI */ /* src16-An-indirect-QI: m16c An indirect destination QI */ /* src16-An-indirect-HI: m16c An indirect destination HI */ /* src32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */ /* src32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */ /* src32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */ /* src32-An-indirect-Prefixed-QI: m32c An indirect destination QI */ /* src32-An-indirect-Prefixed-HI: m32c An indirect destination HI */ /* src32-An-indirect-Prefixed-SI: m32c An indirect destination SI */ /* src16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */ /* src16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */ /* src16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */ /* src16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */ /* src16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */ /* src16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */ /* src16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */ /* src16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */ /* src16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */ /* src16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */ /* src32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */ /* src32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */ /* src32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */ /* src32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */ /* src32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */ /* src32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* src32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* src32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */ /* src32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */ /* src32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */ /* src32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */ /* src32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */ /* src32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* src32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* src32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */ /* src32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */ /* src32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */ /* src32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */ /* src32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */ /* src32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* src32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* src32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */ /* src32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */ /* src32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */ /* src32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */ /* src32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */ /* src32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* src32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* src32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */ /* src32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */ /* src32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */ /* src32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */ /* src32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */ /* src32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* src32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* src32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */ /* src32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */ /* src32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */ /* src32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */ /* src32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */ /* src32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* src32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* src16-16-16-absolute-QI: m16c absolute address QI */ /* src16-16-16-absolute-HI: m16c absolute address HI */ /* src32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */ /* src32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */ /* src32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */ /* src32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */ /* src32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */ /* src32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */ /* src32-24-16-absolute-Prefixed-QI: m32c absolute address QI */ /* src32-24-24-absolute-Prefixed-QI: m32c absolute address QI */ /* src32-24-16-absolute-Prefixed-HI: m32c absolute address HI */ /* src32-24-24-absolute-Prefixed-HI: m32c absolute address HI */ /* src32-24-16-absolute-Prefixed-SI: m32c absolute address SI */ /* src32-24-24-absolute-Prefixed-SI: m32c absolute address SI */ /* src16-2-S-8-SB-relative-QI: m16c SB relative address */ /* src16-2-S-8-FB-relative-QI: m16c FB relative address */ /* src16-2-S-16-absolute-QI: m16c absolute address */ /* src32-2-S-8-SB-relative-QI: m32c SB relative address */ /* src32-2-S-8-FB-relative-QI: m32c FB relative address */ /* src32-2-S-16-absolute-QI: m32c absolute address */ /* src32-2-S-8-SB-relative-HI: m32c SB relative address */ /* src32-2-S-8-FB-relative-HI: m32c FB relative address */ /* src32-2-S-16-absolute-HI: m32c absolute address */ /* dst16-Rn-direct-QI: m16c Rn direct destination QI */ /* dst16-Rn-direct-HI: m16c Rn direct destination HI */ /* dst16-Rn-direct-SI: m16c Rn direct destination SI */ /* dst16-Rn-direct-Ext-QI: m16c Rn direct destination QI */ /* dst32-Rn-direct-Unprefixed-QI: m32c Rn direct destination QI */ /* dst32-Rn-direct-Prefixed-QI: m32c Rn direct destination QI */ /* dst32-Rn-direct-Unprefixed-HI: m32c Rn direct destination HI */ /* dst32-Rn-direct-Prefixed-HI: m32c Rn direct destination HI */ /* dst32-Rn-direct-Unprefixed-SI: m32c Rn direct destination SI */ /* dst32-Rn-direct-Prefixed-SI: m32c Rn direct destination SI */ /* dst32-Rn-direct-ExtUnprefixed-QI: m32c Rn direct destination QI */ /* dst32-Rn-direct-ExtUnprefixed-HI: m32c Rn direct destination HI */ /* dst32-R3-direct-Unprefixed-HI: m32c R3 direct HI */ /* dst16-An-direct-QI: m16c An direct destination QI */ /* dst16-An-direct-HI: m16c An direct destination HI */ /* dst16-An-direct-SI: m16c An direct destination SI */ /* dst32-An-direct-Unprefixed-QI: m32c An direct destination QI */ /* dst32-An-direct-Prefixed-QI: m32c An direct destination QI */ /* dst32-An-direct-Unprefixed-HI: m32c An direct destination HI */ /* dst32-An-direct-Prefixed-HI: m32c An direct destination HI */ /* dst32-An-direct-Unprefixed-SI: m32c An direct destination SI */ /* dst32-An-direct-Prefixed-SI: m32c An direct destination SI */ /* dst16-An-indirect-QI: m16c An indirect destination QI */ /* dst16-An-indirect-HI: m16c An indirect destination HI */ /* dst16-An-indirect-SI: m16c An indirect destination SI */ /* dst16-An-indirect-Ext-QI: m16c An indirect destination QI */ /* dst32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */ /* dst32-An-indirect-Prefixed-QI: m32c An indirect destination QI */ /* dst32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */ /* dst32-An-indirect-Prefixed-HI: m32c An indirect destination HI */ /* dst32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */ /* dst32-An-indirect-Prefixed-SI: m32c An indirect destination SI */ /* dst32-An-indirect-ExtUnprefixed-QI: m32c An indirect destination QI */ /* dst32-An-indirect-ExtUnprefixed-HI: m32c An indirect destination HI */ /* dst16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */ /* dst16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */ /* dst16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */ /* dst16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */ /* dst16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */ /* dst16-24-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */ /* dst16-24-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */ /* dst16-24-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */ /* dst16-24-8-An-relative-QI: m16c dsp:8[An] relative destination QI */ /* dst16-24-16-An-relative-QI: m16c dsp:16[An] relative destination QI */ /* dst16-32-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */ /* dst16-32-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */ /* dst16-32-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */ /* dst16-32-8-An-relative-QI: m16c dsp:8[An] relative destination QI */ /* dst16-32-16-An-relative-QI: m16c dsp:16[An] relative destination QI */ /* dst16-40-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */ /* dst16-40-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */ /* dst16-40-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */ /* dst16-40-8-An-relative-QI: m16c dsp:8[An] relative destination QI */ /* dst16-40-16-An-relative-QI: m16c dsp:16[An] relative destination QI */ /* dst16-48-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */ /* dst16-48-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */ /* dst16-48-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */ /* dst16-48-8-An-relative-QI: m16c dsp:8[An] relative destination QI */ /* dst16-48-16-An-relative-QI: m16c dsp:16[An] relative destination QI */ /* dst16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */ /* dst16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */ /* dst16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */ /* dst16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */ /* dst16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */ /* dst16-24-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */ /* dst16-24-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */ /* dst16-24-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */ /* dst16-24-8-An-relative-HI: m16c dsp:8[An] relative destination HI */ /* dst16-24-16-An-relative-HI: m16c dsp:16[An] relative destination HI */ /* dst16-32-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */ /* dst16-32-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */ /* dst16-32-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */ /* dst16-32-8-An-relative-HI: m16c dsp:8[An] relative destination HI */ /* dst16-32-16-An-relative-HI: m16c dsp:16[An] relative destination HI */ /* dst16-40-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */ /* dst16-40-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */ /* dst16-40-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */ /* dst16-40-8-An-relative-HI: m16c dsp:8[An] relative destination HI */ /* dst16-40-16-An-relative-HI: m16c dsp:16[An] relative destination HI */ /* dst16-48-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */ /* dst16-48-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */ /* dst16-48-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */ /* dst16-48-8-An-relative-HI: m16c dsp:8[An] relative destination HI */ /* dst16-48-16-An-relative-HI: m16c dsp:16[An] relative destination HI */ /* dst16-16-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */ /* dst16-16-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */ /* dst16-16-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */ /* dst16-16-8-An-relative-SI: m16c dsp:8[An] relative destination SI */ /* dst16-16-16-An-relative-SI: m16c dsp:16[An] relative destination SI */ /* dst16-24-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */ /* dst16-24-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */ /* dst16-24-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */ /* dst16-24-8-An-relative-SI: m16c dsp:8[An] relative destination SI */ /* dst16-24-16-An-relative-SI: m16c dsp:16[An] relative destination SI */ /* dst16-32-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */ /* dst16-32-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */ /* dst16-32-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */ /* dst16-32-8-An-relative-SI: m16c dsp:8[An] relative destination SI */ /* dst16-32-16-An-relative-SI: m16c dsp:16[An] relative destination SI */ /* dst16-40-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */ /* dst16-40-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */ /* dst16-40-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */ /* dst16-40-8-An-relative-SI: m16c dsp:8[An] relative destination SI */ /* dst16-40-16-An-relative-SI: m16c dsp:16[An] relative destination SI */ /* dst16-48-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */ /* dst16-48-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */ /* dst16-48-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */ /* dst16-48-8-An-relative-SI: m16c dsp:8[An] relative destination SI */ /* dst16-48-16-An-relative-SI: m16c dsp:16[An] relative destination SI */ /* dst16-16-8-SB-relative-Ext-QI: m16c dsp:8[sb] relative destination QI */ /* dst16-16-16-SB-relative-Ext-QI: m16c dsp:16[sb] relative destination QI */ /* dst16-16-8-FB-relative-Ext-QI: m16c dsp:8[fb] relative destination QI */ /* dst16-16-8-An-relative-Ext-QI: m16c dsp:8[An] relative destination QI */ /* dst16-16-16-An-relative-Ext-QI: m16c dsp:16[An] relative destination QI */ /* dst32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */ /* dst32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */ /* dst32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */ /* dst32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */ /* dst32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */ /* dst32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-24-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */ /* dst32-24-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */ /* dst32-24-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */ /* dst32-24-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */ /* dst32-24-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */ /* dst32-24-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-24-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-32-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */ /* dst32-32-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */ /* dst32-32-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */ /* dst32-32-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */ /* dst32-32-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */ /* dst32-32-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-32-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-40-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */ /* dst32-40-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */ /* dst32-40-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */ /* dst32-40-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */ /* dst32-40-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */ /* dst32-40-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-40-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */ /* dst32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */ /* dst32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */ /* dst32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */ /* dst32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */ /* dst32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-24-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */ /* dst32-24-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */ /* dst32-24-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */ /* dst32-24-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */ /* dst32-24-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */ /* dst32-24-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-24-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-32-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */ /* dst32-32-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */ /* dst32-32-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */ /* dst32-32-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */ /* dst32-32-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */ /* dst32-32-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-32-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-40-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */ /* dst32-40-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */ /* dst32-40-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */ /* dst32-40-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */ /* dst32-40-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */ /* dst32-40-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-40-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */ /* dst32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */ /* dst32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */ /* dst32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */ /* dst32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */ /* dst32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-24-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */ /* dst32-24-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */ /* dst32-24-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */ /* dst32-24-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */ /* dst32-24-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */ /* dst32-24-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-24-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-32-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */ /* dst32-32-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */ /* dst32-32-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */ /* dst32-32-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */ /* dst32-32-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */ /* dst32-32-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-32-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-40-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */ /* dst32-40-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */ /* dst32-40-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */ /* dst32-40-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */ /* dst32-40-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */ /* dst32-40-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-40-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */ /* dst32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */ /* dst32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */ /* dst32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */ /* dst32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */ /* dst32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-32-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */ /* dst32-32-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */ /* dst32-32-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */ /* dst32-32-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */ /* dst32-32-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */ /* dst32-32-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-32-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-40-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */ /* dst32-40-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */ /* dst32-40-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */ /* dst32-40-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */ /* dst32-40-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */ /* dst32-40-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-40-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-48-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */ /* dst32-48-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */ /* dst32-48-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */ /* dst32-48-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */ /* dst32-48-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */ /* dst32-48-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-48-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */ /* dst32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */ /* dst32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */ /* dst32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */ /* dst32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */ /* dst32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-32-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */ /* dst32-32-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */ /* dst32-32-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */ /* dst32-32-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */ /* dst32-32-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */ /* dst32-32-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-32-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-40-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */ /* dst32-40-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */ /* dst32-40-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */ /* dst32-40-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */ /* dst32-40-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */ /* dst32-40-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-40-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-48-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */ /* dst32-48-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */ /* dst32-48-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */ /* dst32-48-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */ /* dst32-48-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */ /* dst32-48-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-48-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */ /* dst32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */ /* dst32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */ /* dst32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */ /* dst32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */ /* dst32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-32-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */ /* dst32-32-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */ /* dst32-32-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */ /* dst32-32-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */ /* dst32-32-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */ /* dst32-32-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-32-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-40-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */ /* dst32-40-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */ /* dst32-40-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */ /* dst32-40-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */ /* dst32-40-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */ /* dst32-40-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-40-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-48-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */ /* dst32-48-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */ /* dst32-48-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */ /* dst32-48-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */ /* dst32-48-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */ /* dst32-48-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-48-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */ /* dst32-16-8-SB-relative-ExtUnprefixed-QI: m32c dsp:8[sb] relative destination QI */ /* dst32-16-16-SB-relative-ExtUnprefixed-QI: m32c dsp:16[sb] relative destination QI */ /* dst32-16-8-FB-relative-ExtUnprefixed-QI: m32c dsp:8[fb] relative destination QI */ /* dst32-16-16-FB-relative-ExtUnprefixed-QI: m32c dsp:16[fb] relative destination QI */ /* dst32-16-8-An-relative-ExtUnprefixed-QI: m32c dsp:8[An] relative destination QI */ /* dst32-16-16-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-16-24-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */ /* dst32-16-8-SB-relative-ExtUnprefixed-HI: m32c dsp:8[sb] relative destination HI */ /* dst32-16-16-SB-relative-ExtUnprefixed-HI: m32c dsp:16[sb] relative destination HI */ /* dst32-16-8-FB-relative-ExtUnprefixed-HI: m32c dsp:8[fb] relative destination HI */ /* dst32-16-16-FB-relative-ExtUnprefixed-HI: m32c dsp:16[fb] relative destination HI */ /* dst32-16-8-An-relative-ExtUnprefixed-HI: m32c dsp:8[An] relative destination HI */ /* dst32-16-16-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst32-16-24-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */ /* dst16-16-16-absolute-QI: m16c absolute address QI */ /* dst16-24-16-absolute-QI: m16c absolute address QI */ /* dst16-32-16-absolute-QI: m16c absolute address QI */ /* dst16-40-16-absolute-QI: m16c absolute address QI */ /* dst16-48-16-absolute-QI: m16c absolute address QI */ /* dst16-16-16-absolute-HI: m16c absolute address HI */ /* dst16-24-16-absolute-HI: m16c absolute address HI */ /* dst16-32-16-absolute-HI: m16c absolute address HI */ /* dst16-40-16-absolute-HI: m16c absolute address HI */ /* dst16-48-16-absolute-HI: m16c absolute address HI */ /* dst16-16-16-absolute-SI: m16c absolute address SI */ /* dst16-24-16-absolute-SI: m16c absolute address SI */ /* dst16-32-16-absolute-SI: m16c absolute address SI */ /* dst16-40-16-absolute-SI: m16c absolute address SI */ /* dst16-48-16-absolute-SI: m16c absolute address SI */ /* dst16-16-16-absolute-Ext-QI: m16c absolute address QI */ /* dst32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */ /* dst32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */ /* dst32-24-16-absolute-Unprefixed-QI: m32c absolute address QI */ /* dst32-24-24-absolute-Unprefixed-QI: m32c absolute address QI */ /* dst32-32-16-absolute-Unprefixed-QI: m32c absolute address QI */ /* dst32-32-24-absolute-Unprefixed-QI: m32c absolute address QI */ /* dst32-40-16-absolute-Unprefixed-QI: m32c absolute address QI */ /* dst32-40-24-absolute-Unprefixed-QI: m32c absolute address QI */ /* dst32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */ /* dst32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */ /* dst32-24-16-absolute-Unprefixed-HI: m32c absolute address HI */ /* dst32-24-24-absolute-Unprefixed-HI: m32c absolute address HI */ /* dst32-32-16-absolute-Unprefixed-HI: m32c absolute address HI */ /* dst32-32-24-absolute-Unprefixed-HI: m32c absolute address HI */ /* dst32-40-16-absolute-Unprefixed-HI: m32c absolute address HI */ /* dst32-40-24-absolute-Unprefixed-HI: m32c absolute address HI */ /* dst32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */ /* dst32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */ /* dst32-24-16-absolute-Unprefixed-SI: m32c absolute address SI */ /* dst32-24-24-absolute-Unprefixed-SI: m32c absolute address SI */ /* dst32-32-16-absolute-Unprefixed-SI: m32c absolute address SI */ /* dst32-32-24-absolute-Unprefixed-SI: m32c absolute address SI */ /* dst32-40-16-absolute-Unprefixed-SI: m32c absolute address SI */ /* dst32-40-24-absolute-Unprefixed-SI: m32c absolute address SI */ /* dst32-24-16-absolute-Prefixed-QI: m32c absolute address QI */ /* dst32-24-24-absolute-Prefixed-QI: m32c absolute address QI */ /* dst32-32-16-absolute-Prefixed-QI: m32c absolute address QI */ /* dst32-32-24-absolute-Prefixed-QI: m32c absolute address QI */ /* dst32-40-16-absolute-Prefixed-QI: m32c absolute address QI */ /* dst32-40-24-absolute-Prefixed-QI: m32c absolute address QI */ /* dst32-48-16-absolute-Prefixed-QI: m32c absolute address QI */ /* dst32-48-24-absolute-Prefixed-QI: m32c absolute address QI */ /* dst32-24-16-absolute-Prefixed-HI: m32c absolute address HI */ /* dst32-24-24-absolute-Prefixed-HI: m32c absolute address HI */ /* dst32-32-16-absolute-Prefixed-HI: m32c absolute address HI */ /* dst32-32-24-absolute-Prefixed-HI: m32c absolute address HI */ /* dst32-40-16-absolute-Prefixed-HI: m32c absolute address HI */ /* dst32-40-24-absolute-Prefixed-HI: m32c absolute address HI */ /* dst32-48-16-absolute-Prefixed-HI: m32c absolute address HI */ /* dst32-48-24-absolute-Prefixed-HI: m32c absolute address HI */ /* dst32-24-16-absolute-Prefixed-SI: m32c absolute address SI */ /* dst32-24-24-absolute-Prefixed-SI: m32c absolute address SI */ /* dst32-32-16-absolute-Prefixed-SI: m32c absolute address SI */ /* dst32-32-24-absolute-Prefixed-SI: m32c absolute address SI */ /* dst32-40-16-absolute-Prefixed-SI: m32c absolute address SI */ /* dst32-40-24-absolute-Prefixed-SI: m32c absolute address SI */ /* dst32-48-16-absolute-Prefixed-SI: m32c absolute address SI */ /* dst32-48-24-absolute-Prefixed-SI: m32c absolute address SI */ /* dst32-16-16-absolute-ExtUnprefixed-QI: m32c absolute address QI */ /* dst32-16-24-absolute-ExtUnprefixed-QI: m32c absolute address QI */ /* dst32-16-16-absolute-ExtUnprefixed-HI: m32c absolute address HI */ /* dst32-16-24-absolute-ExtUnprefixed-HI: m32c absolute address HI */ /* bit16-Rn-direct: m16c Rn direct bit */ /* bit32-Rn-direct-Unprefixed: m32c Rn direct bit */ /* bit32-Rn-direct-Prefixed: m32c Rn direct bit */ /* bit16-An-direct: m16c An direct bit */ /* bit32-An-direct-Unprefixed: m32c An direct bit */ /* bit32-An-direct-Prefixed: m32c An direct bit */ /* bit16-An-indirect: m16c An indirect bit */ /* bit32-An-indirect-Unprefixed: m32c An indirect destination */ /* bit32-An-indirect-Prefixed: m32c An indirect destination */ /* bit16-16-8-SB-relative: m16c dsp:8[sb] relative bit xmode */ /* bit16-16-16-SB-relative: m16c dsp:16[sb] relative bit xmode */ /* bit16-16-8-FB-relative: m16c dsp:8[fb] relative bit xmode */ /* bit16-16-8-An-relative: m16c dsp:8[An] relative bit xmode */ /* bit16-16-16-An-relative: m16c dsp:16[An] relative bit xmode */ /* bit32-16-11-SB-relative-Unprefixed: m32c bit,base:11[sb] relative bit */ /* bit32-16-19-SB-relative-Unprefixed: m32c bit,base:19[sb] relative bit */ /* bit32-16-11-FB-relative-Unprefixed: m32c bit,base:11[fb] relative bit */ /* bit32-16-19-FB-relative-Unprefixed: m32c bit,base:19[fb] relative bit */ /* bit32-16-11-An-relative-Unprefixed: m32c bit,base:11[An] relative bit */ /* bit32-16-19-An-relative-Unprefixed: m32c bit,base:19[An] relative bit */ /* bit32-16-27-An-relative-Unprefixed: m32c bit,base:27[An] relative bit */ /* bit32-24-11-SB-relative-Prefixed: m32c bit,base:11[sb] relative bit */ /* bit32-24-19-SB-relative-Prefixed: m32c bit,base:19[sb] relative bit */ /* bit32-24-11-FB-relative-Prefixed: m32c bit,base:11[fb] relative bit */ /* bit32-24-19-FB-relative-Prefixed: m32c bit,base:19[fb] relative bit */ /* bit32-24-11-An-relative-Prefixed: m32c bit,base:11[An] relative bit */ /* bit32-24-19-An-relative-Prefixed: m32c bit,base:19[An] relative bit */ /* bit32-24-27-An-relative-Prefixed: m32c bit,base:27[An] relative bit */ /* bit16-11-SB-relative-S: m16c bit,base:11[sb] relative bit */ /* Rn16-push-S-derived: m16c r0[lh] for push,pop short version */ /* An16-push-S-derived: m16c r0[lh] for push,pop short version */ /* bit16-16-16-absolute: m16c absolute address */ /* bit32-16-19-absolute-Unprefixed: m32c absolute address bit */ /* bit32-16-27-absolute-Unprefixed: m32c absolute address bit */ /* bit32-24-19-absolute-Prefixed: m32c absolute address bit */ /* bit32-24-27-absolute-Prefixed: m32c absolute address bit */ /* dst16-3-S-R0l-direct-QI: m16c R0l direct QI */ /* dst16-3-S-R0h-direct-QI: m16c R0h direct QI */ /* dst16-3-S-8-8-SB-relative-QI: m16c SB relative QI */ /* dst16-3-S-8-8-FB-relative-QI: m16c FB relative QI */ /* dst16-3-S-8-16-absolute-QI: m16c absolute address QI */ /* dst16-3-S-16-8-SB-relative-QI: m16c SB relative QI */ /* dst16-3-S-16-8-FB-relative-QI: m16c FB relative QI */ /* dst16-3-S-16-16-absolute-QI: m16c absolute address QI */ /* srcdst16-r0l-r0h-S-derived: m16c r0l/r0h operand for short format insns */ /* dst32-2-S-R0l-direct-QI: m32c R0l direct QI */ /* dst32-2-S-R0-direct-HI: m32c R0 direct HI */ /* dst32-1-S-A0-direct-HI: m32c A0 direct HI */ /* dst32-1-S-A1-direct-HI: m32c A1 direct HI */ /* dst32-2-S-8-SB-relative-QI: m32c SB relative for short binary insns */ /* dst32-2-S-8-FB-relative-QI: m32c FB relative for short binary insns */ /* dst32-2-S-16-absolute-QI: m32c absolute address for short binary insns */ /* dst32-2-S-8-SB-relative-HI: m32c SB relative for short binary insns */ /* dst32-2-S-8-FB-relative-HI: m32c FB relative for short binary insns */ /* dst32-2-S-16-absolute-HI: m32c absolute address for short binary insns */ /* dst32-2-S-8-SB-relative-SI: m32c SB relative for short binary insns */ /* dst32-2-S-8-FB-relative-SI: m32c FB relative for short binary insns */ /* dst32-2-S-16-absolute-SI: m32c absolute address for short binary insns */ /* src16-basic-QI: m16c source operand of size QI with no additional fields */ /* src16-basic-HI: m16c source operand of size HI with no additional fields */ /* src32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */ /* src32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */ /* src32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */ /* src32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */ /* src32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */ /* src32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */ /* src32-basic-ExtPrefixed-QI: m32c source operand of size QI with no additional fields */ /* src16-16-8-QI: m16c source operand of size QI with additional 8 bit fields at offset 16 */ /* src16-16-16-QI: m16c source operand of size QI with additional 16 bit fields at offset 16 */ /* src16-16-8-HI: m16c source operand of size HI with additional 8 bit fields at offset 16 */ /* src16-16-16-HI: m16c source operand of size HI with additional 16 bit fields at offset 16 */ /* src32-16-8-Unprefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 16 */ /* src32-16-16-Unprefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */ /* src32-16-24-Unprefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */ /* src32-16-8-Unprefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 16 */ /* src32-16-16-Unprefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */ /* src32-16-24-Unprefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */ /* src32-16-8-Unprefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 16 */ /* src32-16-16-Unprefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */ /* src32-16-24-Unprefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */ /* src32-24-8-Prefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 24 */ /* src32-24-16-Prefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */ /* src32-24-24-Prefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */ /* src32-24-8-Prefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 24 */ /* src32-24-16-Prefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */ /* src32-24-24-Prefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */ /* src32-24-8-Prefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 24 */ /* src32-24-16-Prefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */ /* src32-24-24-Prefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */ /* dst16-basic-QI: m16c destination operand of size QI with no additional fields */ /* dst16-basic-HI: m16c destination operand of size HI with no additional fields */ /* dst16-basic-SI: m16c destination operand of size SI with no additional fields */ /* dst32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */ /* dst32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */ /* dst32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */ /* dst32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */ /* dst32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */ /* dst32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */ /* dst16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */ /* dst16-16-8-QI: m16c destination operand of size QI with additional fields at offset 16 */ /* dst16-16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */ /* dst16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */ /* dst16-16-8-HI: m16c destination operand of size HI with additional fields at offset 16 */ /* dst16-16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */ /* dst16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */ /* dst16-16-8-SI: m16c destination operand of size SI with additional fields at offset 16 */ /* dst16-16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */ /* dst16-16-Ext-QI: m16c destination operand of size QI for 'ext' insns with additional fields at offset 16 */ /* dst16-An-indirect-Mova-HI: m16c addressof An indirect destination HI */ /* dst16-16-8-An-relative-Mova-HI: m16c addressof dsp:8[An] relative destination HI */ /* dst16-16-16-An-relative-Mova-HI: m16c addressof dsp:16[An] relative destination HI */ /* dst16-16-8-SB-relative-Mova-HI: m16c addressof dsp:8[sb] relative destination HI */ /* dst16-16-16-SB-relative-Mova-HI: m16c addressof dsp:16[sb] relative destination HI */ /* dst16-16-8-FB-relative-Mova-HI: m16c addressof dsp:8[fb] relative destination HI */ /* dst16-16-16-absolute-Mova-HI: m16c addressof absolute address HI */ /* dst16-16-Mova-HI: m16c addressof destination operand of size HI with additional fields at offset 16 */ /* dst32-An-indirect-Unprefixed-Mova-SI: m32c addressof An indirect destination SI */ /* dst32-16-8-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[An] relative destination SI */ /* dst32-16-16-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[An] relative destination SI */ /* dst32-16-24-An-relative-Unprefixed-Mova-SI: addressof m32c dsp:16[An] relative destination SI */ /* dst32-16-8-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[sb] relative destination SI */ /* dst32-16-16-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[sb] relative destination SI */ /* dst32-16-8-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[fb] relative destination SI */ /* dst32-16-16-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[fb] relative destination SI */ /* dst32-16-16-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */ /* dst32-16-24-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */ /* dst32-16-Unprefixed-Mova-SI: m32c addressof destination operand of size SI with additional fields at offset 16 */ /* dst32-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */ /* dst32-16-8-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */ /* dst32-16-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */ /* dst32-16-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */ /* dst32-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */ /* dst32-16-8-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */ /* dst32-16-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */ /* dst32-16-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */ /* dst32-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */ /* dst32-16-8-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */ /* dst32-16-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */ /* dst32-16-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */ /* dst32-16-ExtUnprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */ /* dst32-16-ExtUnprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */ /* dst32-16-Unprefixed-Mulex-HI: m32c destination operand of size HI with additional fields at offset 16 */ /* dst16-24-QI: m16c destination operand of size QI with additional fields at offset 24 */ /* dst16-24-HI: m16c destination operand of size HI with additional fields at offset 24 */ /* dst32-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */ /* dst32-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */ /* dst32-24-8-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */ /* dst32-24-16-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */ /* dst32-24-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */ /* dst32-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */ /* dst32-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */ /* dst32-24-8-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */ /* dst32-24-16-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */ /* dst32-24-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */ /* dst32-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */ /* dst32-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */ /* dst32-24-8-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */ /* dst32-24-16-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */ /* dst32-24-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */ /* dst16-32-QI: m16c destination operand of size QI with additional fields at offset 32 */ /* dst16-32-HI: m16c destination operand of size HI with additional fields at offset 32 */ /* dst32-32-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */ /* dst32-32-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */ /* dst32-32-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */ /* dst32-32-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */ /* dst32-32-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */ /* dst32-32-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */ /* dst32-40-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */ /* dst32-40-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */ /* dst32-40-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */ /* dst32-40-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */ /* dst32-40-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */ /* dst32-40-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */ /* dst32-48-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */ /* dst32-48-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */ /* dst32-48-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */ /* bit16-16: m16c bit operand with possible additional fields at offset 24 */ /* bit16-16-basic: m16c bit operand with no additional fields */ /* bit16-16-8: m16c bit operand with possible additional fields at offset 24 */ /* bit16-16-16: m16c bit operand with possible additional fields at offset 24 */ /* bit32-16-Unprefixed: m32c bit operand with possible additional fields at offset 24 */ /* bit32-24-Prefixed: m32c bit operand with possible additional fields at offset 24 */ /* bit32-basic-Unprefixed: m32c bit operand with no additional fields */ /* bit32-16-8-Unprefixed: m32c bit operand with 8 bit additional fields */ /* bit32-16-16-Unprefixed: m32c bit operand with 16 bit additional fields */ /* bit32-16-24-Unprefixed: m32c bit operand with 24 bit additional fields */ /* src16-2-S: m16c source operand of size QI for short format insns */ /* src32-2-S-QI: m32c source operand of size QI for short format insns */ /* src32-2-S-HI: m32c source operand of size QI for short format insns */ /* Dst16-3-S-8: m16c destination operand of size QI for short format insns */ /* Dst16-3-S-16: m16c destination operand of size QI for short format insns */ /* srcdst16-r0l-r0h-S: m16c r0l/r0h operand of size QI for short format insns */ /* dst32-2-S-basic-QI: m32c r0l operand of size QI for short format binary insns */ /* dst32-2-S-basic-HI: m32c r0 operand of size HI for short format binary insns */ /* dst32-2-S-8-QI: m32c operand of size */ /* dst32-2-S-16-QI: m32c operand of size */ /* dst32-2-S-8-HI: m32c operand of size */ /* dst32-2-S-16-HI: m32c operand of size */ /* dst32-2-S-8-SI: m32c operand of size */ /* dst32-2-S-16-SI: m32c operand of size */ /* dst32-an-S: m32c An operand for short format binary insns */ /* bit16-11-S: m16c bit operand for short format insns */ /* Rn16-push-S-anyof: m16c bit operand for short format insns */ /* An16-push-S-anyof: m16c bit operand for short format insns */ /* sentinel */ { 0, 0, 0, 0, 0, { 0, { (const PTR) 0 } }, { 0, { 0 } } } }; #undef A /* The instruction table. */ #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define A(a) (1 << CGEN_INSN_##a) #else #define A(a) (1 << CGEN_INSN_/**/a) #endif static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = { /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ { 0, 0, 0, 0, {0, {0}} }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w $Dst32RnExtUnprefixedHI */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-HI", "exts.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w $Dst32AnUnprefixedSI */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "exts32.w-16-ExtUnprefixed-dst32-An-direct-Unprefixed-SI", "exts.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w [$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-HI", "exts.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-HI", "exts.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-HI", "exts.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-HI", "exts.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w ${Dsp-16-u8}[sb] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-HI", "exts.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w ${Dsp-16-u16}[sb] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-HI", "exts.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w ${Dsp-16-s8}[fb] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-HI", "exts.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w ${Dsp-16-s16}[fb] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-HI", "exts.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w ${Dsp-16-u16} */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-HI", "exts.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.w ${Dsp-16-u24} */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-HI", "exts.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Dst32RnExtUnprefixedQI */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-QI", "exts.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Dst32AnUnprefixedHI */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "exts32.b-16-ExtUnprefixed-dst32-An-direct-Unprefixed-HI", "exts.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b [$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-QI", "exts.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-QI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-QI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-QI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-16-u8}[sb] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-QI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-16-u16}[sb] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-QI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-16-s8}[fb] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-QI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-16-s16}[fb] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-QI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-16-u16} */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-QI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b ${Dsp-16-u24} */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-QI", "exts.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* exts.b $Dst16RnExtQI */ { M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, "exts16.b-16-Ext-dst16-Rn-direct-Ext-QI", "exts.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* exts.b [$Dst16An] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, "exts16.b-16-Ext-dst16-An-indirect-Ext-QI", "exts.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* exts.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-An-relative-Ext-QI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* exts.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-An-relative-Ext-QI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* exts.b ${Dsp-16-u8}[sb] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-SB-relative-Ext-QI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* exts.b ${Dsp-16-u16}[sb] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-SB-relative-Ext-QI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* exts.b ${Dsp-16-s8}[fb] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-FB-relative-Ext-QI", "exts.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* exts.b ${Dsp-16-u16} */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-absolute-Ext-QI", "exts.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "xor.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "xor.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "xor.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xor.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-Rn-direct-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-An-direct-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "xor16.w-imm-G-basic-dst16-An-indirect-HI", "xor.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "xor.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "xor16.w-imm-G-16-16-dst16-16-16-absolute-HI", "xor.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-Rn-direct-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-An-direct-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "xor16.b-imm-G-basic-dst16-An-indirect-QI", "xor.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "xor.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "xor16.b-imm-G-16-16-dst16-16-16-absolute-QI", "xor.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r3,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r2,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a1,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w a0,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r1,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r0,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1h,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0h,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a1,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b a0,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r1l,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.b r0l,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* xchg.w r3,$Dst16RnHI */ { M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, "xchg16w-r3-dst16-Rn-direct-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r3,$Dst16AnHI */ { M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, "xchg16w-r3-dst16-An-direct-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r3,[$Dst16An] */ { M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI, "xchg16w-r3-dst16-An-indirect-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r3,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-8-An-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r3,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-16-An-relative-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r3,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-SB-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r3,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-16-SB-relative-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r3,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-FB-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r3,${Dsp-16-u16} */ { M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, "xchg16w-r3-dst16-16-16-absolute-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r2,$Dst16RnHI */ { M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, "xchg16w-r2-dst16-Rn-direct-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r2,$Dst16AnHI */ { M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI, "xchg16w-r2-dst16-An-direct-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r2,[$Dst16An] */ { M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, "xchg16w-r2-dst16-An-indirect-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r2,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-8-An-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r2,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-16-An-relative-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r2,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-SB-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r2,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-16-SB-relative-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r2,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-FB-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r2,${Dsp-16-u16} */ { M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, "xchg16w-r2-dst16-16-16-absolute-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r1,$Dst16RnHI */ { M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI, "xchg16w-r1-dst16-Rn-direct-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r1,$Dst16AnHI */ { M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, "xchg16w-r1-dst16-An-direct-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r1,[$Dst16An] */ { M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, "xchg16w-r1-dst16-An-indirect-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r1,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-8-An-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r1,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-16-An-relative-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r1,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-SB-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r1,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-16-SB-relative-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r1,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-FB-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r1,${Dsp-16-u16} */ { M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r0,$Dst16RnHI */ { M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, "xchg16w-r0-dst16-Rn-direct-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r0,$Dst16AnHI */ { M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, "xchg16w-r0-dst16-An-direct-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r0,[$Dst16An] */ { M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, "xchg16w-r0-dst16-An-indirect-HI", "xchg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r0,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-8-An-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r0,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-16-An-relative-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r0,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-SB-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r0,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-16-SB-relative-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r0,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-FB-relative-HI", "xchg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.w r0,${Dsp-16-u16} */ { M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, "xchg16w-r0-dst16-16-16-absolute-HI", "xchg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1h,$Dst16RnQI */ { M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, "xchg16b-r1h-dst16-Rn-direct-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1h,$Dst16AnQI */ { M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, "xchg16b-r1h-dst16-An-direct-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1h,[$Dst16An] */ { M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI, "xchg16b-r1h-dst16-An-indirect-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-An-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-An-relative-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-SB-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-SB-relative-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-FB-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1h,${Dsp-16-u16} */ { M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1h-dst16-16-16-absolute-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1l,$Dst16RnQI */ { M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, "xchg16b-r1l-dst16-Rn-direct-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1l,$Dst16AnQI */ { M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI, "xchg16b-r1l-dst16-An-direct-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1l,[$Dst16An] */ { M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, "xchg16b-r1l-dst16-An-indirect-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-An-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-An-relative-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1l,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-SB-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1l,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-SB-relative-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1l,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-FB-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r1l,${Dsp-16-u16} */ { M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1l-dst16-16-16-absolute-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0h,$Dst16RnQI */ { M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI, "xchg16b-r0h-dst16-Rn-direct-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0h,$Dst16AnQI */ { M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, "xchg16b-r0h-dst16-An-direct-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0h,[$Dst16An] */ { M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, "xchg16b-r0h-dst16-An-indirect-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-An-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-An-relative-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0h,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-SB-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0h,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-SB-relative-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0h,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-FB-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0h,${Dsp-16-u16} */ { M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0h-dst16-16-16-absolute-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0l,$Dst16RnQI */ { M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, "xchg16b-r0l-dst16-Rn-direct-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0l,$Dst16AnQI */ { M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, "xchg16b-r0l-dst16-An-direct-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0l,[$Dst16An] */ { M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, "xchg16b-r0l-dst16-An-indirect-QI", "xchg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-An-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-An-relative-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-SB-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-SB-relative-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-FB-relative-QI", "xchg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* xchg.b r0l,${Dsp-16-u16} */ { M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0l-dst16-16-16-absolute-QI", "xchg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "tst32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "tst32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "tst32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "tst32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "tst.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "tst.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} [$Src16An],$Dst16RnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "tst.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "tst.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "tst.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} [$Src16An],$Dst16AnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "tst.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16RnHI,[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "tst.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16AnHI,[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "tst.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} [$Src16An],[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "tst.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "tst.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} [$Src16An],$Dst16RnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} [$Src16An],$Dst16AnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16RnQI,[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16AnQI,[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} [$Src16An],[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "tst.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "tst.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "tst.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* tst.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-Rn-direct-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-An-direct-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "tst16.w-imm-G-basic-dst16-An-indirect-HI", "tst.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "tst.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "tst16.w-imm-G-16-16-dst16-16-16-absolute-HI", "tst.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-Rn-direct-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-An-direct-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "tst16.b-imm-G-basic-dst16-An-indirect-QI", "tst.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "tst.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "tst16.b-imm-G-16-16-dst16-16-16-absolute-QI", "tst.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "subx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "subx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* subx${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "subx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stzx.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stzx.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stzx.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stzx.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stzx.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stzx.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stzx.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stzx.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stzx.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */ { M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stzx.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stzx.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */ { M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stzx.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stzx.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stzx.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stzx.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stzx.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stzx.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stzx.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stzx.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stzx.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stzx.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */ { M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stzx.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stzx.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */ { M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stzx.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stz.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stz.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stz.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stz.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stz.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stz.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stz.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stz.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stz.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stz.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stz.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stz.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stz.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stz.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stz.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stz.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stz.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stz.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stz.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stz.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stz.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stz.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stz.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stz.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stz${S} #${Imm-8-QI},r0l */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stz", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* stz${S} #${Imm-8-QI},r0h */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stz", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* stz${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stnz.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stnz.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stnz.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stnz.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stnz.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stnz.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stnz.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stnz.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stnz.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stnz.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stnz.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stnz.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stnz.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stnz.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stnz.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stnz.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stnz.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stnz.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stnz.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stnz.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stnz.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stnz.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stnz.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stnz.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* stnz${S} #${Imm-8-QI},r0l */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stnz", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* stnz${S} #${Imm-8-QI},r0h */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stnz", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stnz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stnz", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stnz", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shlnc.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shlnc.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shlnc.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shlnc.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shlnc.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shlnc.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shlnc.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shlnc.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shlnc.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shlnc.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shlnc.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shlnc.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,$Dst32RnUnprefixedSI */ { M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-Rn-direct-Unprefixed-SI", "shl.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,$Dst32AnUnprefixedSI */ { M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-direct-Unprefixed-SI", "shl.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-indirect-Unprefixed-SI", "shl.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,${Dsp-16-u16} */ { M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l r1h,${Dsp-16-u24} */ { M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shl.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shl.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shl.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,$Dst32RnUnprefixedHI */ { M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,$Dst32AnUnprefixedHI */ { M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-direct-Unprefixed-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-indirect-Unprefixed-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,${Dsp-16-u16} */ { M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,${Dsp-16-u24} */ { M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,$Dst32RnUnprefixedQI */ { M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,$Dst32AnUnprefixedQI */ { M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-direct-Unprefixed-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-indirect-Unprefixed-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,${Dsp-16-u16} */ { M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b r1h,${Dsp-16-u24} */ { M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w r1h,$Dst16RnHI */ { M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI, "shl16.w-dst-dst16-Rn-direct-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w r1h,$Dst16AnHI */ { M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, "shl16.w-dst-dst16-An-direct-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w r1h,[$Dst16An] */ { M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, "shl16.w-dst-dst16-An-indirect-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-8-An-relative-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-16-An-relative-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-SB-relative-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-16-SB-relative-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-FB-relative-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w r1h,${Dsp-16-u16} */ { M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI, "shl16.w-dst-dst16-16-16-absolute-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b r1h,$Dst16RnQI */ { M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, "shl16.b-dst-dst16-Rn-direct-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b r1h,$Dst16AnQI */ { M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, "shl16.b-dst-dst16-An-direct-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b r1h,[$Dst16An] */ { M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, "shl16.b-dst-dst16-An-indirect-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-8-An-relative-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-16-An-relative-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-SB-relative-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-16-SB-relative-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-FB-relative-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b r1h,${Dsp-16-u16} */ { M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, "shl16.b-dst-dst16-16-16-absolute-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-Rn-direct-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-direct-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-indirect-HI", "shl.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "shl.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "shl16.w-imm4-Q-16-dst16-16-16-absolute-HI", "shl.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-Rn-direct-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-direct-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-indirect-QI", "shl.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "shl.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "shl16.b-imm4-Q-16-dst16-16-16-absolute-QI", "shl.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shanc.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shanc.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shanc.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shanc.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shanc.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shanc.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shanc.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shanc.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shanc.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shanc.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shanc.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shanc.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,$Dst32RnUnprefixedSI */ { M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-Rn-direct-Unprefixed-SI", "sha.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,$Dst32AnUnprefixedSI */ { M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-direct-Unprefixed-SI", "sha.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-indirect-Unprefixed-SI", "sha.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,${Dsp-16-u16} */ { M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l r1h,${Dsp-16-u24} */ { M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sha.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sha.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sha.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,$Dst32RnUnprefixedHI */ { M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,$Dst32AnUnprefixedHI */ { M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-direct-Unprefixed-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-indirect-Unprefixed-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,${Dsp-16-u16} */ { M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,${Dsp-16-u24} */ { M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,$Dst32RnUnprefixedQI */ { M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,$Dst32AnUnprefixedQI */ { M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-direct-Unprefixed-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-indirect-Unprefixed-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,${Dsp-16-u16} */ { M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b r1h,${Dsp-16-u24} */ { M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w r1h,$Dst16RnHI */ { M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI, "sha16.w-dst-dst16-Rn-direct-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w r1h,$Dst16AnHI */ { M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, "sha16.w-dst-dst16-An-direct-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w r1h,[$Dst16An] */ { M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, "sha16.w-dst-dst16-An-indirect-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-8-An-relative-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-16-An-relative-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-SB-relative-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-16-SB-relative-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-FB-relative-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w r1h,${Dsp-16-u16} */ { M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI, "sha16.w-dst-dst16-16-16-absolute-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b r1h,$Dst16RnQI */ { M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, "sha16.b-dst-dst16-Rn-direct-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b r1h,$Dst16AnQI */ { M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, "sha16.b-dst-dst16-An-direct-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b r1h,[$Dst16An] */ { M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, "sha16.b-dst-dst16-An-indirect-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-8-An-relative-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-16-An-relative-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-SB-relative-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-16-SB-relative-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-FB-relative-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b r1h,${Dsp-16-u16} */ { M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, "sha16.b-dst-dst16-16-16-absolute-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-Rn-direct-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-direct-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-indirect-HI", "sha.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "sha.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "sha16.w-imm4-Q-16-dst16-16-16-absolute-HI", "sha.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-Rn-direct-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-direct-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-indirect-QI", "sha.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "sha.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "sha16.b-imm4-Q-16-dst16-16-16-absolute-QI", "sha.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sc${sccond32} $Dst32RnUnprefixedHI */ { M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-Rn-direct-Unprefixed-HI", "sc", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} $Dst32AnUnprefixedHI */ { M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-An-direct-Unprefixed-HI", "sc", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} [$Dst32AnUnprefixed] */ { M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, "sccnd-dst32-An-indirect-Unprefixed-HI", "sc", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-An-relative-Unprefixed-HI", "sc", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-An-relative-Unprefixed-HI", "sc", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-24-An-relative-Unprefixed-HI", "sc", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} ${Dsp-16-u8}[sb] */ { M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-SB-relative-Unprefixed-HI", "sc", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} ${Dsp-16-u16}[sb] */ { M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-SB-relative-Unprefixed-HI", "sc", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} ${Dsp-16-s8}[fb] */ { M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-FB-relative-Unprefixed-HI", "sc", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} ${Dsp-16-s16}[fb] */ { M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-FB-relative-Unprefixed-HI", "sc", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} ${Dsp-16-u16} */ { M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-16-absolute-Unprefixed-HI", "sc", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sc${sccond32} ${Dsp-16-u24} */ { M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */ { M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */ { M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ { M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */ { M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */ { M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ { M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */ { M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */ { M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ { M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */ { M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */ { M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ { M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24, { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} [$Src16An],$Dst16RnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sbb.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sbb.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sbb.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} [$Src16An],$Dst16AnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sbb.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16RnHI,[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sbb.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16AnHI,[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sbb.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} [$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sbb.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} [$Src16An],$Dst16RnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sbb.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sbb.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sbb.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} [$Src16An],$Dst16AnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sbb.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16RnQI,[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sbb.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16AnQI,[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sbb.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} [$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sbb.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-Rn-direct-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-direct-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-indirect-HI", "sbb.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sbb.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sbb.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-Rn-direct-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-direct-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-indirect-QI", "sbb.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sbb.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w r1h,$Dst32RnUnprefixedHI */ { M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,$Dst32AnUnprefixedHI */ { M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-direct-Unprefixed-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-indirect-Unprefixed-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,${Dsp-16-u16} */ { M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,${Dsp-16-u24} */ { M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,$Dst32RnUnprefixedQI */ { M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,$Dst32AnUnprefixedQI */ { M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-direct-Unprefixed-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-indirect-Unprefixed-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,${Dsp-16-u16} */ { M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b r1h,${Dsp-16-u24} */ { M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w r1h,$Dst16RnHI */ { M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, "rot16.w-dst-dst16-Rn-direct-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w r1h,$Dst16AnHI */ { M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, "rot16.w-dst-dst16-An-direct-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w r1h,[$Dst16An] */ { M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI, "rot16.w-dst-dst16-An-indirect-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-8-An-relative-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-16-An-relative-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-SB-relative-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-16-SB-relative-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-FB-relative-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w r1h,${Dsp-16-u16} */ { M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b r1h,$Dst16RnQI */ { M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, "rot16.b-dst-dst16-Rn-direct-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b r1h,$Dst16AnQI */ { M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI, "rot16.b-dst-dst16-An-direct-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b r1h,[$Dst16An] */ { M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, "rot16.b-dst-dst16-An-indirect-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-8-An-relative-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-16-An-relative-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-SB-relative-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-16-SB-relative-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-FB-relative-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b r1h,${Dsp-16-u16} */ { M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, "rot16.b-dst-dst16-16-16-absolute-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-Rn-direct-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-direct-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-indirect-HI", "rot.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "rot.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "rot16.w-imm4-Q-16-dst16-16-16-absolute-HI", "rot.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-Rn-direct-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-direct-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-indirect-QI", "rot.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "rot.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "rot16.b-imm4-Q-16-dst16-16-16-absolute-QI", "rot.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.w $Dst32RnUnprefixedHI */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rorc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w $Dst32AnUnprefixedHI */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rorc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w [$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rorc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rorc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rorc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rorc.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w ${Dsp-16-u8}[sb] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rorc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w ${Dsp-16-u16}[sb] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rorc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w ${Dsp-16-s8}[fb] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rorc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w ${Dsp-16-s16}[fb] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rorc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w ${Dsp-16-u16} */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rorc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w ${Dsp-16-u24} */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rorc.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b $Dst32RnUnprefixedQI */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rorc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b $Dst32AnUnprefixedQI */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rorc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b [$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rorc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rorc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rorc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rorc.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b ${Dsp-16-u8}[sb] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rorc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b ${Dsp-16-u16}[sb] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rorc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b ${Dsp-16-s8}[fb] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rorc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b ${Dsp-16-s16}[fb] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rorc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b ${Dsp-16-u16} */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rorc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.b ${Dsp-16-u24} */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rorc.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rorc.w $Dst16RnHI */ { M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, "rorc16.w-16-dst16-Rn-direct-HI", "rorc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.w $Dst16AnHI */ { M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, "rorc16.w-16-dst16-An-direct-HI", "rorc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.w [$Dst16An] */ { M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI, "rorc16.w-16-dst16-An-indirect-HI", "rorc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-8-An-relative-HI", "rorc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-16-An-relative-HI", "rorc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.w ${Dsp-16-u8}[sb] */ { M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-SB-relative-HI", "rorc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.w ${Dsp-16-u16}[sb] */ { M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-16-SB-relative-HI", "rorc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.w ${Dsp-16-s8}[fb] */ { M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-FB-relative-HI", "rorc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.w ${Dsp-16-u16} */ { M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, "rorc16.w-16-dst16-16-16-absolute-HI", "rorc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.b $Dst16RnQI */ { M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, "rorc16.b-16-dst16-Rn-direct-QI", "rorc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.b $Dst16AnQI */ { M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI, "rorc16.b-16-dst16-An-direct-QI", "rorc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.b [$Dst16An] */ { M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, "rorc16.b-16-dst16-An-indirect-QI", "rorc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-8-An-relative-QI", "rorc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-16-An-relative-QI", "rorc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.b ${Dsp-16-u8}[sb] */ { M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-SB-relative-QI", "rorc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.b ${Dsp-16-u16}[sb] */ { M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-16-SB-relative-QI", "rorc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.b ${Dsp-16-s8}[fb] */ { M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-FB-relative-QI", "rorc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rorc.b ${Dsp-16-u16} */ { M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, "rorc16.b-16-dst16-16-16-absolute-QI", "rorc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.w $Dst32RnUnprefixedHI */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rolc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w $Dst32AnUnprefixedHI */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rolc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w [$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rolc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rolc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rolc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rolc.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w ${Dsp-16-u8}[sb] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rolc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w ${Dsp-16-u16}[sb] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rolc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w ${Dsp-16-s8}[fb] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rolc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w ${Dsp-16-s16}[fb] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rolc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w ${Dsp-16-u16} */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rolc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w ${Dsp-16-u24} */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rolc.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b $Dst32RnUnprefixedQI */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rolc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b $Dst32AnUnprefixedQI */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rolc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b [$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rolc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rolc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rolc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rolc.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b ${Dsp-16-u8}[sb] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rolc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b ${Dsp-16-u16}[sb] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rolc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b ${Dsp-16-s8}[fb] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rolc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b ${Dsp-16-s16}[fb] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rolc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b ${Dsp-16-u16} */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rolc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.b ${Dsp-16-u24} */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rolc.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* rolc.w $Dst16RnHI */ { M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI, "rolc16.w-16-dst16-Rn-direct-HI", "rolc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.w $Dst16AnHI */ { M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, "rolc16.w-16-dst16-An-direct-HI", "rolc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.w [$Dst16An] */ { M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, "rolc16.w-16-dst16-An-indirect-HI", "rolc.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-8-An-relative-HI", "rolc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-16-An-relative-HI", "rolc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.w ${Dsp-16-u8}[sb] */ { M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-SB-relative-HI", "rolc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.w ${Dsp-16-u16}[sb] */ { M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-16-SB-relative-HI", "rolc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.w ${Dsp-16-s8}[fb] */ { M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-FB-relative-HI", "rolc.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.w ${Dsp-16-u16} */ { M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI, "rolc16.w-16-dst16-16-16-absolute-HI", "rolc.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.b $Dst16RnQI */ { M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, "rolc16.b-16-dst16-Rn-direct-QI", "rolc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.b $Dst16AnQI */ { M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, "rolc16.b-16-dst16-An-direct-QI", "rolc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.b [$Dst16An] */ { M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, "rolc16.b-16-dst16-An-indirect-QI", "rolc.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-8-An-relative-QI", "rolc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-16-An-relative-QI", "rolc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.b ${Dsp-16-u8}[sb] */ { M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-SB-relative-QI", "rolc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.b ${Dsp-16-u16}[sb] */ { M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-16-SB-relative-QI", "rolc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.b ${Dsp-16-s8}[fb] */ { M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-FB-relative-QI", "rolc.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* rolc.b ${Dsp-16-u16} */ { M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, "rolc16.b-16-dst16-16-16-absolute-QI", "rolc.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pusha [$Dst32AnUnprefixed] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-An-indirect-Unprefixed-Mova-SI", "pusha", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-An-relative-Unprefixed-Mova-SI", "pusha", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-An-relative-Unprefixed-Mova-SI", "pusha", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-An-relative-Unprefixed-Mova-SI", "pusha", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "pusha", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "pusha", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "pusha", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha ${Dsp-16-s16}[fb] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "pusha", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha ${Dsp-16-u16} */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-absolute-Unprefixed-Mova-SI", "pusha", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha ${Dsp-16-u24} */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-absolute-Unprefixed-Mova-SI", "pusha", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pusha [$Dst16An] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI, "pusha16-16-Mova-dst16-An-indirect-Mova-HI", "pusha", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pusha ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-An-relative-Mova-HI", "pusha", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pusha ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-An-relative-Mova-HI", "pusha", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pusha ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-SB-relative-Mova-HI", "pusha", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pusha ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-SB-relative-Mova-HI", "pusha", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pusha ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-FB-relative-Mova-HI", "pusha", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pusha ${Dsp-16-u16} */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-absolute-Mova-HI", "pusha", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.l $Dst32RnUnprefixedSI */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "push.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l $Dst32AnUnprefixedSI */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "push.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l [$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "push.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "push.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "push.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "push.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "push.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "push.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "push.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l ${Dsp-16-s16}[fb] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "push.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l ${Dsp-16-u16} */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "push.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.l ${Dsp-16-u24} */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "push.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w${S} ${An16-push-S} */ { M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, "push16.b-s-an-An16-push-S-derived", "push.w", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b${S} ${Rn16-push-S} */ { M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED, "push16.b-s-rn-Rn16-push-S-derived", "push.b", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.w $Dst32RnUnprefixedHI */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "push.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w $Dst32AnUnprefixedHI */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "push.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w [$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "push.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "push.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "push.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "push.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "push.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "push.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "push.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w ${Dsp-16-s16}[fb] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "push.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w ${Dsp-16-u16} */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "push.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w ${Dsp-16-u24} */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "push.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b $Dst32RnUnprefixedQI */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "push.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b $Dst32AnUnprefixedQI */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "push.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b [$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "push.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "push.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "push.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "push.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "push.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "push.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "push.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b ${Dsp-16-s16}[fb] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "push.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b ${Dsp-16-u16} */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "push.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.b ${Dsp-16-u24} */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* push.w $Dst16RnHI */ { M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.w $Dst16AnHI */ { M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.w [$Dst16An] */ { M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.w ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.w ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.w ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.w ${Dsp-16-u16} */ { M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b $Dst16RnQI */ { M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b $Dst16AnQI */ { M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b [$Dst16An] */ { M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* push.b ${Dsp-16-u16} */ { M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w${S} ${An16-push-S} */ { M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, "pop16.b-s-an-An16-push-S-derived", "pop.w", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b${S} ${Rn16-push-S} */ { M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED, "pop16.b-s-rn-Rn16-push-S-derived", "pop.b", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w $Dst32RnUnprefixedHI */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "pop.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w $Dst32AnUnprefixedHI */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "pop.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w [$Dst32AnUnprefixed] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "pop.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "pop.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "pop.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "pop.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w ${Dsp-16-u8}[sb] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "pop.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w ${Dsp-16-u16}[sb] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "pop.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w ${Dsp-16-s8}[fb] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "pop.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w ${Dsp-16-s16}[fb] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "pop.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w ${Dsp-16-u16} */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "pop.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w ${Dsp-16-u24} */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "pop.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b $Dst32RnUnprefixedQI */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "pop.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b $Dst32AnUnprefixedQI */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "pop.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b [$Dst32AnUnprefixed] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "pop.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "pop.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "pop.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "pop.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b ${Dsp-16-u8}[sb] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "pop.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b ${Dsp-16-u16}[sb] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "pop.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b ${Dsp-16-s8}[fb] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "pop.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b ${Dsp-16-s16}[fb] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "pop.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b ${Dsp-16-u16} */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "pop.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.b ${Dsp-16-u24} */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "pop.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* pop.w $Dst16RnHI */ { M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, "pop16.w-16-dst16-Rn-direct-HI", "pop.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w $Dst16AnHI */ { M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, "pop16.w-16-dst16-An-direct-HI", "pop.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w [$Dst16An] */ { M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, "pop16.w-16-dst16-An-indirect-HI", "pop.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI, "pop16.w-16-dst16-16-8-An-relative-HI", "pop.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, "pop16.w-16-dst16-16-16-An-relative-HI", "pop.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w ${Dsp-16-u8}[sb] */ { M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, "pop16.w-16-dst16-16-8-SB-relative-HI", "pop.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w ${Dsp-16-u16}[sb] */ { M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, "pop16.w-16-dst16-16-16-SB-relative-HI", "pop.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w ${Dsp-16-s8}[fb] */ { M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI, "pop16.w-16-dst16-16-8-FB-relative-HI", "pop.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.w ${Dsp-16-u16} */ { M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, "pop16.w-16-dst16-16-16-absolute-HI", "pop.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b $Dst16RnQI */ { M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, "pop16.b-16-dst16-Rn-direct-QI", "pop.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b $Dst16AnQI */ { M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, "pop16.b-16-dst16-An-direct-QI", "pop.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b [$Dst16An] */ { M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI, "pop16.b-16-dst16-An-indirect-QI", "pop.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, "pop16.b-16-dst16-16-8-An-relative-QI", "pop.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, "pop16.b-16-dst16-16-16-An-relative-QI", "pop.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b ${Dsp-16-u8}[sb] */ { M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, "pop16.b-16-dst16-16-8-SB-relative-QI", "pop.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b ${Dsp-16-u16}[sb] */ { M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI, "pop16.b-16-dst16-16-16-SB-relative-QI", "pop.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b ${Dsp-16-s8}[fb] */ { M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, "pop16.b-16-dst16-16-8-FB-relative-QI", "pop.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* pop.b ${Dsp-16-u16} */ { M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, "pop16.b-16-dst16-16-16-absolute-QI", "pop.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "or.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "or32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "or32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "or.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "or32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "or32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${S} #${Imm-8-QI},r0h */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "or.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "or.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "or.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* or.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "or16.w-imm-G-basic-dst16-Rn-direct-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "or16.w-imm-G-basic-dst16-An-direct-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "or16.w-imm-G-basic-dst16-An-indirect-HI", "or.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "or.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "or16.w-imm-G-16-16-dst16-16-16-absolute-HI", "or.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "or16.b-imm-G-basic-dst16-Rn-direct-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "or16.b-imm-G-basic-dst16-An-direct-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "or16.b-imm-G-basic-dst16-An-indirect-QI", "or.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "or.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.w $Dst32RnUnprefixedHI */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w $Dst32AnUnprefixedHI */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w [$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w ${Dsp-16-u8}[sb] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w ${Dsp-16-u16}[sb] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w ${Dsp-16-s8}[fb] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w ${Dsp-16-s16}[fb] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w ${Dsp-16-u16} */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w ${Dsp-16-u24} */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b $Dst32RnUnprefixedQI */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b $Dst32AnUnprefixedQI */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b [$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b ${Dsp-16-u8}[sb] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b ${Dsp-16-u16}[sb] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b ${Dsp-16-s8}[fb] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b ${Dsp-16-s16}[fb] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b ${Dsp-16-u16} */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.b ${Dsp-16-u24} */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* not.w $Dst16RnHI */ { M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.w $Dst16AnHI */ { M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.w [$Dst16An] */ { M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.w ${Dsp-16-u8}[sb] */ { M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.w ${Dsp-16-u16}[sb] */ { M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.w ${Dsp-16-s8}[fb] */ { M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.w ${Dsp-16-u16} */ { M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.b $Dst16RnQI */ { M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.b $Dst16AnQI */ { M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.b [$Dst16An] */ { M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.b ${Dsp-16-u8}[sb] */ { M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.b ${Dsp-16-u16}[sb] */ { M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.b ${Dsp-16-s8}[fb] */ { M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* not.b ${Dsp-16-u16} */ { M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.w $Dst32RnUnprefixedHI */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "neg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w $Dst32AnUnprefixedHI */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "neg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w [$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "neg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "neg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "neg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "neg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w ${Dsp-16-u8}[sb] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "neg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w ${Dsp-16-u16}[sb] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "neg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w ${Dsp-16-s8}[fb] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "neg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w ${Dsp-16-s16}[fb] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "neg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w ${Dsp-16-u16} */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "neg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w ${Dsp-16-u24} */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "neg.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b $Dst32RnUnprefixedQI */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "neg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b $Dst32AnUnprefixedQI */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "neg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b [$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "neg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "neg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "neg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "neg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b ${Dsp-16-u8}[sb] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "neg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b ${Dsp-16-u16}[sb] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "neg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b ${Dsp-16-s8}[fb] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "neg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b ${Dsp-16-s16}[fb] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "neg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b ${Dsp-16-u16} */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "neg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.b ${Dsp-16-u24} */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "neg.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* neg.w $Dst16RnHI */ { M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, "neg16.w-16-dst16-Rn-direct-HI", "neg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.w $Dst16AnHI */ { M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, "neg16.w-16-dst16-An-direct-HI", "neg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.w [$Dst16An] */ { M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, "neg16.w-16-dst16-An-indirect-HI", "neg.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, "neg16.w-16-dst16-16-8-An-relative-HI", "neg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, "neg16.w-16-dst16-16-16-An-relative-HI", "neg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.w ${Dsp-16-u8}[sb] */ { M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, "neg16.w-16-dst16-16-8-SB-relative-HI", "neg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.w ${Dsp-16-u16}[sb] */ { M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, "neg16.w-16-dst16-16-16-SB-relative-HI", "neg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.w ${Dsp-16-s8}[fb] */ { M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, "neg16.w-16-dst16-16-8-FB-relative-HI", "neg.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.w ${Dsp-16-u16} */ { M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, "neg16.w-16-dst16-16-16-absolute-HI", "neg.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.b $Dst16RnQI */ { M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, "neg16.b-16-dst16-Rn-direct-QI", "neg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.b $Dst16AnQI */ { M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, "neg16.b-16-dst16-An-direct-QI", "neg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.b [$Dst16An] */ { M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, "neg16.b-16-dst16-An-indirect-QI", "neg.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, "neg16.b-16-dst16-16-8-An-relative-QI", "neg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, "neg16.b-16-dst16-16-16-An-relative-QI", "neg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.b ${Dsp-16-u8}[sb] */ { M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, "neg16.b-16-dst16-16-8-SB-relative-QI", "neg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.b ${Dsp-16-u16}[sb] */ { M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, "neg16.b-16-dst16-16-16-SB-relative-QI", "neg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.b ${Dsp-16-s8}[fb] */ { M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, "neg16.b-16-dst16-16-8-FB-relative-QI", "neg.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* neg.b ${Dsp-16-u16} */ { M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, "neg16.b-16-dst16-16-16-absolute-QI", "neg.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mulu.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mulu.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-Rn-direct-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-direct-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-indirect-HI", "mulu.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mulu.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mulu.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-Rn-direct-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-direct-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-indirect-QI", "mulu.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mulu.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mulu.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mulex $R3 */ { M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, "mulex-dst32-R3-direct-Unprefixed-HI", "mulex", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex $Dst32AnUnprefixedHI */ { M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, "mulex-dst32-An-direct-Unprefixed-HI", "mulex", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex [$Dst32AnUnprefixed] */ { M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulex-dst32-An-indirect-Unprefixed-HI", "mulex", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-An-relative-Unprefixed-HI", "mulex", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-An-relative-Unprefixed-HI", "mulex", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-24-An-relative-Unprefixed-HI", "mulex", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex ${Dsp-16-u8}[sb] */ { M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-SB-relative-Unprefixed-HI", "mulex", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex ${Dsp-16-u16}[sb] */ { M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-SB-relative-Unprefixed-HI", "mulex", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex ${Dsp-16-s8}[fb] */ { M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-FB-relative-Unprefixed-HI", "mulex", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex ${Dsp-16-s16}[fb] */ { M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-FB-relative-Unprefixed-HI", "mulex", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex ${Dsp-16-u16} */ { M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-16-absolute-Unprefixed-HI", "mulex", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mulex ${Dsp-16-u24} */ { M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-24-absolute-Unprefixed-HI", "mulex", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mul.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mul.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mul.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mul.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-Rn-direct-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-An-direct-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mul16.w-imm-G-basic-dst16-An-indirect-HI", "mul.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mul.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mul16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mul.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-Rn-direct-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-An-direct-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mul16.b-imm-G-basic-dst16-An-indirect-QI", "mul.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mul.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mul16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mul.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "movx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "movx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "movx", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "movx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "movx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "movx", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "movx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "movx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "movx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "movx", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "movx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movx${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "movx", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh $Dst32RnPrefixedQI,r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh $Dst32AnPrefixedQI,r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-direct-Prefixed-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh [$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh ${Dsp-24-u8}[sb],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh ${Dsp-24-u16}[sb],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh ${Dsp-24-s8}[fb],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh ${Dsp-24-s16}[fb],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh ${Dsp-24-u16},r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh ${Dsp-24-u24},r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhh", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl $Dst32RnPrefixedQI,r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl $Dst32AnPrefixedQI,r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-direct-Prefixed-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl [$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl ${Dsp-24-u8}[sb],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl ${Dsp-24-u16}[sb],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl ${Dsp-24-s8}[fb],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl ${Dsp-24-s16}[fb],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl ${Dsp-24-u16},r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhl", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl ${Dsp-24-u24},r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhl", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh $Dst32RnPrefixedQI,r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh $Dst32AnPrefixedQI,r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-direct-Prefixed-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh [$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh ${Dsp-24-u8}[sb],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh ${Dsp-24-u16}[sb],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh ${Dsp-24-s8}[fb],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh ${Dsp-24-s16}[fb],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh ${Dsp-24-u16},r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movlh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh ${Dsp-24-u24},r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movlh", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll $Dst32RnPrefixedQI,r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll $Dst32AnPrefixedQI,r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-direct-Prefixed-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll [$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-indirect-Prefixed-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movll", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movll", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll ${Dsp-24-u8}[sb],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll ${Dsp-24-u16}[sb],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll ${Dsp-24-s8}[fb],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll ${Dsp-24-s16}[fb],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll ${Dsp-24-u16},r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movll", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll ${Dsp-24-u24},r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movll", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,$Dst32RnPrefixedQI */ { M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,$Dst32AnPrefixedQI */ { M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,[$Dst32AnPrefixed] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,${Dsp-24-u8}[sb] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,${Dsp-24-u16}[sb] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,${Dsp-24-s8}[fb] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,${Dsp-24-s16}[fb] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,${Dsp-24-u16} */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh r0l,${Dsp-24-u24} */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhh", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,$Dst32RnPrefixedQI */ { M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,$Dst32AnPrefixedQI */ { M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,[$Dst32AnPrefixed] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,${Dsp-24-u8}[sb] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,${Dsp-24-u16}[sb] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,${Dsp-24-s8}[fb] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,${Dsp-24-s16}[fb] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,${Dsp-24-u16} */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhl", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhl r0l,${Dsp-24-u24} */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhl", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,$Dst32RnPrefixedQI */ { M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,$Dst32AnPrefixedQI */ { M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,[$Dst32AnPrefixed] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,${Dsp-24-u8}[sb] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,${Dsp-24-u16}[sb] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,${Dsp-24-s8}[fb] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,${Dsp-24-s16}[fb] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,${Dsp-24-u16} */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movlh", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movlh r0l,${Dsp-24-u24} */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movlh", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,$Dst32RnPrefixedQI */ { M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,$Dst32AnPrefixedQI */ { M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-direct-Prefixed-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,[$Dst32AnPrefixed] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movll", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movll", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,${Dsp-24-u8}[sb] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,${Dsp-24-u16}[sb] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,${Dsp-24-s8}[fb] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,${Dsp-24-s16}[fb] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,${Dsp-24-u16} */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movll", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movll r0l,${Dsp-24-u24} */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movll", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* movhh $Dst16RnQI,r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, "movhh16.src-r0l-dst16-Rn-direct-QI", "movhh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh $Dst16AnQI,r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, "movhh16.src-r0l-dst16-An-direct-QI", "movhh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh [$Dst16An],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhh16.src-r0l-dst16-An-indirect-QI", "movhh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh ${Dsp-16-u8}[$Dst16An],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-An-relative-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh ${Dsp-16-u16}[$Dst16An],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-An-relative-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh ${Dsp-16-u8}[sb],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-SB-relative-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh ${Dsp-16-u16}[sb],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-SB-relative-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh ${Dsp-16-s8}[fb],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-FB-relative-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh ${Dsp-16-u16},r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhh16.src-r0l-dst16-16-16-absolute-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl $Dst16RnQI,r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, "movhl16.src-r0l-dst16-Rn-direct-QI", "movhl", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl $Dst16AnQI,r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, "movhl16.src-r0l-dst16-An-direct-QI", "movhl", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl [$Dst16An],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhl16.src-r0l-dst16-An-indirect-QI", "movhl", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl ${Dsp-16-u8}[$Dst16An],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-An-relative-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl ${Dsp-16-u16}[$Dst16An],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-An-relative-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl ${Dsp-16-u8}[sb],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-SB-relative-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl ${Dsp-16-u16}[sb],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-SB-relative-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl ${Dsp-16-s8}[fb],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-FB-relative-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl ${Dsp-16-u16},r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhl16.src-r0l-dst16-16-16-absolute-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh $Dst16RnQI,r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, "movlh16.src-r0l-dst16-Rn-direct-QI", "movlh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh $Dst16AnQI,r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, "movlh16.src-r0l-dst16-An-direct-QI", "movlh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh [$Dst16An],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movlh16.src-r0l-dst16-An-indirect-QI", "movlh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh ${Dsp-16-u8}[$Dst16An],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-An-relative-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh ${Dsp-16-u16}[$Dst16An],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-An-relative-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh ${Dsp-16-u8}[sb],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-SB-relative-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh ${Dsp-16-u16}[sb],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-SB-relative-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh ${Dsp-16-s8}[fb],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-FB-relative-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh ${Dsp-16-u16},r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movlh16.src-r0l-dst16-16-16-absolute-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll $Dst16RnQI,r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, "movll16.src-r0l-dst16-Rn-direct-QI", "movll", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll $Dst16AnQI,r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, "movll16.src-r0l-dst16-An-direct-QI", "movll", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll [$Dst16An],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movll16.src-r0l-dst16-An-indirect-QI", "movll", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll ${Dsp-16-u8}[$Dst16An],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-An-relative-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll ${Dsp-16-u16}[$Dst16An],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-An-relative-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll ${Dsp-16-u8}[sb],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-SB-relative-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll ${Dsp-16-u16}[sb],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-SB-relative-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll ${Dsp-16-s8}[fb],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-FB-relative-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll ${Dsp-16-u16},r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movll16.src-r0l-dst16-16-16-absolute-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh r0l,$Dst16RnQI */ { M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, "movhh16.r0l-dst-dst16-Rn-direct-QI", "movhh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh r0l,$Dst16AnQI */ { M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, "movhh16.r0l-dst-dst16-An-direct-QI", "movhh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh r0l,[$Dst16An] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, "movhh16.r0l-dst-dst16-An-indirect-QI", "movhh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-An-relative-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-An-relative-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-SB-relative-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-SB-relative-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-FB-relative-QI", "movhh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhh r0l,${Dsp-16-u16} */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhh16.r0l-dst-dst16-16-16-absolute-QI", "movhh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl r0l,$Dst16RnQI */ { M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, "movhl16.r0l-dst-dst16-Rn-direct-QI", "movhl", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl r0l,$Dst16AnQI */ { M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, "movhl16.r0l-dst-dst16-An-direct-QI", "movhl", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl r0l,[$Dst16An] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, "movhl16.r0l-dst-dst16-An-indirect-QI", "movhl", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-An-relative-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-An-relative-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-SB-relative-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-SB-relative-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-FB-relative-QI", "movhl", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movhl r0l,${Dsp-16-u16} */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhl16.r0l-dst-dst16-16-16-absolute-QI", "movhl", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh r0l,$Dst16RnQI */ { M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, "movlh16.r0l-dst-dst16-Rn-direct-QI", "movlh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh r0l,$Dst16AnQI */ { M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, "movlh16.r0l-dst-dst16-An-direct-QI", "movlh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh r0l,[$Dst16An] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, "movlh16.r0l-dst-dst16-An-indirect-QI", "movlh", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-An-relative-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-An-relative-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-SB-relative-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-SB-relative-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-FB-relative-QI", "movlh", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movlh r0l,${Dsp-16-u16} */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movlh16.r0l-dst-dst16-16-16-absolute-QI", "movlh", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll r0l,$Dst16RnQI */ { M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, "movll16.r0l-dst-dst16-Rn-direct-QI", "movll", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll r0l,$Dst16AnQI */ { M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, "movll16.r0l-dst-dst16-An-direct-QI", "movll", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll r0l,[$Dst16An] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, "movll16.r0l-dst-dst16-An-indirect-QI", "movll", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-An-relative-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-An-relative-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-SB-relative-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-SB-relative-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-FB-relative-QI", "movll", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* movll r0l,${Dsp-16-u16} */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movll16.r0l-dst-dst16-16-16-absolute-QI", "movll", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova [$Dst32AnUnprefixed],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u8}[sb],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16}[sb],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-s8}[fb],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-s16}[fb],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16},a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u24},a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova [$Dst32AnUnprefixed],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u8}[sb],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16}[sb],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-s8}[fb],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-s16}[fb],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16},a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u24},a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova [$Dst32AnUnprefixed],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u8}[sb],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16}[sb],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-s8}[fb],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-s16}[fb],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16},r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u24},r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova [$Dst32AnUnprefixed],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u8}[sb],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16}[sb],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-s8}[fb],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-s16}[fb],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u16},r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova ${Dsp-16-u24},r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mova [$Dst16An],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a1-dst16-An-indirect-Mova-HI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[$Dst16An],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-An-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[$Dst16An],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-An-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[sb],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-SB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[sb],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-SB-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-s8}[fb],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-FB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16},a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a1-dst16-16-16-absolute-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova [$Dst16An],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a0-dst16-An-indirect-Mova-HI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[$Dst16An],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-An-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[$Dst16An],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-An-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[sb],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-SB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[sb],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-SB-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-s8}[fb],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-FB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16},a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a0-dst16-16-16-absolute-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova [$Dst16An],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r3-dst16-An-indirect-Mova-HI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[$Dst16An],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-An-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[$Dst16An],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-An-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[sb],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-SB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[sb],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-SB-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-s8}[fb],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-FB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16},r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r3-dst16-16-16-absolute-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova [$Dst16An],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r2-dst16-An-indirect-Mova-HI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[$Dst16An],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-An-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[$Dst16An],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-An-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[sb],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-SB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[sb],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-SB-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-s8}[fb],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-FB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16},r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r2-dst16-16-16-absolute-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova [$Dst16An],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r1-dst16-An-indirect-Mova-HI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[$Dst16An],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-An-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[$Dst16An],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-An-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[sb],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-SB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[sb],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-SB-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-s8}[fb],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-FB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16},r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r1-dst16-16-16-absolute-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova [$Dst16An],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r0-dst16-An-indirect-Mova-HI", "mova", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[$Dst16An],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-An-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[$Dst16An],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-An-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u8}[sb],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-SB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16}[sb],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-SB-relative-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-s8}[fb],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-FB-relative-Mova-HI", "mova", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mova ${Dsp-16-u16},r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r0-dst16-16-16-absolute-Mova-HI", "mova", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-indirect-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-indirect-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ { M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */ { M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ { M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */ { M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-An-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-An-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ { M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-absolute-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */ { M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-Rn-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */ { M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */ { M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-indirect-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-An-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ { M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-absolute-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */ { M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-Rn-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */ { M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */ { M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-indirect-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.l${S} ${Dsp-8-u8}[sb],a1 */ { M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-SB-relative-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${S} ${Dsp-8-s8}[fb],a1 */ { M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-FB-relative-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${S} ${Dsp-8-u8}[sb],a0 */ { M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-SB-relative-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${S} ${Dsp-8-s8}[fb],a0 */ { M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-FB-relative-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${S} ${Dsp-8-u16},a1 */ { M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a1-dst32-2-S-16-absolute-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${S} ${Dsp-8-u16},a0 */ { M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a0-dst32-2-S-16-absolute-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} r0,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} r0,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} r0l,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} r0l,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} r0,${Dsp-8-u16} */ { M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-r0-dst32-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} r0l,${Dsp-8-u16} */ { M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-r0l-dst32-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} ${Dsp-8-u8}[sb],r1 */ { M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-SB-relative-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} ${Dsp-8-s8}[fb],r1 */ { M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-FB-relative-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} ${Dsp-8-u8}[sb],r1l */ { M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-SB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} ${Dsp-8-s8}[fb],r1l */ { M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-FB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} ${Dsp-8-u16},r1 */ { M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r1-dst32-2-S-16-absolute-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} ${Dsp-8-u16},r1l */ { M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r1l-dst32-2-S-16-absolute-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} r0,r1 */ { M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1-dst32-2-S-R0-direct-HI", "mov.w", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} r0l,r1l */ { M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, "mov32.b-dst32-2-S-basic-r1l-dst32-2-S-R0l-direct-QI", "mov.b", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} ${Dsp-8-u8}[sb],r0 */ { M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-SB-relative-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} ${Dsp-8-s8}[fb],r0 */ { M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-FB-relative-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} ${Dsp-8-u8}[sb],r0l */ { M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-SB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} ${Dsp-8-s8}[fb],r0l */ { M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-FB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} ${Dsp-8-u16},r0 */ { M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r0-dst32-2-S-16-absolute-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} ${Dsp-8-u16},r0l */ { M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r0l-dst32-2-S-16-absolute-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */ { M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "mov16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "mov.b", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ { M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-SB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ { M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-FB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ { M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-src2-src16-2-S-16-absolute-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */ { M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-SB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */ { M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-FB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */ { M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-Rn-An-src16-2-S-16-absolute-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */ { M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-SB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */ { M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-FB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */ { M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-An-src16-2-S-16-absolute-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Z} #0,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Z} #0,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Z} #0,${Dsp-8-u16} */ { M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-Z-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Z} #0,r0 */ { M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-Z-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Z} #0,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Z} #0,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Z} #0,${Dsp-8-u16} */ { M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-Z-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Z} #0,r0l */ { M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-Z-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Z} #0,r0l */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Z} #0,r0h */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Z} #0,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-SB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Z} #0,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-FB-relative-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Z} #0,${Dsp-8-u16} */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${Q} #${Imm-8-s4},$Dst16RnQI */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-Rn-direct-QI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Q} #${Imm-8-s4},$Dst16AnQI */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-direct-QI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Q} #${Imm-8-s4},[$Dst16An] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-indirect-QI", "mov.w", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.w-imm4-Q-16-dst16-16-16-absolute-QI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-Rn-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Q} #${Imm-8-s4},[$Dst16An] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-indirect-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} #${Imm-8-QI},r0h */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "mov.l", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */ { M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */ { M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* mov.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-Rn-direct-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-An-direct-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-imm-G-basic-dst16-An-indirect-HI", "mov.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mov.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mov.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-Rn-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-An-direct-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-imm-G-basic-dst16-An-indirect-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mov.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "min.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "min.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "min.w", 64, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "min.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "min.b", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "min.b", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },


context:
space:
mode: