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| author | Peter Griffin <peter.griffin@linaro.org> | 2016-04-20 17:14:01 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-04-25 15:10:34 -0400 |
| commit | 7e4902d47933eeeadb2eb5505683ffafa96691b7 (patch) | |
| tree | b6e03c5e54502c22ad4ec032f0ca1d30e1a864d0 | |
| parent | 9261f8b1809d6bf2075cfc97bbd0cac23e086716 (diff) | |
| download | u-boot-7e4902d47933eeeadb2eb5505683ffafa96691b7.zip u-boot-7e4902d47933eeeadb2eb5505683ffafa96691b7.tar.gz u-boot-7e4902d47933eeeadb2eb5505683ffafa96691b7.tar.bz2 | |
ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.
This is a binding which only exists in U-Boot, but is
required to get working serial in U-Boot.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | arch/arm/dts/hi6220.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/dts/hi6220.dtsi b/arch/arm/dts/hi6220.dtsi index ad1f1eb..a610ccb 100644 --- a/arch/arm/dts/hi6220.dtsi +++ b/arch/arm/dts/hi6220.dtsi @@ -166,6 +166,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clock = <19200000>; clocks = <&ao_ctrl HI6220_UART0_PCLK>, <&ao_ctrl HI6220_UART0_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -175,6 +176,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7111000 0x0 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clock = <19200000>; clocks = <&sys_ctrl HI6220_UART1_PCLK>, <&sys_ctrl HI6220_UART1_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -185,6 +187,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7112000 0x0 0x1000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clock = <19200000>; clocks = <&sys_ctrl HI6220_UART2_PCLK>, <&sys_ctrl HI6220_UART2_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -195,6 +198,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7113000 0x0 0x1000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clock = <19200000>; clocks = <&sys_ctrl HI6220_UART3_PCLK>, <&sys_ctrl HI6220_UART3_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -204,6 +208,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7114000 0x0 0x1000>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clock = <19200000>; clocks = <&sys_ctrl HI6220_UART4_PCLK>, <&sys_ctrl HI6220_UART4_PCLK>; clock-names = "uartclk", "apb_pclk"; |