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| author | Patrice Chotard <patrice.chotard@st.com> | 2018-04-26 16:45:19 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-08 09:07:38 -0400 |
| commit | 7c339bbae6629d4d7a717ee553fc53e7fbc6dfa5 (patch) | |
| tree | 16d52bcbf306a310b20e290f95935d9a4900921b | |
| parent | e8b85e810ad28aebc4971df3c0d3975708377ab4 (diff) | |
| download | u-boot-7c339bbae6629d4d7a717ee553fc53e7fbc6dfa5.zip u-boot-7c339bbae6629d4d7a717ee553fc53e7fbc6dfa5.tar.gz u-boot-7c339bbae6629d4d7a717ee553fc53e7fbc6dfa5.tar.bz2 | |
ARM: dts: stm32mp157: Add SoC pwr regulator entry
Add SoC power regulator entry for reg11, reg18 and usb33
regulator.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| -rw-r--r-- | arch/arm/dts/stm32mp157.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi index b84899a..a798144 100644 --- a/arch/arm/dts/stm32mp157.dtsi +++ b/arch/arm/dts/stm32mp157.dtsi @@ -123,6 +123,39 @@ }; }; + pwr: pwr@50001000 { + compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd"; + reg = <0x50001000 0x400>; + system-power-controller; + interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>; + st,sysrcc = <&rcc>; + clocks = <&rcc_clk PLL2_R>; + clock-names = "phyclk"; + + pwr-regulators@c { + compatible = "st,stm32mp1,pwr-reg"; + st,tzcr = <&rcc 0x0 0x1>; + + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + pinctrl: pin-controller { compatible = "st,stm32mp157-pinctrl"; #address-cells = <1>; |