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| author | Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> | 2022-06-27 14:22:45 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-07-26 08:23:54 +0200 |
| commit | 71f07731488e9ade674ee396208317ab2db3cce1 (patch) | |
| tree | abf1f1faf624e9dbd4bf61466330d0556276626d | |
| parent | 156cb2af92c244fae15c8fbdab293d88d451edcf (diff) | |
| download | u-boot-71f07731488e9ade674ee396208317ab2db3cce1.zip u-boot-71f07731488e9ade674ee396208317ab2db3cce1.tar.gz u-boot-71f07731488e9ade674ee396208317ab2db3cce1.tar.bz2 | |
mmc: zynq_sdhci: Fix timing macros for MMC High speed
Timing macro's are wrong for MMC_HS_52 and MMC_DDR_52. Fix it with
correct values of MMC_TIMING_MMC_HS and MMC_TIMING_MMC_DDR52 respectively.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1656319965-12124-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
| -rw-r--r-- | drivers/mmc/zynq_sdhci.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index e978b67..8f4071c 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -101,8 +101,8 @@ static const u8 mode2timing[] = { [MMC_LEGACY] = MMC_TIMING_LEGACY, [MMC_HS] = MMC_TIMING_MMC_HS, [SD_HS] = MMC_TIMING_SD_HS, - [MMC_HS_52] = MMC_TIMING_UHS_SDR50, - [MMC_DDR_52] = MMC_TIMING_UHS_DDR50, + [MMC_HS_52] = MMC_TIMING_MMC_HS, + [MMC_DDR_52] = MMC_TIMING_MMC_DDR52, [UHS_SDR12] = MMC_TIMING_UHS_SDR12, [UHS_SDR25] = MMC_TIMING_UHS_SDR25, [UHS_SDR50] = MMC_TIMING_UHS_SDR50, |