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| author | horia.geanta@freescale.com <horia.geanta@freescale.com> | 2015-10-15 14:21:31 +0300 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-10-29 10:33:58 -0700 |
| commit | 5757e06c69a02fe95208a503504756b7d422e64f (patch) | |
| tree | f296fff714a636cac0b60a76d5137715ea8a928c | |
| parent | 2bc3b2e85c3be81688693f28f1c1f6b1a333d4a8 (diff) | |
| download | u-boot-5757e06c69a02fe95208a503504756b7d422e64f.zip u-boot-5757e06c69a02fe95208a503504756b7d422e64f.tar.gz u-boot-5757e06c69a02fe95208a503504756b7d422e64f.tar.bz2 | |
arm: ls102xa: enable snooping for CAAM transactions
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/cpu.c | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index e2eb5f3..df2e1b7 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -301,6 +301,7 @@ int arch_cpu_init(void) void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *rcpm2_base = (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; u32 state; /* @@ -328,6 +329,8 @@ int arch_cpu_init(void) */ fsl_epu_clean(epu_base); + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 60aa0d3..fbd06ba 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -144,6 +144,7 @@ struct ccsr_gur { }; #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 |