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authorRan Wang <ran.wang_1@nxp.com>2019-05-14 17:34:56 +0800
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2019-06-19 12:54:56 +0530
commit3458a4198cca572f6c82d38810e4f3c80dc8849d (patch)
tree277c5da267fdab56303aa3e8ceaf10fb02899c35
parent1be0c66c792d0d51debf45de3bc4eb5cafc6271d (diff)
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armv8: ls1028a: enable workaround for USB erratum A-008997
Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL registers has been moved to DSCR as compared to other Layerscape SoCs where it was in SCFG. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig1
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c4
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h2
3 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a843c1e..3f6c983 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -48,6 +48,7 @@ config ARCH_LS1028A
select SYS_I2C_MXC_I2C6
select SYS_I2C_MXC_I2C7
select SYS_I2C_MXC_I2C8
+ select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 06f3edb..f2392f0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -126,6 +126,10 @@ static void erratum_a008997(void)
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
#endif
+#elif defined(CONFIG_ARCH_LS1028A)
+ clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
+ 0x7F << 11,
+ DCSR_USB_PCSTXSWINGFULL << 11);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 24c1b0e..2b12e9f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -226,6 +226,8 @@
#define USB_PHY_RX_EQ_VAL_2 0x0080
#define USB_PHY_RX_EQ_VAL_3 0x0380
#define USB_PHY_RX_EQ_VAL_4 0x0b80
+#define DCSR_USB_IOCR1 0x108004
+#define DCSR_USB_PCSTXSWINGFULL 0x71
#define TP_ITYP_AV 0x00000001 /* Initiator available */
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */