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| author | Patrice Chotard <patrice.chotard@foss.st.com> | 2024-12-13 14:26:55 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-12-17 09:14:01 -0600 |
| commit | 25fb58e88aba0c4af0af554d7b141be3f2e5e0b5 (patch) | |
| tree | df9a6788a1df481eaf4bc9134dab457a40abc8d6 | |
| parent | 1cde96bee57ead9714d0ee2f484e0be4540f3fad (diff) | |
| download | u-boot-25fb58e88aba0c4af0af554d7b141be3f2e5e0b5.zip u-boot-25fb58e88aba0c4af0af554d7b141be3f2e5e0b5.tar.gz u-boot-25fb58e88aba0c4af0af554d7b141be3f2e5e0b5.tar.bz2 | |
ARM: stm32mp: Fix dram_bank_mmu_setup() for LMB located above ram_top
Previously, all LMB marked with LMB_NOMAP (above and below ram_top)
are considered as invalid entry in TLB.
Since commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top
even from same bank") all LMB located above ram_top are now marked
LMB_NOOVERWRITE and no more LMB_MAP.
This area above ram_top is reserved for OPTEE and must not be cacheable,
otherwise this leads to a Panic on some boards (Issue on STM32MP135F-DK).
Restore previous behavior by marking invalid entry all TLB above ram_top.
Fixes: 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp1/cpu.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 62cc989..cb1b84c 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -53,6 +53,7 @@ void dram_bank_mmu_setup(int bank) struct bd_info *bd = gd->bd; int i; phys_addr_t start; + phys_addr_t addr; phys_size_t size; bool use_lmb = false; enum dcache_option option; @@ -77,8 +78,12 @@ void dram_bank_mmu_setup(int bank) for (i = start >> MMU_SECTION_SHIFT; i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); i++) { + addr = i << MMU_SECTION_SHIFT; option = DCACHE_DEFAULT_OPTION; - if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP)) + if (use_lmb && + (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) || + addr >= gd->ram_top) + ) option = 0; /* INVALID ENTRY in TLB */ set_section_dcache(i, option); } |