diff options
| author | Tom Rini <trini@konsulko.com> | 2016-08-22 08:22:17 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-08-26 17:04:46 -0400 |
| commit | 067716bac59716b07f1ee70d9bf6e5528289bb45 (patch) | |
| tree | 97e27955376354dbe1bbae977b02a6e323d2b54a | |
| parent | da968c7bfa4cc1203a4f9f61a97f55c85dfbb3b6 (diff) | |
| download | u-boot-067716bac59716b07f1ee70d9bf6e5528289bb45.zip u-boot-067716bac59716b07f1ee70d9bf6e5528289bb45.tar.gz u-boot-067716bac59716b07f1ee70d9bf6e5528289bb45.tar.bz2 | |
ARM: Move SYS_CACHELINE_SIZE over to Kconfig
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here. Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: "Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Chin Liang See <clsee@altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
81 files changed, 32 insertions, 182 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aef901c..e6d4a20 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -7,6 +7,7 @@ config SYS_ARCH config ARM64 bool select PHYS_64BIT + select SYS_CACHE_SHIFT_6 config DMA_ADDR_T_64BIT bool @@ -20,37 +21,47 @@ config HAS_THUMB2 config CPU_ARM720T bool + select SYS_CACHE_SHIFT_5 config CPU_ARM920T bool + select SYS_CACHE_SHIFT_5 config CPU_ARM926EJS bool + select SYS_CACHE_SHIFT_5 config CPU_ARM946ES bool + select SYS_CACHE_SHIFT_5 config CPU_ARM1136 bool + select SYS_CACHE_SHIFT_5 config CPU_ARM1176 bool select HAS_VBAR + select SYS_CACHE_SHIFT_5 config CPU_V7 bool select HAS_VBAR select HAS_THUMB2 + select SYS_CACHE_SHIFT_6 config CPU_V7M bool select HAS_THUMB2 + select SYS_CACHE_SHIFT_5 config CPU_PXA bool + select SYS_CACHE_SHIFT_5 config CPU_SA1100 bool + select SYS_CACHE_SHIFT_5 config SYS_CPU default "arm720t" if CPU_ARM720T @@ -79,6 +90,21 @@ config SYS_ARM_ARCH default 4 if CPU_SA1100 default 8 if ARM64 +config SYS_CACHE_SHIFT_5 + bool + +config SYS_CACHE_SHIFT_6 + bool + +config SYS_CACHE_SHIFT_7 + bool + +config SYS_CACHELINE_SIZE + int + default 128 if SYS_CACHE_SHIFT_7 + default 64 if SYS_CACHE_SHIFT_6 + default 32 if SYS_CACHE_SHIFT_5 + config SEMIHOSTING bool "support boot from semihosting" help @@ -867,6 +893,7 @@ config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 select OF_CONTROL + select SYS_CACHE_SHIFT_7 endchoice diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 7244c2e..ef32c3f 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -53,11 +53,6 @@ static void cache_flush(void) } #ifndef CONFIG_SYS_DCACHE_OFF - -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - void invalidate_dcache_all(void) { asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 2119382..02cb24c 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -8,11 +8,6 @@ #include <common.h> #ifndef CONFIG_SYS_DCACHE_OFF - -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - void invalidate_dcache_all(void) { asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c index 7aba112..d26354e 100644 --- a/arch/arm/cpu/pxa/cache.c +++ b/arch/arm/cpu/pxa/cache.c @@ -8,11 +8,6 @@ #include <common.h> #ifndef CONFIG_SYS_DCACHE_OFF - -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - void invalidate_dcache_all(void) { /* Flush/Invalidate I cache */ diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index e062da1..6ebc759 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -16,8 +16,6 @@ #define _ARMD1_CONFIG_H #include <asm/arch/armada100.h> -/* default Dcache Line length for armada100 */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ #define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b0ad4b4..5279981 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_PAGE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 64 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) @@ -150,7 +149,6 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index d408fe4..56d8f32 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -7,8 +7,6 @@ #ifndef _ASM_ARMV7_LS102XA_CONFIG_ #define _ASM_ARMV7_LS102XA_CONFIG_ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define OCRAM_BASE_ADDR 0x10000000 #define OCRAM_SIZE 0x00010000 #define OCRAM_BASE_S_ADDR 0x10010000 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index e73cc07..3e79fa3 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,8 +9,6 @@ #define ARCH_MXC -#define CONFIG_SYS_CACHELINE_SIZE 64 - #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index ac37e4f..53bf054 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -9,12 +9,6 @@ #define ARCH_MXC -#ifdef CONFIG_MX6UL -#define CONFIG_SYS_CACHELINE_SIZE 64 -#else -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 74917f0..d33be31 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -9,8 +9,6 @@ #define ARCH_MXC -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define ROM_SW_INFO_ADDR 0x000001E8 #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x00017FFF diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 16e65c3..5400cbe 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -43,14 +43,11 @@ void dram_bank_mmu_setup(int bank); #endif /* - * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We - * use that value for aligning DMA buffers unless the board config has specified - * an alternate cache line size. + * The value of the largest data cache relevant to DMA operations shall be set + * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger + * value than found in the L1 cache but this is OK to use in terms of + * alignment. */ -#ifdef CONFIG_SYS_CACHELINE_SIZE #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 64 -#endif #endif /* _ASM_CACHE_H */ diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index d330b09..4f72f89 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,10 +10,6 @@ #include <common.h> #include <malloc.h> -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - /* * Flush range from all levels of d-cache/unified-cache. * Affects the range [start, start + size - 1]. diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 60b60aa..446457f 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -24,8 +24,6 @@ #endif /* CONFIG_KW88F6281 */ #include <asm/arch/soc.h> -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* default Dcache Line length for kirkwood */ #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 4df70d7..1b35e08 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -26,8 +26,6 @@ #define MV88F78X60 /* for the DDR training bin_hdr code */ #endif -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_L2_PL310 #ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index a8a0b90..8961458 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -75,6 +75,7 @@ config ARCH_UNIPHIER_LD6B config CACHE_UNIPHIER bool "Enable the UniPhier L2 cache controller" depends on ARCH_UNIPHIER_32BIT + select SYS_CACHE_SHIFT_7 default y help This option allows to use the UniPhier System Cache as L2 cache. diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index a65d1a8..30c4278 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 4d88aac..ef4a8ba 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -18,8 +18,6 @@ #define CONFIG_OMAP #define CONFIG_OMAP_COMMON -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 0467953..518b904 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -11,7 +11,6 @@ #define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ @@ -49,7 +48,6 @@ /* Enabling L2 Cache */ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 9257c5f..051186d 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -12,8 +12,6 @@ #include <asm/hardware.h> -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_TEXT_BASE 0x26f00000 /* ARM asynchronous clock */ diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h index 770dd87..b968801 100644 --- a/include/configs/bcm23550_w1d.h +++ b/include/configs/bcm23550_w1d.h @@ -127,7 +127,6 @@ /* Commands */ #define CONFIG_FAT_WRITE -#define CONFIG_SYS_CACHELINE_SIZE 64 #undef CONFIG_USB_GADGET_VBUS_DRAW #define CONFIG_USB_GADGET_VBUS_DRAW 0 #define CONFIG_USBID_ADDR 0x34052c46 diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index df0b2ba..f38f081 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -126,7 +126,6 @@ /* Commands */ #define CONFIG_FAT_WRITE -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_USBID_ADDR 0x34052c46 #endif /* __BCM28155_AP_H */ diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index 50cd743..b5e5029 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -11,8 +11,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * Memory configuration * (these must be defined elsewhere) diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index a94b1e2..04da877 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -15,7 +15,6 @@ #define CONFIG_AM33XX #define CONFIG_OMAP #define CONFIG_OMAP_COMMON -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index ea9983b..a89ccb7 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options */ @@ -30,7 +28,6 @@ * Although the default iss 64, we still define it * to be on the safe side once the default is changed. */ -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 5d94f13..b896d4d 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -79,7 +79,6 @@ /* Enabling L2 Cache */ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 5892595..fb68e59 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -12,8 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include <asm/arch/imx-regs.h> #define CONFIG_VF610 @@ -207,8 +205,6 @@ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* USB Host Support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_VF diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 28ea15b..746475d 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -118,7 +118,6 @@ #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#define CONFIG_SYS_CACHELINE_SIZE SZ_8K #define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 /* bootstrap + u-boot + env in nandflash */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 1dbe219..cc7ab83 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -27,8 +27,6 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) #define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* UART */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index fbe0fa9..fdbaf02 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -15,7 +15,6 @@ #define CONFIG_BOARD_COMMON -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_REVISION_TAG /* SD/MMC configuration */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index f2ed798..1538787 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -13,7 +13,6 @@ #include "exynos-common.h" -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_EXYNOS_SPL #ifdef FTRACE diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 824aca45..e84803d 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -19,7 +19,6 @@ #define CONFIG_MX35 #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/hikey.h b/include/configs/hikey.h index ffcc4d2..9cbccd9 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -21,9 +21,6 @@ #define CONFIG_SUPPORT_RAW_INITRD -/* MMU Definitions */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_IDENT_STRING "hikey" #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/kc1.h b/include/configs/kc1.h index b08cf21..8b95799 100644 --- a/include/configs/kc1.h +++ b/include/configs/kc1.h @@ -24,7 +24,6 @@ #define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0x48242000 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* * Platform diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 94f3516..a4b296a 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -10,8 +10,6 @@ #undef DEBUG -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SH73A0 #define CONFIG_KZM_A9_GT #define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 0c6e111..8387f19 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -25,8 +25,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MCX #define CONFIG_BOARD_LATE_INIT -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index eaf6a9c..3bba2e6 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -10,7 +10,6 @@ #define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_IS_NOWHERE 1 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index cd154a4..cdae544 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -19,8 +19,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 4dbe2b6..fc5de03 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -275,8 +275,6 @@ #define CONFIG_OMAP3_SPI -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Defines for SPL */ #define CONFIG_SPL_OMAP3_ID_NAND diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h index 82e0d50..4310bad 100644 --- a/include/configs/omap3_cairo.h +++ b/include/configs/omap3_cairo.h @@ -192,8 +192,6 @@ #define CONFIG_OMAP3_SPI -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Defines for SPL */ #define CONFIG_SPL_OMAP3_ID_NAND diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 52a24d3..e87b4c0 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -340,8 +340,6 @@ /* Uncomment to define the board revision statically */ /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40200800 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 49a8b3f..05a4361 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -82,7 +82,6 @@ #define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 -#define CONFIG_SYS_CACHELINE_SIZE 64 /* TWL4030 */ #define CONFIG_TWL4030_PWM diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index fbd0c2a..618a546 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -215,7 +215,6 @@ /* Initial RAM setup */ #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_CACHELINE_SIZE 64 /* NAND boot config */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 380ec12..9e7bd88 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -119,6 +119,4 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#define CONFIG_SYS_CACHELINE_SIZE 64 - #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 99d9fc3..6397051 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -176,8 +176,6 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#define CONFIG_SYS_CACHELINE_SIZE 64 - #ifdef CONFIG_CMD_NET /* Ethernet (LAN9211 from SMSC9118 family) */ #define CONFIG_SMC911X diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 74e22db..57a7630 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include <asm/arch/imx-regs.h> #define CONFIG_VF610 diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 80313fc..8f91e8e 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -9,8 +9,6 @@ #ifndef __RCAR_GEN2_COMMON_H #define __RCAR_GEN2_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch/rmobile.h> #define CONFIG_CMD_DFL diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 21d4683..101a3ed 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -6,8 +6,6 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch/hardware.h> #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index d3d4c68..601186c 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch/hardware.h> #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 6875308..e9626a5 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_RK3399_COMMON_H #define __CONFIG_RK3399_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index dbbb81e..752cc31 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -14,12 +14,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif -#ifdef CONFIG_BCM2835 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#else -#define CONFIG_SYS_CACHELINE_SIZE 64 -#endif - /* Architecture, CPU, etc.*/ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 87e51d0..61c5663 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -17,8 +17,6 @@ #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ #define CONFIG_MACH_GONI 1 /* working with Goni */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <linux/sizes.h> #include <asm/arch/cpu.h> /* get chip and board defs */ @@ -236,8 +234,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX8998 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index eab665c..3d25e3d 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -36,8 +36,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* commands to include */ #define CONFIG_ENV_VARS_UBOOT_CONFIG diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 076a5ce..8ad8f24 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -170,8 +170,6 @@ #define CONFIG_DFU_NAND #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M #define DFU_MANIFEST_POLL_TIMEOUT 25000 - -#define CONFIG_SYS_CACHELINE_SIZE 0x2000 #endif /* General Boot Parameter */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 84a188a..9d52689 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -12,8 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options * (easy to change) diff --git a/include/configs/sniper.h b/include/configs/sniper.h index fb348a5..e2f5e60 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -16,8 +16,6 @@ * CPU */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_ARM_ARCH_CP15_ERRATA #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f654f94..ce5781b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -75,7 +75,6 @@ /* * Cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b9aa62b..f64edd4 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -55,7 +55,6 @@ /* CPU */ #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_TIMER_CLK_FREQ 24000000 /* diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 73ff416..5213065 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -23,8 +23,6 @@ #define CONFIG_SYS_TEXT_BASE 0x80008000 -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 6616d73..52bd837 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 2d091db..513e655 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -133,8 +133,6 @@ #define CONFIG_DFU_NAND #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) #define DFU_MANIFEST_POLL_TIMEOUT 25000 - -#define CONFIG_SYS_CACHELINE_SIZE SZ_8K #endif /* SPI EEPROM */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 21454d4..107a0f8 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -8,9 +8,6 @@ #define _TEGRA114_COMMON_H_ #include "tegra-common.h" -/* Cortex-A15 uses a cache line size of 64 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * NS16550 Configuration */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 39e74f0..8cf9bac 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -10,9 +10,6 @@ #include "tegra-common.h" -/* Cortex-A15 uses a cache line size of 64 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * NS16550 Configuration */ diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index aa7b9d0..98e4fc2 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -9,9 +9,6 @@ #include "tegra-common.h" -/* Cortex-A57 uses a cache line size of 64 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * NS16550 Configuration */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 00e85c4..793310f 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -9,9 +9,6 @@ #define _TEGRA20_COMMON_H_ #include "tegra-common.h" -/* Cortex-A9 uses a cache line size of 32 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* * Errata configuration */ diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 8f35a7b..874fe34d 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -10,9 +10,6 @@ #include "tegra-common.h" -/* Cortex-A57 uses a cache line size of 64 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * NS16550 Configuration */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 9afd864..baf3d00 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -9,9 +9,6 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" -/* Cortex-A9 uses a cache line size of 32 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* * Errata configuration */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 3c05883..732854e 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -16,8 +16,6 @@ #ifndef __CONFIG_TI814X_EVM_H #define __CONFIG_TI814X_EVM_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_TI81XX #define CONFIG_TI814X #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 05fd00f..17f12a8 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_TI816X_EVM_H #define __CONFIG_TI816X_EVM_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_TI81XX #define CONFIG_TI816X #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index bcd56fc..a9b10d0 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -14,7 +14,6 @@ #define CONFIG_AM33XX #define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 4aa262e..c830c0c 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -200,7 +200,6 @@ #define CONFIG_USB_STORAGE #define CONFIG_EFI_PARTITION #define CONFIG_FS_FAT -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_USB_SS_BASE KS2_USB_SS_BASE #define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE #define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 32877d1..c54b7b5 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -18,8 +18,6 @@ * High Level Configuration Options */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch/cpu.h> #include <asm/arch/omap.h> diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 5fad3c1..e6e88c5 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0x48242000 #endif -#define CONFIG_SYS_CACHELINE_SIZE 32 /* Get CPU defs */ #include <asm/arch/cpu.h> diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 3589cdc..e42c88e 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -23,8 +23,6 @@ /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_798870 -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 127a968..ae0e89c 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -16,8 +16,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* High Level Configuration Options */ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_OMAP /* in a TI OMAP core */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 0f5b20f..f41a0b1 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -30,12 +30,6 @@ /* #define CONFIG_SYS_ICACHE_OFF */ /* #define CONFIG_SYS_DCACHE_OFF */ -#ifdef CONFIG_CACHE_UNIPHIER -#define CONFIG_SYS_CACHELINE_SIZE 128 -#else -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_F diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 9aca393..71c4a1f 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -19,9 +19,6 @@ #define CONFIG_SUPPORT_RAW_INITRD -/* MMU Definitions */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_IDENT_STRING " vexpress_aemv8a" /* Link Definitions */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 51898e6..a8eba31 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -118,8 +118,6 @@ #define CONFIG_SYS_MEMTEST_START V2M_BASE #define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SYS_L2CACHE_OFF 1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index c4a1fd0..33f966a 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include <asm/arch/imx-regs.h> #define CONFIG_VF610 diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 153466a..de6b183 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ca60e5d..02f0e4c 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -34,9 +34,6 @@ /* Have release address at the end of 256MB for now */ #define CPU_RELEASE_ADDR 0xFFFFFF0 -/* Cache Definitions */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #if !defined(CONFIG_IDENT_STRING) # define CONFIG_IDENT_STRING " Xilinx ZynqMP" #endif diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index e59e412..5f7fefd 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -16,8 +16,6 @@ #endif /* Cache options */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF # define CONFIG_SYS_L2_PL310 |