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| author | Gatien Chevallier <gatien.chevallier@foss.st.com> | 2023-09-19 17:27:56 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2023-10-04 13:26:03 +0200 |
| commit | 01af3636230656cdcba7a1c625c17a5c32a3fb69 (patch) | |
| tree | 575acd80f61cff1ca1bd7084aac32acfc748ebf0 | |
| parent | 2d2574b4055f86f2fac57c6322e6487f15524baf (diff) | |
| download | u-boot-01af3636230656cdcba7a1c625c17a5c32a3fb69.zip u-boot-01af3636230656cdcba7a1c625c17a5c32a3fb69.tar.gz u-boot-01af3636230656cdcba7a1c625c17a5c32a3fb69.tar.bz2 | |
rng: stm32: add RNG clock frequency restraint
In order to ensure a good RNG quality and compatibility with
certified RNG configuration, add RNG clock frequency restraint.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| -rw-r--r-- | drivers/rng/stm32_rng.c | 43 |
1 files changed, 38 insertions, 5 deletions
diff --git a/drivers/rng/stm32_rng.c b/drivers/rng/stm32_rng.c index ada5d92..f943acd 100644 --- a/drivers/rng/stm32_rng.c +++ b/drivers/rng/stm32_rng.c @@ -18,10 +18,11 @@ #include <linux/iopoll.h> #include <linux/kernel.h> -#define RNG_CR 0x00 -#define RNG_CR_RNGEN BIT(2) -#define RNG_CR_CED BIT(5) -#define RNG_CR_CONDRST BIT(30) +#define RNG_CR 0x00 +#define RNG_CR_RNGEN BIT(2) +#define RNG_CR_CED BIT(5) +#define RNG_CR_CLKDIV_SHIFT 16 +#define RNG_CR_CONDRST BIT(30) #define RNG_SR 0x04 #define RNG_SR_SEIS BIT(6) @@ -31,7 +32,15 @@ #define RNG_DR 0x08 +/* + * struct stm32_rng_data - RNG compat data + * + * @max_clock_rate: Max RNG clock frequency, in Hertz + * @has_cond_reset: True if conditionnal reset is supported + * + */ struct stm32_rng_data { + uint max_clock_rate; bool has_cond_reset; }; @@ -87,6 +96,26 @@ static int stm32_rng_read(struct udevice *dev, void *data, size_t len) return 0; } +static uint stm32_rng_clock_freq_restrain(struct stm32_rng_plat *pdata) +{ + ulong clock_rate = 0; + uint clock_div = 0; + + clock_rate = clk_get_rate(&pdata->clk); + + /* + * Get the exponent to apply on the CLKDIV field in RNG_CR register. + * No need to handle the case when clock-div > 0xF as it is physically + * impossible. + */ + while ((clock_rate >> clock_div) > pdata->data->max_clock_rate) + clock_div++; + + log_debug("RNG clk rate : %lu\n", clk_get_rate(&pdata->clk) >> clock_div); + + return clock_div; +} + static int stm32_rng_init(struct stm32_rng_plat *pdata) { int err; @@ -99,7 +128,9 @@ static int stm32_rng_init(struct stm32_rng_plat *pdata) cr = readl(pdata->base + RNG_CR); if (pdata->data->has_cond_reset) { - cr |= RNG_CR_CONDRST; + uint clock_div = stm32_rng_clock_freq_restrain(pdata); + + cr |= RNG_CR_CONDRST | (clock_div << RNG_CR_CLKDIV_SHIFT); if (pdata->ced) cr &= ~RNG_CR_CED; else @@ -186,10 +217,12 @@ static const struct dm_rng_ops stm32_rng_ops = { static const struct stm32_rng_data stm32mp13_rng_data = { .has_cond_reset = true, + .max_clock_rate = 48000000, }; static const struct stm32_rng_data stm32_rng_data = { .has_cond_reset = false, + .max_clock_rate = 3000000, }; static const struct udevice_id stm32_rng_match[] = { |