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| author | Marek Vasut <marex@denx.de> | 2018-08-13 18:42:32 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-08-13 22:35:16 +0200 |
| commit | 6f96ed7e2080c305fa45e8b12d8013d8bab9ec5d (patch) | |
| tree | ea2a0f1b8cee8c2d3e042290dce4c80a3ed15eb3 | |
| parent | af74658e04a78d02229804ed429551da5e6a3488 (diff) | |
| download | u-boot-6f96ed7e2080c305fa45e8b12d8013d8bab9ec5d.zip u-boot-6f96ed7e2080c305fa45e8b12d8013d8bab9ec5d.tar.gz u-boot-6f96ed7e2080c305fa45e8b12d8013d8bab9ec5d.tar.bz2 | |
ARM: dts: socfpga: Flag reset manager on A10 as pre-reloc
The Altera reset manager block must be available very early on, since
it controls ie. UART resets. Flag it as pre-reloc.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| -rw-r--r-- | arch/arm/dts/socfpga_arria10.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 2f935a2..51b31dc 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -55,6 +55,7 @@ device_type = "soc"; interrupt-parent = <&intc>; ranges; + u-boot,dm-pre-reloc; amba { compatible = "simple-bus"; @@ -735,6 +736,7 @@ compatible = "altr,rst-mgr"; reg = <0xffd05000 0x100>; altr,modrst-offset = <0x20>; + u-boot,dm-pre-reloc; }; scu: snoop-control-unit@ffffc000 { |