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| author | Simon Glass <sjg@chromium.org> | 2023-09-19 21:00:07 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng@tinylab.org> | 2023-09-22 06:03:46 +0800 |
| commit | b1350636e69d4aac1e00aee5a327b5724f074420 (patch) | |
| tree | 7798b7d37cc280700f40ffd4464ac176f67f62ab | |
| parent | 0c45c76ced7222ad8e5fb41b8be4d5237fd791a0 (diff) | |
| download | u-boot-b1350636e69d4aac1e00aee5a327b5724f074420.zip u-boot-b1350636e69d4aac1e00aee5a327b5724f074420.tar.gz u-boot-b1350636e69d4aac1e00aee5a327b5724f074420.tar.bz2 | |
x86: coreboot: Look for DBG2 UART in SPL too
If coreboot does not set up sysinfo for the UART, SPL currently hangs.
Use the DBG2 technique there as well. This allows coreboot64 to boot from
coreboot even if the console info is missing from sysinfo
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | configs/coreboot64_defconfig | 1 | ||||
| -rw-r--r-- | drivers/serial/Kconfig | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 5623197..e816596 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -54,4 +54,5 @@ CONFIG_SYS_64BIT_LBA=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_SPL_ACPI=y # CONFIG_GZIP is not set diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 7ca42df..27b4b9d 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -672,7 +672,7 @@ config COREBOOT_SERIAL config COREBOOT_SERIAL_FROM_DBG2 bool "Obtain UART from ACPI tables" depends on COREBOOT_SERIAL - default y if !SPL + default y help Select this to try to find a DBG2 record in the ACPI tables, in the event that coreboot does not provide information about the UART in the |