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authorKevin O'Connor <kevin@koconnor.net>2015-08-10 16:14:48 -0400
committerKevin O'Connor <kevin@koconnor.net>2015-08-24 11:02:13 -0400
commitbd5f6c7432f4c8297871ed4e243dc69a9cece318 (patch)
tree68dd87717f2d7ff05b1540ea8911810192f823e6 /src/hw/timer.c
parentbc46ebe2edeb624c1d1ae6f5c914dd0ae12fb0fa (diff)
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Add minimal support for machines without hardware interrupts
Some Chromebooks (with Baytrail CPUs) apparently do not support routing of legacy interrupts. This patch adds minimal support for running SeaBIOS in such an environment. Even with this patch, it is known that old operating systems and even some recent bootloaders will not function without real hardware interrupts. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/hw/timer.c')
-rw-r--r--src/hw/timer.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/hw/timer.c b/src/hw/timer.c
index 882b772..03d22b2 100644
--- a/src/hw/timer.c
+++ b/src/hw/timer.c
@@ -242,6 +242,8 @@ ticks_from_ms(u32 ms)
void
pit_setup(void)
{
+ if (!CONFIG_HARDWARE_IRQ)
+ return;
// timer0: binary count, 16bit count, mode 2
outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
// maximum count of 0000H = 18.2Hz