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author | Kevin O'Connor <kevin@koconnor.net> | 2015-07-23 08:36:01 -0400 |
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committer | Kevin O'Connor <kevin@koconnor.net> | 2015-07-23 08:36:01 -0400 |
commit | 4ec872aac65d59e0c28252051a7415f28971dd64 (patch) | |
tree | 3442e95f4e7696e2238c4f7dbe9011d388a37bee /src/hw/timer.c | |
parent | bbb3fbac21c7d3839654bf1c352423b424dbaeb3 (diff) | |
download | seabios-hppa-4ec872aac65d59e0c28252051a7415f28971dd64.zip seabios-hppa-4ec872aac65d59e0c28252051a7415f28971dd64.tar.gz seabios-hppa-4ec872aac65d59e0c28252051a7415f28971dd64.tar.bz2 |
timer: Add CONFIG_TSC_TIMER build option to disable the CPU TSC timer
Allow users to remove the CPU timestamp counter support at compile
time. The PMTIMER is frequently used instead of the TSC and this
compile time option allows one to strip a few bytes from the final
binary. This change also defaults the internal timer to use the PIT
based timer until the PMTIMER or TSC is detected.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/hw/timer.c')
-rw-r--r-- | src/hw/timer.c | 23 |
1 files changed, 8 insertions, 15 deletions
diff --git a/src/hw/timer.c b/src/hw/timer.c index 5edc9fd..882b772 100644 --- a/src/hw/timer.c +++ b/src/hw/timer.c @@ -49,8 +49,8 @@ #define PMTIMER_HZ 3579545 // Underlying Hz of the PM Timer #define PMTIMER_TO_PIT 3 // Ratio of pmtimer rate to pit rate -u32 TimerKHz VARFSEG; -u16 TimerPort VARFSEG; +u32 TimerKHz VARFSEG = DIV_ROUND_UP(PMTIMER_HZ, 1000 * PMTIMER_TO_PIT); +u16 TimerPort VARFSEG = PORT_PIT_COUNTER0; u8 ShiftTSC VARFSEG; @@ -92,6 +92,7 @@ tsctimer_setup(void) t = (t + 1) >> 1; } TimerKHz = DIV_ROUND_UP((u32)t, 1000 * PMTIMER_TO_PIT); + TimerPort = 0; dprintf(1, "CPU Mhz=%u\n", (TimerKHz << ShiftTSC) / 1000); } @@ -100,24 +101,16 @@ tsctimer_setup(void) void timer_setup(void) { - if (CONFIG_PMTIMER && TimerPort) { - dprintf(3, "pmtimer already configured; will not calibrate TSC\n"); + if (!CONFIG_TSC_TIMER || (CONFIG_PMTIMER && TimerPort != PORT_PIT_COUNTER0)) return; - } + // Check if CPU has a timestamp counter u32 eax, ebx, ecx, edx, cpuid_features = 0; cpuid(0, &eax, &ebx, &ecx, &edx); if (eax > 0) cpuid(1, &eax, &ebx, &ecx, &cpuid_features); - - if (!(cpuid_features & CPUID_TSC)) { - TimerPort = PORT_PIT_COUNTER0; - TimerKHz = DIV_ROUND_UP(PMTIMER_HZ, 1000 * PMTIMER_TO_PIT); - dprintf(3, "386/486 class CPU. Using TSC emulation\n"); - return; - } - - tsctimer_setup(); + if (cpuid_features & CPUID_TSC) + tsctimer_setup(); } void @@ -154,7 +147,7 @@ static u32 timer_read(void) { u16 port = GET_GLOBAL(TimerPort); - if (!port) + if (CONFIG_TSC_TIMER && !port) // Read from CPU TSC return rdtscll() >> GET_GLOBAL(ShiftTSC); if (CONFIG_PMTIMER && port != PORT_PIT_COUNTER0) |