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| author | Chen Fan <chen.fan.fnst@cn.fujitsu.com> | 2015-01-28 16:05:13 +0800 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2015-02-24 11:58:20 -0500 |
| commit | 32ec3eed5046d0d45bcf30911a39aaea17b0cfa7 (patch) | |
| tree | 8992a21121f559ba762c29658adb7e834d01e552 /src/fw | |
| parent | 339ef2e1d30be0c0477851afef3f2f53f6b469a5 (diff) | |
| download | seabios-hppa-32ec3eed5046d0d45bcf30911a39aaea17b0cfa7.zip seabios-hppa-32ec3eed5046d0d45bcf30911a39aaea17b0cfa7.tar.gz seabios-hppa-32ec3eed5046d0d45bcf30911a39aaea17b0cfa7.tar.bz2 | |
pci: enable SERR# for error forwarding in bridge control register
For PCIe device support AER(Advanced Error Reporting), from the
pcie spec 3.0 chapter 6.2.5, ERR_COR, ERR_NONFATAL, and ERR_FATAL
can be forwarded from the secondary interface to the primary interface,
only require the SERR# Enable bit in the Bridge Control register is set.
and at the kernel side, we found only _HPP() method can enable
SERR#, So here we want to turn on this bit.
Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com>
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/fw')
| -rw-r--r-- | src/fw/pciinit.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 3e6308a..b1c72c4 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -316,6 +316,10 @@ static void pci_bios_init_device(struct pci_device *pci) /* enable memory mappings */ pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR); + /* enable SERR# for forwarding */ + if (pci->header_type & PCI_HEADER_TYPE_BRIDGE) + pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, + PCI_BRIDGE_CTL_SERR); } static void pci_bios_init_devices(void) |