ahci: Convert to new PCI BAR helper functions

Use the pci_enable_x() functions.

This patch also converts cntl->iobase from a 'u32' to a 'void*' so
that it is clear that the address is a virtual memory address.

After this change, the AHCI driver will no longer enable
PCI_COMMAND_IO io accesses, as the AHCI driver doesn't actually
attempt IO accesses to the device.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>

2 files changed, 17 insertions, 21 deletions

diff --git a/src/hw/ahci.c b/src/hw/ahci.c
index 83b747c..5401cca 100644
--- a/src/hw/ahci.c
+++ b/src/hw/ahci.c
@@ -71,14 +71,12 @@ static void sata_prep_atapi(struct sata_cmd_fis *fis, u16 blocksize)
 // ahci register access helpers
 static u32 ahci_ctrl_readl(struct ahci_ctrl_s *ctrl, u32 reg)
 {
-    u32 addr = ctrl->iobase + reg;
-    return readl((void*)addr);
+    return readl(ctrl->iobase + reg);
 }
 
 static void ahci_ctrl_writel(struct ahci_ctrl_s *ctrl, u32 reg, u32 val)
 {
-    u32 addr = ctrl->iobase + reg;
-    writel((void*)addr, val);
+    writel(ctrl->iobase + reg, val);
 }
 
 static u32 ahci_port_to_ctrl(u32 pnr, u32 port_reg)
@@ -567,31 +565,30 @@ ahci_port_detect(void *data)
 static void
 ahci_controller_setup(struct pci_device *pci)
 {
-    struct ahci_ctrl_s *ctrl = malloc_fseg(sizeof(*ctrl));
     struct ahci_port_s *port;
-    u16 bdf = pci->bdf;
     u32 val, pnr, max;
 
-    if (!ctrl) {
-        warn_noalloc();
+    if (create_bounce_buf() < 0)
         return;
-    }
 
-    if (create_bounce_buf() < 0) {
+    void *iobase = pci_enable_membar(pci, PCI_BASE_ADDRESS_5);
+    if (!iobase)
+        return;
+
+    struct ahci_ctrl_s *ctrl = malloc_fseg(sizeof(*ctrl));
+    if (!ctrl) {
         warn_noalloc();
-        free(ctrl);
         return;
     }
 
     ctrl->pci_tmp = pci;
-    ctrl->pci_bdf = bdf;
-    ctrl->iobase = pci_config_readl(bdf, PCI_BASE_ADDRESS_5);
-    ctrl->irq = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
-    dprintf(1, "AHCI controller at %02x.%x, iobase %x, irq %d\n",
-            bdf >> 3, bdf & 7, ctrl->iobase, ctrl->irq);
-
-    pci_config_maskw(bdf, PCI_COMMAND, 0,
-                     PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+    ctrl->iobase = iobase;
+    ctrl->irq = pci_config_readb(pci->bdf, PCI_INTERRUPT_LINE);
+    dprintf(1, "AHCI controller at %02x:%02x.%x, iobase %p, irq %d\n"
+            , pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf)
+            , pci_bdf_to_fn(pci->bdf), ctrl->iobase, ctrl->irq);
+
+    pci_enable_busmaster(pci);
 
     val = ahci_ctrl_readl(ctrl, HOST_CTL);
     ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN);
diff --git a/src/hw/ahci.h b/src/hw/ahci.h
index fa11d66..5c4f6e1 100644
--- a/src/hw/ahci.h
+++ b/src/hw/ahci.h
@@ -30,9 +30,8 @@ struct sata_cmd_fis {
 
 struct ahci_ctrl_s {
     struct pci_device *pci_tmp;
-    u16 pci_bdf;
     u8  irq;
-    u32 iobase;
+    void *iobase;
     u32 caps;
     u32 ports;
 };