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| author | Paolo Bonzini <pbonzini@redhat.com> | 2015-05-25 11:14:01 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2015-05-25 13:27:04 +0200 |
| commit | bac3766d3d0912bb8dc40ee8f6d0cc54e37c4db6 (patch) | |
| tree | ecccb69761e0424a1761c43b17d6cb4714e50fa9 /include | |
| parent | c2aa6a6a11c062dbf11dcbc757d10751bab393a5 (diff) | |
| download | qboot-bac3766d3d0912bb8dc40ee8f6d0cc54e37c4db6.zip qboot-bac3766d3d0912bb8dc40ee8f6d0cc54e37c4db6.tar.gz qboot-bac3766d3d0912bb8dc40ee8f6d0cc54e37c4db6.tar.bz2 | |
setup PCI devices
setup interrupt line, PCI bridges, and IDE devices
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/bios.h | 1 | ||||
| -rw-r--r-- | include/pci.h | 33 |
2 files changed, 33 insertions, 1 deletions
diff --git a/include/bios.h b/include/bios.h index ff2064b..eddca6b 100644 --- a/include/bios.h +++ b/include/bios.h @@ -38,6 +38,7 @@ extern void bios_irq(void); extern void bios_int10(void); extern void bios_int15(void); +extern void setup_pci(void); extern void setup_hw(void); extern void extract_acpi(void); extern void boot_from_fwcfg(void); diff --git a/include/pci.h b/include/pci.h index c12a784..6270ac4 100644 --- a/include/pci.h +++ b/include/pci.h @@ -39,6 +39,37 @@ static inline uint8_t pci_config_readb(uint16_t bdf, uint32_t addr) return inb(0xcfc | (addr & 3)); } -#define PCI_VENDOR_ID 0 +#define PCI_VENDOR_ID 0x00 +#define PCI_DEVICE_ID 0x02 +#define PCI_COMMAND 0x04 +#define PCI_CLASS_DEVICE 0x0a +#define PCI_HEADER_TYPE 0x0e +#define PCI_PRIMARY_BUS 0x18 +#define PCI_SECONDARY_BUS 0x19 +#define PCI_SUBORDINATE_BUS 0x1a +#define PCI_INTERRUPT_LINE 0x3c +#define PCI_INTERRUPT_PIN 0x3d +#define PCI_BRIDGE_CONTROL 0x3e + +/* PCI_COMMAND */ +#define PCI_COMMAND_DIS_INTX 0x400 + +/* PCI_CLASS_DEVICE */ +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_BRIDGE_PCI 0x0604 + +/* PCI_HEADER_TYPE */ +#define PCI_HEADER_TYPE_BRIDGE 1 +#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 + +/* PCI_BRIDGE_CONTROL */ +#define PCI_BRIDGE_CTL_SERR 0x02 + +/* PCI_VENDOR_ID / PCI_DEVICE_ID */ +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 +#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 +#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 #endif |