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path: root/lib/sbi/sbi_hart.c
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2022-04-28lib: sbi: Fix mstatus_init() for RV32 when Sscofpmf is not availableAnup Patel1-1/+3
The mhpmevent3h to mhpmevent31h CSRs are available on RV32 only when Sscofpmf extension is available so mstatus_init() should set this CSRs only when Sscofpmf extension is available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-04-28lib: sbi: Implement Sstc extensionAtish Patra1-0/+28
Recently, Sstc extension was ratified. It defines stimecmp which allows the supervisor mode to directly update the timecmp value without the need of the SBI call. The hardware also can inject the S-mode timer interrupt direclty to the supervisor without going through the M-mode. To maintain backward compatibility with the older software, SBI call now uses stimecmp directly if the hardware supports. Implement the Sstc extension. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-17lib: sbi/hart: preserve csr validation valueDmitry Dunaev1-3/+3
The OpenSBI hart init function hart_detect_features() try to read important CSRs but reasign the last read value to the variable that initially contains write probe value. So for series of CSRs (like PMPADDRx) the second CSR probe value will became the initial value of first probing CSR. To avoid of this issue the CSR read value should be saved in different variable. In this configuration the count of PMP will detect rightly if any PMPADDR is hardwired to zero. Signed-off-by: Dmitry Dunaev <dunaich@mail.ru> Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-11lib: irqchip/imsic: configure mstateenMayuresh Chitale1-0/+6
When mstateen registers are implemented, the AIA related configurations need to be done in mstateen for the IMSIC initialization to succeed. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-11lib: sbi: Detect Smstateen CSRs at boot-timeMayuresh Chitale1-0/+25
Extend HART feature detection to discover Smstateen CSRs at boot-time and configure mstateen envcfg bit depending on availability of menvcfg CSR. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-05lib: sbi: Enable Svpbmt extension in the menvcfg CSRAnup Patel1-0/+10
The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not available so we try to enable menvcfg.PBMTE bit irrespective whether Svpbmt is available or not. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Xiang W <wxjstz@126.com>
2022-04-05lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSRAnup Patel1-1/+32
The bits to configure/enable Zicbo[m|z] extensions in the menvcfg CSR are WARL. We try to enable these bits irrespective whether these extensions are available or not because writes to these bits will be ignored if these extensions are not available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Xiang W <wxjstz@126.com>
2022-04-05lib: sbi: Detect menvcfg CSR at boot timeAtish Patra1-0/+9
We add the menvcfg CSR as a HART feature and detect it at boot time using traping mechanism. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com>
2022-02-15lib: sbi: Detect AIA CSRs at boot-timeAnup Patel1-0/+11
We extend HART feature detection to discover AIA CSRs at boot-time. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-04lib: fix compilation when strings.h is includedPetro Karashchenko1-4/+4
In a systems that provide strings.h and it is included together with sbi_bitops.h the compilation error appears. The ffs() and fls() are provided by strings.h Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-04lib: sbi: Disable interrupt and inhibit counting in M-mode during initAtish Patra1-0/+18
Currently, the mhpmevent CSRs are untouched during hart init during cold/warm boot. Ideally, we should clear out all the bits except overflow and MINH bit. That is required to disable overflow interrupt and inhibit counting in M-mode to avoid any spurious interrupts before perf start. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2021-11-30lib: sbi: Fix missing spaceNikita Shubin1-1/+1
Fix missing space in sbi_hart_pmp_configure error printing. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by: Xiang w <wxjstz@126.com>
2021-11-11lib: sbi: Fix PMP address bits detectionVasan VS1-0/+4
We should ensure that pmpcfg0.pmp0cfg is set to zero before using pmpaddr0 CSR for detecting implemented PMP address bits. Fixes: bf21632860b4 ("lib: sbi: Detect PMP granularity and number of address bits") Signed-off-by: Vasan VS <vasan.vs@gmail.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
2021-11-11lib: sbi: Always enable access for all countersAtish Patra1-14/+7
OpenSBI doesn't use any counters for its own usage. Thus, all the counters can be made accessible for lower privilege mode always. However, the mcountinhibit must be set so that the counter doesn't increment. As a result, we don't have to enable/disable mcounteren at every start/stop. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-11-11lib: sbi: Delegate PMU counter overflow interrupt to S modeAtish Patra1-0/+3
OpenSBI doesn't handle PMU counters for now. Delegate the overflow counter to S-mode always. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-11-11lib: sbi: Detect Sscofpmf extension at run timeAtish Patra1-0/+12
Sscofpmf ISA extension introduces PMU counter overflow and filtering support. It introduces a read only `scountovf` csr that can be used to detect if a hart supports this extension at runtime. However, this feature is only useful if the hart already supports mcounteren and mcountinhibit. Add a dynamic detection mechanism and boot time print message if sscofpmf is present. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-11-02lib: sbi: Refine addr format in sbi_printfDong Du1-9/+2
Although we have PRILX to help us print unsigned long without considering the 32bit/64bit differences, there are still some places using 08lx and 016lx manually --- leading to redundant code. This commit fixes the issue by using PRILX all the time. Signed-off-by: Dong Du <Dd_nirvana@sjtu.edu.cn> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2021-07-11lib: sbi: Disable m/scounteren & enable mcountinhibitAtish Patra1-4/+21
Currently, all bits in mcountern are enabled unconditionally at boot time. With SBI PMU extension, all the programmable counters should enabled only during performance monitoring for a particular event. However, this is done only if mcountinhibit is implemented because the supervisor mode can not start/stop any event without mcountinhibit. Similarly, supervisor should take care enabling scounteren which allows U-mode to access programmable pmu counters. All the non-programmable ones (CY, TM, IR) should be enabled in M-mode because some userspace may rely on builtins such as __builtin_readcyclecounter. Supervisor OS can still disable them during initial configuration. Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-07-11lib: sbi: Detect number of bits implemented in mhpmcounterAtish Patra1-0/+48
RISC-V privilege specification allows the implementation to have less than 64 bits. Add a function to detect the number of implemented bits in mhpmcounter dynamically at runtime. Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-07-11lib: sbi: Remove stray '\' characterAtish Patra1-1/+1
Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-07-11lib: sbi: Detect mcountinihibit support at runtimeAtish Patra1-0/+11
RISC-V ISA specification v1.11 defined mcountinhibit CSR that allows software to stop any counter from incrementing. The SBI PMU extension depends on this CSR support in hardware. Define mcountinhibit as a hart specific feature and detect it at runtime. Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-06-02lib: sbi_scratch: remove owner from sbi_scratch_alloc_offsetHeinrich Schuchardt1-2/+1
The parameter owner of function sbi_scratch_alloc_offset() is never used. The scratch memory is small. We should not use it for debug information in future. Hence eliminate the parameter. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2021-04-05lib: fix csr detect supportXiang W1-3/+0
csr_read_allowed/csr_read_allowed requires trap.case to detect the results, but if no exception occurs, the value of trap.case will remain unchanged, which makes the detection results unreliable. Add code to initialize trap.case to 0. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2021-03-03lib: sbi: Add sbi_hart_reinit() functionAnup Patel1-12/+17
We add sbi_hart_reinit() function which will re-initialize HART CSRs assuming HART features are already detected. This new function will be useful in re-initializing HART after it resumes from HSM SUSPENDED state. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-12-04lib: sbi: Fix sbi_hart_switch_mode() for u-modeAnup Patel1-3/+5
We should check and access N-extension CSRs in sbi_hart_switch_mode() when next_mode is u-mode because N-extension is optional. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-26lib: sbi: Detect PMP granularity and number of address bitsAtish Patra1-4/+58
As per RISC-V privilege specification, a platform may choose to implement a coarser granularity scheme for PMP addresses. In that case, we shouldn't allow any pmp region size smaller than the platform supports. A platform may not also implement all the bits for a PMP address specified in the priv specification. The pmp range granularity and address bits should be detected dynamically before detecing PMP regions. Any pmp modification request beyond these detected value must not succeed. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-10-21lib: sbi: Display domain details in boot printsAnup Patel1-34/+10
We extend boot prints to display details of each domain. In the process, we remove sbi_hart_pmp_dump() because it shows redundant information which domain details already show. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-20lib: sbi: Configure PMP based on domain memory regionsAnup Patel1-15/+22
The PMP configuration on each HART should be only based on the memory regions of the assigned domain because each domain includes a memory region to protect the underlying firmware. This patch updates the sbi_hart_pmp_configure() function accordingly. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-20lib: sbi: Remove redundant sbi_hart_pmp_xyz() functionsAnup Patel1-42/+0
The sbi_hart_pmp_get() and sbi_hart_pmp_check_addr() functions are not used anymore hence this patch removes these functions. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-20lib: sbi: Remove redundant hartid parameter from sbi_hart_init()Anup Patel1-7/+7
The hartid parameter of sbi_hart_init() is not used anywhere in sbi_hart_init() implementation so let's remove it. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-10-20lib: sbi: Configure PMP late in coldboot and warmboot pathAnup Patel1-2/+2
We factor-out PMP configuration from sbi_hart_init() as a separate sbi_hart_pmp_configure() function and do the PMP configuration very late in coldboot and warmboot path just before platform_final_init(). Eventually, this enable us to configure PMP totally based on OpenSBI domain where OpenSBI domains can be parsed from device-tree in any of the platform operations except platform_final_init(). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-10-20include: sbi: Remove pmp_region callbacks from sbi_platform_operationsAnup Patel1-13/+1
The pmp_region_xyz() callbacks are not required in sbi_platform_operations because we will be using OpenSBI domain memory regions to program the PMP CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-10-20include: sbi: Remove redundant includes from sbi_platform.hAnup Patel1-0/+1
The sbi_ecall.h and sbi_trap.h are not required to be included in sbi_platform.h hence we remove it. This way sources requiring these headers will have to explicitly include it thereby reducing implicit includes. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-25lib: sbi: Fix PMP CSR detectionPragnesh Patel1-1/+1
HiFive unleashed currently implements fewer than 56 bits of physical address so existing PMP CSR detection is broken. PMP address register encodes bits 55-2 of a 56-bit physical address, Not all physical address bits may be implemented, So just check minimum 1 bit. Fixes: 74d1db706293 ("lib: sbi: Improve PMP CSR detection and progamming") Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-09-16lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() APIAnup Patel1-7/+21
We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-09include: Rename ECALL defines to match latest RISC-V specAnup Patel1-1/+1
We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that it matches latest RISC-V privilege spec. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-01lib: sbi: Detect and print MHPM counters at boot-timeAnup Patel1-0/+17
A RISC-V platform can leave unimplemented MHPM counters hard-wired to zero. We extend hart_detect_features() to detect MHPM counters which are accessible and not hard-wired to zero. We also print number of available MHPM counters as part of boot prints. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-01lib: sbi: Improve PMP CSR detection and progammingAnup Patel1-24/+48
As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-01lib: sbi: Remove redundant SBI_HART_HAS_PMP featureAnup Patel1-14/+1
The SBI_HART_HAS_PMP feature is redundant because we already have number of PMP regions returned by sbi_hart_pmp_count(). Checking whether PMP is supported for a HART can be simply done by checking non-zero value returned by sbi_hart_pmp_count(). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-06-20lib: Don't return any invalid error from SBI ecallAnup Patel1-1/+1
We should only return valid error codes from SBI ecalls as defined by the RISC-V SBI spec. To achieve this: 1. We use SBI_Exxxx defines for OpenSBI internal errors with error values starting from -1000 2. We use SBI_ERR_xxxx defines for errors defined by SBI spec 3. We map some of the SBI_Exxxx defines to SBI_ERR_xxxx defines which are semantically same 4. We throw a error print and force return error code to SBI_ERR_FAILED in sbi_ecall_handler() if we see an invalid error code being returned to S-mode Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-06-18lib: Fix the SBI_HART_HAS_MCOUNTEREN feature checkAlistair Francis1-1/+1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-06-18lib: Don't print delegation CSRs if there is no S-ModeAlistair Francis1-0/+4
If the platform doesn't support S-Mode don't print the delegation registers. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-06-08lib: Add RISC-V hypervisor v0.6.1 supportAnup Patel1-0/+1
To support RISC-V hypervisor v0.6.1, we: 1. Don't need to explicitly forward WFI traps from VS/VU-mode 2. Have to delegate virtual instruction trap to HS-mode 3. Have to update trap redirection for changes in HSTATUS CSR Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-19lib: sbi_hart: Detect number of supported PMP regionsAnup Patel1-36/+80
It is not mandatory for a RISC-V systems to implement all PMP regions so we have to check all PMPADDRx CSRs to determine excat number of supported PMP regions. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-05-19lib: sbi: Few cosmetic improvements to HART feature detectionAnup Patel1-20/+12
This patch does few cosmetic improvements to HART feature detection: 1. Remove sbi_ perfix from HART feature detection functions because all local/static functions in sbi_hart.c don't have sbi_ prefix 2. Remove sbi_hart_set_feature() because it's quite small and local/static in sbi_hart.c Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-19include: sbi: Use scratch pointer as parmeter in HART feature APIsAnup Patel1-23/+23
It makes more sense to have scratch pointer as parameter in HART feature APIs because: 1. We already have scratch pointer at places where these APIs are used. 2. This is consistent with lot of other APIs in sbi_hart.h Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-19lib: sbi: Improve get_feature_str() implementation and usageAnup Patel1-7/+11
We do following improvements for get_feature_str(): 1. We should return "none" from get_feature_str() no features available instead of sbi_boot_prints() explicitly handling failure. 2. We don't need to return failure (just like misa_xlen()) because we are returning "none" for no features and we are truncating output when space is not available. 3. Based on 1 and 2, the sbi_boot_prints() can be further simplified. 4. No need for two char[] in sbi_boot_prints() Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-19lib: sbi: detect features before everything else in sbi_hart_init()Anup Patel1-3/+3
We should detect HART features in sbi_hart_init() before mstatus_init(), delegate_traps() and pmp_init(). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-10lib: Add hart features in boot time printAtish Patra1-0/+77
We have now clear distinction between platform and hart features. Modify the boot print messages to print hart specific features in a string format. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-05-10lib: timer: Provide a hart based timer featureAtish Patra1-0/+6
As per the RISC-V specification, time value can be obtained from a time CSR implemented in hardware or a MMIO based IP block. Qemu virt machine already supports timer csr while CLINT provides the timer for other platforms. Implement a hart specific timer feature that can be detected at runtime. As CSR based timer implementation are faster than MMIO address based, it is always preferred over MMIO based one. Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu> Reviewed-by: Anup Patel <anup.patel@wdc.com>
generated by cgit v1.1 at 2024-08-28 05:35:17 +0000