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2024-03-11lib: sbi: call platform load/store emulatorsBo Gan2-2/+80
sbi_load/store_access_handler now tries to call platform emulators if defined. Otherwise, redirects the fault. If the platform code returns failure, this means the H/S/U has accessed the emulated devices in an unexpected manner, which is very likely caused by buggy code in H/S/U. We redirect the fault, so lower privileged level can get notified, and act accordingly. (E.g., oops in Linux) We let the handler truly fail if the trap was originated from M mode. In this case, something must be very wrong and we should just fail. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-11include: sbi: add emulate_load/store handler to platform opsBo Gan1-0/+8
This patch allows the platform to define load/store emulators. This enables a platform to trap-and-emulate special devices or filter access to existing physical devices. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-11lib: sbi: abstract out insn decoding to unify mem fault handlersBo Gan3-39/+127
This patch abstracts out the instruction decoding part of misaligned ld/st fault handlers, so it can be reused by ld/st access fault handlers. Also Added lb/lbu/sb decoding. (previously unreachable by misaligned fault) sbi_trap_emulate_load/store is now the common handler which takes a `emu` parameter that is responsible for emulating the misaligned or access fault. The `emu` callback is expected to fixup the fault, and based on the return code of `emu`, sbi_trap_emulate_load/store will: r/wlen => the fixup is successful and regs/mepc needs to be updated. 0 => the fixup is successful, but regs/mepc should be left untouched (this is usually used if `emu` does `sbi_trap_redirect`) -err => failed, sbi_trap_error will be called For now, load/store access faults are blindly redirected. It will be enhanced in the following patches. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-11lib: sbi: change prototype of sbi_misaligned_load/store_handlerBo Gan3-45/+35
This simplifies both handlers such that when the handler needs to redirect the original trap, it's readily available. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-11lib: sbi: change prototype of sbi_trap_redirectBo Gan2-2/+2
sbi_trap_redirect now uses const pointer to `trap`. This ensures the caller that we never change `trap` in sbi_trap_redirect. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-11include: sbi: rename sbi_misaligned_ldst.h to sbi_trap_ldst.hBo Gan3-4/+4
Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-11lib: sbi: rename sbi_misaligned_ldst.c to sbi_trap_ldst.cBo Gan2-1/+1
Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-10lib: sbi: Add initial domain context management supportQingyu Shang6-2/+242
The domain context management component in OpenSBI provides basic CPU context management routines for existing OpenSBI domain. As domain extension, it was initially designed to facilitate the suspension and resumption of domains, enabling secure domains to efficiently share CPU resources. The patch also provides an addition to the OpenSBI domain to provide updates on hart-domain assignment and declarations of contexts within the domain. Signed-off-by: Qingyu Shang <2931013282@sjtu.edu.cn> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Tested-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-10lib: tests: Add sbi_console testIvan Orlov3-0/+110
Add the test suite covering some of the functions from lib/sbi/sbi_console.c: putc, puts and printf. The test covers a variety of format specifiers for printf and different strings and characters for putc and puts. In order to do that, the test "mocks" the sbi_console_device structure by setting the 'console_dev' variable to the virtual console. Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2024-03-10lib: tests: Add a test for sbi_bitmapIvan Orlov2-0/+105
Add test suite covering all of the functions from lib/sbi/sbi_bitmap.c: __bitmap_and, __bitmap_or and __bitmap_xor. Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2024-03-10lib: Add SBIUnit testing macros and functionsIvan Orlov6-0/+126
This patch introduces all of the SBIUnit macros and functions which can be used during the test development process. Also, it defines the 'run_all_tests' function, which is being called during the 'init_coldboot' right after printing the boot hart information. Also, add the CONFIG_SBIUNIT Kconfig entry in order to be able to turn the tests on and off. When the CONFIG_SBIUNIT is disabled, the tests and all related code is excluded completely on the compilation stage. Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2024-03-10docs: Add documentation about tests and SBIUnitIvan Orlov2-0/+134
This patch contains the documentation for SBIUnit. It describes: - What is SBIUnit - Simple test writing scenario - How we can cover static functions - How we can "mock" structures in order to test the functions which operate on them - SBIUnit API Reference Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2024-03-09firmware: fw_base.S: fix _reset_regsXiang W1-5/+3
a3 and a4 cannot be reset because used in fw_platform_init. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-09firmware: fw_base.S: Remove _relocate_lotteryXiang W1-11/+6
Remove _relocate_lottery and use _boot_status instead. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-09firmware: fw_dynamic.S: Remove _bad_dynamic_infoXiang W1-8/+2
_bad_dynamic_info is same as _start_hang, so remove it. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-09firmware: fw_base: Simplified setup trap handlerXiang W1-12/+4
The same detection was done twice when setting mtvec and trap_exit. Merging can reduce code size. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-09firmware: fw_base.S: Simplify address getXiang W1-33/+11
Simplify address get and remove _link_start _link_end _load_start. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-05lib: sbi_misaligned_ldst: Add handling of C.LHU/C.LH and C.SHNylon Chen2-0/+17
Added exception handling for compressed instructions C.LHU, C.LH, and C.SH from the zcb extension to the sbi_misaligned_ldst library. Signed-off-by: Nylon Chen <nylon.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-04platform: andes: Drop andes_pmu_setup()Yu Chien Peter Lin2-24/+0
andes_pmu_setup() [1] was intended to populate event mapping from hardcoded arrays, however, this increases firmware size and we should just use PMU DT node [2] instead. Link: https://lists.infradead.org/pipermail/opensbi/2023-November/006032.html [1] Link: https://github.com/riscv-software-src/opensbi/blob/v1.4/docs/pmu_support.md#example-3 [2] Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-04lib: sbi: Add support for smcsrind and smcdelegAtish Patra3-7/+42
Smcsrind allows generic indirect CSR access mechanism while Smcdeleg allows delegating hpmcounters in Supervisor mode. Enable both extensions and set the appropriate bits in mstateen and menvcfg. Co-developed-by: Kaiwen Xue <kaiwenxue1@gmail.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-24lib: sbi_hsm: Restor hart state to stop when fails to startJoshua Yeong1-0/+4
Hart state should change back to hart stop when hsm_device_hart_start() or sbi_ipi_raw_send() fails to perform hart start. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-24docs/firmware: document new options for jump and payload firmwaresInochi Amaoto2-3/+19
Adding relocatable address brings new configuration options for jump and payload firmwares. Describe these new options in documentation. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-24platform: Apply relocatable addressInochi Amaoto2-4/+21
Since jump and payload firmware support relocatable address, make general platform use runtime relocatable address. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-24firmware: Add relocatable FW_PAYLOAD_FDT_ADDRInochi Amaoto2-0/+7
The fw_payload.bin has the same issue as described in previous patch. But only FW_PAYLOAD_FDT_ADDR is affected. Add FW_PAYLOAD_FDT_OFFSET to identify relocatable payload fdt address. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-24firmware: Add relocatable FW_JUMP_ADDR and FW_JUMP_FDT_ADDRInochi Amaoto2-4/+20
If FW_PIC=y is defined, the fw_jump.bin will be broken if FW_TEXT_START is wrong. This is not the desired behavior. Add two new variables to identify relocatable jump address: FW_JUMP_OFFSET and FW_JUMP_FDT_ADDR. To keep the existing ABI, FW_JUMP_ADDR and FW_JUMP_FDT_ADDR is prefered if they are defined. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-22platform: starfive: call starfive_jh7110_inst_init() in pm_reset_init()Nam Cao1-1/+6
The function starfive_jh7110_inst_init() initialize some power management unit address and clock addresses, needed for the reset driver. It doesn't do anything else, and also the reset driver doesn't work without calling this function. Thus, it does not make much sense that this function is independent from pm_reset_init(). Delete the separate call to starfive_jh7110_inst_init(), and instead just call this function inside pm_reset_init(). Doing this also fixes another problem: if starfive_jh7110_inst_init() returns an error code, it gets propagated to final_init() and OpenSBI hangs. This hang is not necessary, because failures within starfive_jh7110_inst_init() only mean OpenSBI cannot perform reboot or shutdown, but the system can still function normally. Signed-off-by: Nam Cao <namcao@linutronix.de> Tested-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-22platform: starfive: return error if needed devices are not presentNam Cao1-0/+4
Jh7110's reset driver needs power management device and clock controller device to work. Currently, the driver proceed anyway without these devices, and invalid addresses (jh7110_inst.pmu_reg_base and jh7110_inst.clk_reg_base) are used during reboot, which causes unpredictable broken behaviors. If these devices are not present, return -SBI_ENODEV. Signed-off-by: Nam Cao <namcao@linutronix.de> Tested-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-22platform: starfive: rename "stf,axp15060-regulator" -> "x-powers,axp15060"Nam Cao1-1/+1
OpenSBI uses the device tree compatible string "stf,axp15060-regulator" for the regulator node. However, the string used by U-Boot (and Linux) is actually "x-powers,axp15060". As OpenSBI gets the device tree from U-Boot, this causes the regulator device to be undetected, and OpenSBI does not use this device to perform board reset/shutdown. Rename this device tree compatible string to match U-Boot (and Linux). Signed-off-by: Nam Cao <namcao@linutronix.de> Acked-by: Minda Chen <minda.chen@starfivetech.com> Tested-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-22platform: starfive: remove redundant compatibility check in pmic_opsNam Cao1-22/+14
pmic_ops() is only called if a compatible device is found in device tree. It is redundant for this function to check the compability again. Remove this check. Signed-off-by: Nam Cao <namcao@linutronix.de> Tested-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-22platform: starfive: get I2C offset address from clocks propertyNam Cao1-10/+14
The current code gets the I2C offset address using the device tree node name: it get the I2C device index from the 4th character in the node name (for example, "i2c5" -> i2c device 5). However, the device tree node's name in U-Boot is actually just "i2c" without the number, so the current code cannot be used with the device tree from U-Boot. Get the I2C offset address from the "clocks" property instead. Signed-off-by: Nam Cao <namcao@linutronix.de> Reviewed-by: Minda Chen <minda.chen@starfivetech.com> Tested-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-22platform: starfive: correct system clock device tree nodeNam Cao1-1/+1
Starfive names the system clock device tree node "starfive,jh7110-clkgen" in all their git repositories. However, a different name is used in upstream U-Boot (and also Linux): "starfive,jh7110-syscrg". Since OpenSBI gets the device tree from U-Boot, this inconsistency leads the problem that OpenSBI doesn't know the system clock device exists. Correct this name to keep the consistency. Signed-off-by: Nam Cao <namcao@linutronix.de> Acked-by: Minda Chen <minda.chen@starfivetech.com> Tested-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-20lib: sbi_pmu: Before using we should ensure PMU init doneyang.zhang1-2/+25
If trap earlier before sbi_pmu_init done, some path would call sbi_pmu_ctr_incr_fw, then it would go wrong: 1. if phs_ptr_offset is zero, then it get a wrong pmu state ptr 2. if phs_ptr_offset is ok, but we didn't call pmu_set_hart_state_ptr it would be NULL POINT Of course, the above situation will not occur at present, but it is reasonable to check before using. Signed-off-by: yang.zhang <yang.zhang@hexintek.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-20docs: move documentation of system suspend test.Cheng Yang2-4/+4
This patch move documentation of "system-suspend-test" from docs/domain_support.md to docs/opensbi_config.md Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-20platform: generic: Parse system suspend test from config node.Cheng Yang1-1/+1
This patch update generic_domains_init() so that "system-suspend-test" is parsed from "/chosen/opensbi-config" DT node. Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-20docs: Add OpenSBI DT configuration guide.Cheng Yang2-0/+84
This patch add docs/opensbi_config.md which describes the "/chosen/opensbi-config" DT node and properties Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-20platform: generic: Add support for specify coldboot harts in DTCheng Yang3-1/+86
Added support for the generic platform to specify the set of coldboot hart in DT. If not specified in DT, all harts are allowed to coldboot as before. The functions related to sbi_hartmask are not available before coldboot, so I used bitmap, and added a new bitmap_test() function to test whether a certain bit of the bitmap is set. Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-06firmware: fw_base.S: remove _runtime_offsetXiang W1-6/+0
_runtime_offset is a variable not used elsewhere, so remove it. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-06firmware: fw_base.S: Improve loading u32Xiang W1-4/+4
lwu exists under the current rv64 and should also exist under the rv128 in the future, so I modified the conditions of conditional compilation so that it can adapt to the future situation Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-05firmware: always create dynsym sectionLeon M. Busch-George1-0/+5
With a bare-metal linkers (e.g. riscv64-elf-ld), there exists no dynsym section. The dynsym section is not used by OpenSBI but discarding it makes linkers with dynamic library support unhappy. Signed-off-by: Leon M. Busch-George <leon@georgemail.eu> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-05Makefile: check for --exclude-libsLeon M. Busch-George1-0/+5
While writing to the dynsym is futile, the --exclude-libs options is not recognized by all linkers (e.g. riscv64-elf-ld.bfd). Signed-off-by: Leon M. Busch-George <leon@georgemail.eu> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-05Makefile: don't pass -mstrict-align if not supportedKalle Wachsmuth1-4/+13
Support for that option will be added in LLVM 18: https://github.com/llvm/llvm-project/commit/23ce5368409c760f3dd49d0f17f34772b0b869d8 Clang 17.0.6, however, will error when passed the `-mstrict-align` flag. We should only use the flag if it is supported. Signed-off-by: Kalle Wachsmuth <kalle.wachsmuth@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Xiang W <wxjstz@126.com>
2024-02-05fw_base.S: Fix comment errorsZhang Runmin1-2/+2
When calling '_reset_regs', it'll reset all registers except some specific registers (ra, a0, a1, and a2). Both boot HART and non-boot HARTs will execute the '_start_warm' function. Therefore, when '_reset_regs' is called in '_start_warm', it will reset all registers except some specific registers (ra, a0, a1 and a2) for both boot HART and non-boot HARTs. Signed-off-by: Zhang Runmin <fmrt19zrmin@163.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-05lib: sbi: Use mask to check the free bit during trigger allocationHimanshu Chauhan1-1/+1
The trigger allocation function uses bit shift instead of mask to check the mapped status of the triggers. This causes index 0 to be return always. As a result, the older triggers are overwritten. Use the mask for MAPPED field in state word to check if the trigger is mapped. Fixes: 97f234f15 ("lib: sbi: Introduce the SBI debug triggers extension support") Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-01-10lib: sbi: Print number of debug triggers foundHimanshu Chauhan1-0/+2
Print the total number of triggers found on the boot hart. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-01-10lib: sbi: Implement SBI debug trigger extensionHimanshu Chauhan3-0/+80
This patch adds functions to register ecalls for debug triggers and handler to handle the debug trigger function IDs. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-01-10include: sbi: Add SBI debug trigger extension related definesHimanshu Chauhan1-0/+11
This patch adds defines for SBI debug trigger extension and function IDs to access the extension. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-01-10lib: sbi: Introduce the SBI debug triggers extension supportHimanshu Chauhan4-0/+863
RISC-V Debug specification includes Sdtrig ISA extension which describes Trigger Module. Triggers can cause a breakpoint exception or trace action without execution of a special instruction. They can be used to implement hardware breakpoints and watchpoints for native debugging. The SBI Debut Trigger extension (Draft v6) can be found at: https://lists.riscv.org/g/tech-debug/topic/99825362#1302 This patch is an initial implementation of SBI Debug Trigger Extension (Draft v6) in OpenSBI. The following features are supported: * mcontrol, mcontrol6 triggers * Breakpoint and trace actions NOTE: Chained triggers are not supported Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-01-10lib: sbi: Detect support of debug triggersHimanshu Chauhan2-0/+6
Detect if debug triggers, sdtrig extension, is supported by the CPU. The support is detected by access traps and ISA string parsing. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-01-10include: sbi: Introduce debug trigger register encodingsHimanshu Chauhan1-0/+249
This patch introduces Mcontrol and M6 control register encodings along with macros to manipulate them. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-01-10include: sbi: Add TINFO debug trigger CSRHimanshu Chauhan1-0/+1
Add the missing TINFO debug trigger CSR. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.1 at 2024-08-16 04:00:10 +0000