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| author | Xiang W <wxjstz@126.com> | 2024-03-04 20:15:52 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-03-09 18:16:04 +0530 |
| commit | 526b9ce0793ab6b1a2c11e19066d9400ea77f742 (patch) | |
| tree | f3d46edcee616f566eb4d32c609dd6f4fa93efc6 | |
| parent | 8151105af5e4bd5d2a17fe0babd6cff3b36496fb (diff) | |
| download | opensbi-526b9ce0793ab6b1a2c11e19066d9400ea77f742.zip opensbi-526b9ce0793ab6b1a2c11e19066d9400ea77f742.tar.gz opensbi-526b9ce0793ab6b1a2c11e19066d9400ea77f742.tar.bz2 | |
firmware: fw_base.S: fix _reset_regs
a3 and a4 cannot be reset because used in fw_platform_init.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | firmware/fw_base.S | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index d83397e..126b067 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -167,7 +167,7 @@ _relocate_done: /* At this point we are running from link address */ - /* Reset all registers except ra, a0, a1 and a2 for boot HART */ + /* Reset all registers except ra, a0, a1, a2, a3 and a4 for boot HART */ li ra, 0 call _reset_regs @@ -394,7 +394,7 @@ _wait_for_boot_hart: bne t0, t1, _wait_for_boot_hart _start_warm: - /* Reset all registers except ra, a0, a1 and a2 for non-boot HARTs */ + /* Reset all registers except ra, a0, a1, a2, a3 and a4 for non-boot HART */ li ra, 0 call _reset_regs @@ -745,7 +745,7 @@ _reset_regs: /* flush the instruction cache */ fence.i - /* Reset all registers except ra, a0, a1 and a2 */ + /* Reset all registers except ra, a0, a1, a2, a3 and a4 */ li sp, 0 li gp, 0 li tp, 0 @@ -754,8 +754,6 @@ _reset_regs: li t2, 0 li s0, 0 li s1, 0 - li a3, 0 - li a4, 0 li a5, 0 li a6, 0 li a7, 0 |