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authorSamuel Holland <samuel@sholland.org>2022-06-12 20:03:50 -0500
committerAnup Patel <anup@brainfault.org>2022-06-13 11:54:06 +0530
commit8c362e7d065eaf4d55da23a190a464ba870f89aa (patch)
tree0e329ebde4ba12c1119e7dfc299d63bcf33b0588 /platform
parent2ea7799d563ed9bbaf3b677728e928a6cd8f580c (diff)
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lib: irqchip/plic: Factor out a context init function
This simplifies both the callers and the callees by removing duplicated code and consolidating the error handling. It also fixes two bugs in the process: 1) ie_words was one too large when plic->num_src was a multiple of 32. 2) plic_set_ie takes a 32-bit mask, not a Boolean value, so the FPGA platforms previously only enabled one out of every 32 interrupts. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
Diffstat (limited to 'platform')
-rw-r--r--platform/fpga/ariane/platform.c19
-rw-r--r--platform/fpga/openpiton/platform.c19
2 files changed, 16 insertions, 22 deletions
diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c
index 3fdc03b..56a666b 100644
--- a/platform/fpga/ariane/platform.c
+++ b/platform/fpga/ariane/platform.c
@@ -99,24 +99,21 @@ static int ariane_console_init(void)
static int plic_ariane_warm_irqchip_init(int m_cntx_id, int s_cntx_id)
{
- size_t i, ie_words = ARIANE_PLIC_NUM_SOURCES / 32 + 1;
+ int ret;
/* By default, enable all IRQs for M-mode of target HART */
if (m_cntx_id > -1) {
- for (i = 0; i < ie_words; i++)
- plic_set_ie(&plic, m_cntx_id, i, 1);
+ ret = plic_context_init(&plic, m_cntx_id, true, 0x1);
+ if (ret)
+ return ret;
}
+
/* Enable all IRQs for S-mode of target HART */
if (s_cntx_id > -1) {
- for (i = 0; i < ie_words; i++)
- plic_set_ie(&plic, s_cntx_id, i, 1);
+ ret = plic_context_init(&plic, s_cntx_id, true, 0x0);
+ if (ret)
+ return ret;
}
- /* By default, enable M-mode threshold */
- if (m_cntx_id > -1)
- plic_set_thresh(&plic, m_cntx_id, 1);
- /* By default, disable S-mode threshold */
- if (s_cntx_id > -1)
- plic_set_thresh(&plic, s_cntx_id, 0);
return 0;
}
diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c
index 15e289a..7ca2123 100644
--- a/platform/fpga/openpiton/platform.c
+++ b/platform/fpga/openpiton/platform.c
@@ -134,24 +134,21 @@ static int openpiton_console_init(void)
static int plic_openpiton_warm_irqchip_init(int m_cntx_id, int s_cntx_id)
{
- size_t i, ie_words = plic.num_src / 32 + 1;
+ int ret;
/* By default, enable all IRQs for M-mode of target HART */
if (m_cntx_id > -1) {
- for (i = 0; i < ie_words; i++)
- plic_set_ie(&plic, m_cntx_id, i, 1);
+ ret = plic_context_init(&plic, m_cntx_id, true, 0x1);
+ if (ret)
+ return ret;
}
+
/* Enable all IRQs for S-mode of target HART */
if (s_cntx_id > -1) {
- for (i = 0; i < ie_words; i++)
- plic_set_ie(&plic, s_cntx_id, i, 1);
+ ret = plic_context_init(&plic, s_cntx_id, true, 0x0);
+ if (ret)
+ return ret;
}
- /* By default, enable M-mode threshold */
- if (m_cntx_id > -1)
- plic_set_thresh(&plic, m_cntx_id, 1);
- /* By default, disable S-mode threshold */
- if (s_cntx_id > -1)
- plic_set_thresh(&plic, s_cntx_id, 0);
return 0;
}