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author | Nylon Chen <nylon.chen@sifive.com> | 2023-02-10 16:52:38 +0800 |
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committer | Anup Patel <anup@brainfault.org> | 2023-02-27 11:22:11 +0530 |
commit | 30ea8069f4c704e67017215f90f74b8588ee9bdf (patch) | |
tree | 389237de2dabdc8e54ab040c039b76846fa6fbb1 /lib | |
parent | 4f2be401025d7f5095dd2a4d2acad0fa60ef15e0 (diff) | |
download | opensbi-30ea8069f4c704e67017215f90f74b8588ee9bdf.zip opensbi-30ea8069f4c704e67017215f90f74b8588ee9bdf.tar.gz opensbi-30ea8069f4c704e67017215f90f74b8588ee9bdf.tar.bz2 |
lib: sbi_hart: Enable hcontext and scontext
According to the description in "riscv-state-enable[0]", to access
h/scontext in S-Mode, we need to enable the 57th bit.
If it is not enabled, an "illegal instruction" error will occur.
Link: https://github.com/riscv/riscv-state-enable/blob/a28bfae443f350d5b4c42874f428367d5b322ffe/content.adoc [0]
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib')
-rw-r--r-- | lib/sbi/sbi_hart.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 02ce991..5e06918 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -90,6 +90,7 @@ static void mstatus_init(struct sbi_scratch *scratch) mstateen_val |= ((uint64_t)csr_read(CSR_MSTATEEN0H)) << 32; #endif mstateen_val |= SMSTATEEN_STATEN; + mstateen_val |= SMSTATEEN0_CONTEXT; mstateen_val |= SMSTATEEN0_HSENVCFG; if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMAIA)) |