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authorEric Lin <eric.lin@sifive.com>2024-07-30 17:30:22 +0800
committerAnup Patel <anup@brainfault.org>2024-08-01 20:13:18 +0530
commita2807646a85878cb631cbc2b012cf888fc4427d7 (patch)
tree17dc88bd92872e6b4bef45e96a0569ee4099b007 /lib/utils/serial/uart8250.c
parentbb7267a07f8f93b30355c66538f0752c4766b309 (diff)
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include: Adjust Sscofpmf mhpmevent mask for upper 6 bitsHEADmaster
Currently, OpenSBI reserves the upper 16 bits in mhpmevent for the Sscofpmf extension. However, according to the Sscofpmf extension specification [1], it only defines the upper 6 bits in mhpmevent for privilege mode inhibit and counter overflow disable. Other bits are defined by the platform for event selection. Since vendors might define raw event encoding exceeding 48 bits in mhpmevent, we should adjust the MHPMEVENT_SSCOF_MASK to support it. Link: https://github.com/riscv/riscv-isa-manual [1] Signed-off-by: Eric Lin <eric.lin@sifive.com> Reviewed-By: Xiang W <wxjstz@126.com> Reviewed-By: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils/serial/uart8250.c')
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