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| author | Samuel Holland <samuel.holland@sifive.com> | 2024-07-10 07:26:06 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-07-24 10:42:46 +0530 |
| commit | 4afb57c9ebe27e29ce3777024bfc186991a8b4fe (patch) | |
| tree | 75e23b51f978c3d25b1053b5fc3cd42c5c261a70 /lib/sbi | |
| parent | f7a92f6b67bda221e96eb8dfa54e1eb162fa984f (diff) | |
| download | opensbi-4afb57c9ebe27e29ce3777024bfc186991a8b4fe.zip opensbi-4afb57c9ebe27e29ce3777024bfc186991a8b4fe.tar.gz opensbi-4afb57c9ebe27e29ce3777024bfc186991a8b4fe.tar.bz2 | |
lib: sbi_hsm: Save/restore menvcfg only when it exists
Attempting to access the menvcfg CSR raises an illegal instruction
exception on hardware which implements Sm1p11 or older.
Fixes: e9ee9678ba50 ("lib: sbi: fwft: add support for SBI_FWFT_PTE_AD_HW_UPDATING")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/sbi')
| -rw-r--r-- | lib/sbi/sbi_hsm.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/lib/sbi/sbi_hsm.c b/lib/sbi/sbi_hsm.c index 7e32af3..3706acf 100644 --- a/lib/sbi/sbi_hsm.c +++ b/lib/sbi/sbi_hsm.c @@ -423,10 +423,12 @@ void __sbi_hsm_suspend_non_ret_save(struct sbi_scratch *scratch) hdata->saved_mie = csr_read(CSR_MIE); hdata->saved_mip = csr_read(CSR_MIP) & (MIP_SSIP | MIP_STIP); hdata->saved_medeleg = csr_read(CSR_MEDELEG); + if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_12) { #if __riscv_xlen == 32 - hdata->saved_menvcfgh = csr_read(CSR_MENVCFGH); + hdata->saved_menvcfgh = csr_read(CSR_MENVCFGH); #endif - hdata->saved_menvcfg = csr_read(CSR_MENVCFG); + hdata->saved_menvcfg = csr_read(CSR_MENVCFG); + } } static void __sbi_hsm_suspend_non_ret_restore(struct sbi_scratch *scratch) @@ -434,10 +436,12 @@ static void __sbi_hsm_suspend_non_ret_restore(struct sbi_scratch *scratch) struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch, hart_data_offset); - csr_write(CSR_MENVCFG, hdata->saved_menvcfg); + if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_12) { + csr_write(CSR_MENVCFG, hdata->saved_menvcfg); #if __riscv_xlen == 32 - csr_write(CSR_MENVCFGH, hdata->saved_menvcfgh); + csr_write(CSR_MENVCFGH, hdata->saved_menvcfgh); #endif + } csr_write(CSR_MEDELEG, hdata->saved_medeleg); csr_write(CSR_MIE, hdata->saved_mie); csr_set(CSR_MIP, (hdata->saved_mip & (MIP_SSIP | MIP_STIP))); |