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| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2023-03-25 22:20:47 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-04-06 18:52:03 +0530 |
| commit | 8e90259da8b4b5bc6c934506cc4302578d44dbc2 (patch) | |
| tree | 6a38a05e971bf6d0ffcce5da92a83b738f258a6f /firmware | |
| parent | 30b9e7ee14498e5db805f471dbb23ea67c7a3b32 (diff) | |
| download | opensbi-8e90259da8b4b5bc6c934506cc4302578d44dbc2.zip opensbi-8e90259da8b4b5bc6c934506cc4302578d44dbc2.tar.gz opensbi-8e90259da8b4b5bc6c934506cc4302578d44dbc2.tar.bz2 | |
lib: sbi_hart: clear mip csr during hart init
If mip.SEIP bit is not cleared then on HiFive Unmatched board it causes
spurious external interrupts. This breaks the boot up of HiFive Unmatched
board. Hence it is required to bring the mip CSR to a known state during
hart init and avoid spurious interrupts.
Fixes: d9e7368 ("firmware: Not to clear all the MIP")
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/fw_base.S | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index ceef44f..5a3e894 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -430,13 +430,6 @@ _start_warm: /* Disable all interrupts */ csrw CSR_MIE, zero - /* - * Only clear the MIP_SSIP and MIP_STIP. For the platform like QEMU, - * If we clear other interrupts like MIP_SEIP and the pendings of - * PLIC still exist, the QEMU may not set it back immediately. - */ - li t0, (MIP_SSIP | MIP_STIP) - csrc CSR_MIP, t0 /* Find HART count and HART stack size */ lla a4, platform |