diff options
author | Vivian Wang <dramforever@live.com> | 2023-09-18 01:52:50 +0800 |
---|---|---|
committer | Anup Patel <anup@brainfault.org> | 2023-10-06 09:21:23 +0530 |
commit | 2a6d72534d44c39e1de0614970a0dad97b1c41ba (patch) | |
tree | 69a2a42c6abca54f0121aeef2c6da6733f7ed9e8 /firmware | |
parent | de525ac18dc32bafc64e78893f343afdd6003028 (diff) | |
download | opensbi-2a6d72534d44c39e1de0614970a0dad97b1c41ba.zip opensbi-2a6d72534d44c39e1de0614970a0dad97b1c41ba.tar.gz opensbi-2a6d72534d44c39e1de0614970a0dad97b1c41ba.tar.bz2 |
firmware: Remove handling of R_RISCV_{32,64}
Since everything is statically linked, we won't actually have
R_RISCV_{32,64} relocations. No need to handle these.
Fixes: 0f20e8adcf42 ("firmware: Support position independent execution")
Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/fw_base.S | 22 | ||||
-rw-r--r-- | firmware/fw_base.ldS | 6 |
2 files changed, 0 insertions, 28 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index ca34b4c..42b03fe 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -88,30 +88,8 @@ _try_lottery: add t5, t5, t2 add t3, t3, t2 REG_S t5, 0(t3) /* store runtime address to the GOT entry */ - j 5f 3: - lla t4, __dyn_sym_start - -4: - srli t6, t5, SYM_INDEX /* t6 <--- sym table index */ - andi t5, t5, 0xFF /* t5 <--- relocation type */ - li t3, RELOC_TYPE - bne t5, t3, 5f - - /* address R_RISCV_64 or R_RISCV_32 cases*/ - REG_L t3, 0(t0) - li t5, SYM_SIZE - mul t6, t6, t5 - add s5, t4, t6 - REG_L t6, (REGBYTES * 2)(t0) /* t0 <-- addend */ - REG_L t5, REGBYTES(s5) - add t5, t5, t6 - add t5, t5, t2 /* t5 <-- location to fix up in RAM */ - add t3, t3, t2 /* t3 <-- location to fix up in RAM */ - REG_S t5, 0(t3) /* store runtime address to the variable */ - -5: addi t0, t0, (REGBYTES * 3) blt t0, t1, 2b j _relocate_done diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS index 88b8dfd..c15ccdb 100644 --- a/firmware/fw_base.ldS +++ b/firmware/fw_base.ldS @@ -40,12 +40,6 @@ . = ALIGN(0x1000); /* Ensure next section is page aligned */ - .dynsym : { - PROVIDE(__dyn_sym_start = .); - *(.dynsym) - PROVIDE(__dyn_sym_end = .); - } - .rela.dyn : { PROVIDE(__rel_dyn_start = .); *(.rela*) |