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authorQingyu Shang <2931013282@sjtu.edu.cn>2024-03-06 19:15:58 +0800
committerAnup Patel <anup@brainfault.org>2024-03-10 10:26:42 +0530
commite11025c52d70c8a6042965d5f368ae9d14bd80d6 (patch)
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parent87d8fe78653e77de33cc12b9df07fc3a202f7d49 (diff)
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lib: sbi: Add initial domain context management support
The domain context management component in OpenSBI provides basic CPU context management routines for existing OpenSBI domain. As domain extension, it was initially designed to facilitate the suspension and resumption of domains, enabling secure domains to efficiently share CPU resources. The patch also provides an addition to the OpenSBI domain to provide updates on hart-domain assignment and declarations of contexts within the domain. Signed-off-by: Qingyu Shang <2931013282@sjtu.edu.cn> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Tested-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'docs')
-rw-r--r--docs/domain_support.md2
1 files changed, 2 insertions, 0 deletions
diff --git a/docs/domain_support.md b/docs/domain_support.md
index 65b6142..b34e43a 100644
--- a/docs/domain_support.md
+++ b/docs/domain_support.md
@@ -41,6 +41,7 @@ has following details:
* **name** - Name of this domain
* **assigned_harts** - HARTs assigned to this domain
* **possible_harts** - HARTs possible in this domain
+* **hartindex_to_context_table** - Contexts corresponding to possible HARTs
* **regions** - Array of memory regions terminated by a memory region
with order zero
* **boot_hartid** - HART id of the HART booting this domain. The domain
@@ -80,6 +81,7 @@ following manner:
platform support
* **possible_harts** - All valid HARTs of a RISC-V platform are possible
HARTs of the ROOT domain
+* **hartindex_to_context_table** - Contexts corresponding to ROOT domain's possible HARTs
* **regions** - Two memory regions available to the ROOT domain:
**A)** A memory region to protect OpenSBI firmware from S-mode and U-mode
**B)** A memory region of **order=__riscv_xlen** allowing S-mode and