diff options
Diffstat (limited to 'src/arch')
98 files changed, 2168 insertions, 711 deletions
diff --git a/src/arch/arm/Makefile b/src/arch/arm/Makefile index b6509dd..f827ed4 100644 --- a/src/arch/arm/Makefile +++ b/src/arch/arm/Makefile @@ -3,9 +3,9 @@ ASM_TCHAR := % ASM_TCHAR_OPS := %% -# Include common ARM headers +# Include ARM-specific headers # -INCDIRS += arch/arm/include +INCDIRS := arch/$(ARCH)/include arch/arm/include $(INCDIRS) # ARM-specific directories containing source files # diff --git a/src/arch/arm/include/bits/acpi.h b/src/arch/arm/include/bits/acpi.h deleted file mode 100644 index f9f2f00..0000000 --- a/src/arch/arm/include/bits/acpi.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_ACPI_H -#define _BITS_ACPI_H - -/** @file - * - * ARM-specific ACPI API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_ACPI_H */ diff --git a/src/arch/arm/include/bits/hyperv.h b/src/arch/arm/include/bits/hyperv.h deleted file mode 100644 index f0e0c87..0000000 --- a/src/arch/arm/include/bits/hyperv.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_HYPERV_H -#define _BITS_HYPERV_H - -/** @file - * - * Hyper-V interface - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_HYPERV_H */ diff --git a/src/arch/arm/include/bits/iomap.h b/src/arch/arm/include/bits/iomap.h deleted file mode 100644 index ae953c4..0000000 --- a/src/arch/arm/include/bits/iomap.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_IOMAP_H -#define _BITS_IOMAP_H - -/** @file - * - * ARM-specific I/O mapping API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_IOMAP_H */ diff --git a/src/arch/arm/include/bits/mp.h b/src/arch/arm/include/bits/mp.h deleted file mode 100644 index e7d4c0c..0000000 --- a/src/arch/arm/include/bits/mp.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_MP_H -#define _BITS_MP_H - -/** @file - * - * ARM-specific multiprocessor API implementation - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_MP_H */ diff --git a/src/arch/arm/include/bits/nap.h b/src/arch/arm/include/bits/nap.h index e30a714..dbdf371 100644 --- a/src/arch/arm/include/bits/nap.h +++ b/src/arch/arm/include/bits/nap.h @@ -9,6 +9,12 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); -#include <ipxe/efi/efiarm_nap.h> +/** + * Sleep until next CPU interrupt + * + */ +static inline __attribute__ (( always_inline )) void cpu_halt ( void ) { + __asm__ __volatile__ ( "wfi" ); +} -#endif /* _BITS_MAP_H */ +#endif /* _BITS_NAP_H */ diff --git a/src/arch/arm/include/bits/pci_io.h b/src/arch/arm/include/bits/pci_io.h deleted file mode 100644 index 91f507a..0000000 --- a/src/arch/arm/include/bits/pci_io.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_PCI_IO_H -#define _BITS_PCI_IO_H - -/** @file - * - * ARM PCI I/O API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_PCI_IO_H */ diff --git a/src/arch/arm/include/bits/reboot.h b/src/arch/arm/include/bits/reboot.h deleted file mode 100644 index 88c5025..0000000 --- a/src/arch/arm/include/bits/reboot.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_REBOOT_H -#define _BITS_REBOOT_H - -/** @file - * - * ARM-specific reboot API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_REBOOT_H */ diff --git a/src/arch/arm/include/bits/sanboot.h b/src/arch/arm/include/bits/sanboot.h deleted file mode 100644 index abd4c79..0000000 --- a/src/arch/arm/include/bits/sanboot.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_SANBOOT_H -#define _BITS_SANBOOT_H - -/** @file - * - * ARM-specific sanboot API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_SANBOOT_H */ diff --git a/src/arch/arm/include/bits/smbios.h b/src/arch/arm/include/bits/smbios.h deleted file mode 100644 index d942181..0000000 --- a/src/arch/arm/include/bits/smbios.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_SMBIOS_H -#define _BITS_SMBIOS_H - -/** @file - * - * ARM-specific SMBIOS API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_SMBIOS_H */ diff --git a/src/arch/arm/include/bits/time.h b/src/arch/arm/include/bits/time.h deleted file mode 100644 index 724d8b9..0000000 --- a/src/arch/arm/include/bits/time.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_TIME_H -#define _BITS_TIME_H - -/** @file - * - * ARM-specific time API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_TIME_H */ diff --git a/src/arch/arm/include/bits/uaccess.h b/src/arch/arm/include/bits/uaccess.h deleted file mode 100644 index 87f1150..0000000 --- a/src/arch/arm/include/bits/uaccess.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_UACCESS_H -#define _BITS_UACCESS_H - -/** @file - * - * ARM-specific user access API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_UACCESS_H */ diff --git a/src/arch/arm/include/bits/uart.h b/src/arch/arm/include/bits/uart.h deleted file mode 100644 index 6f85975..0000000 --- a/src/arch/arm/include/bits/uart.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_UART_H -#define _BITS_UART_H - -/** @file - * - * 16550-compatible UART - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_UART_H */ diff --git a/src/arch/arm/include/bits/umalloc.h b/src/arch/arm/include/bits/umalloc.h deleted file mode 100644 index 27970d7..0000000 --- a/src/arch/arm/include/bits/umalloc.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_UMALLOC_H -#define _BITS_UMALLOC_H - -/** @file - * - * ARM-specific user memory allocation API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_UMALLOC_H */ diff --git a/src/arch/arm/include/ipxe/efi/efiarm_nap.h b/src/arch/arm/include/ipxe/efi/efiarm_nap.h deleted file mode 100644 index dcbdd3e..0000000 --- a/src/arch/arm/include/ipxe/efi/efiarm_nap.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _IPXE_EFIARM_NAP_H -#define _IPXE_EFIARM_NAP_H - -/** @file - * - * EFI CPU sleeping - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#ifdef NAP_EFIARM -#define NAP_PREFIX_efiarm -#else -#define NAP_PREFIX_efiarm __efiarm_ -#endif - -#endif /* _IPXE_EFIARM_NAP_H */ diff --git a/src/arch/arm32/Makefile.efi b/src/arch/arm32/Makefile.efi index d720f34..9bd3438 100644 --- a/src/arch/arm32/Makefile.efi +++ b/src/arch/arm32/Makefile.efi @@ -8,10 +8,6 @@ CFLAGS += -mfloat-abi=soft # ELF2EFI = $(ELF2EFI32) -# Specify EFI boot file -# -EFI_BOOT_FILE = bootarm.efi - # Include generic EFI Makefile # MAKEDEPS += arch/arm/Makefile.efi diff --git a/src/arch/arm32/include/setjmp.h b/src/arch/arm32/include/bits/setjmp.h index 4828b47..9ee264e 100644 --- a/src/arch/arm32/include/setjmp.h +++ b/src/arch/arm32/include/bits/setjmp.h @@ -1,5 +1,5 @@ -#ifndef _SETJMP_H -#define _SETJMP_H +#ifndef _BITS_SETJMP_H +#define _BITS_SETJMP_H FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); @@ -29,10 +29,4 @@ typedef struct { uint32_t lr; } jmp_buf[1]; -extern int __asmcall __attribute__ (( returns_twice )) -setjmp ( jmp_buf env ); - -extern void __asmcall __attribute__ (( noreturn )) -longjmp ( jmp_buf env, int val ); - -#endif /* _SETJMP_H */ +#endif /* _BITS_SETJMP_H */ diff --git a/src/arch/arm32/include/bits/tcpip.h b/src/arch/arm32/include/bits/tcpip.h deleted file mode 100644 index fc3c5b3..0000000 --- a/src/arch/arm32/include/bits/tcpip.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _BITS_TCPIP_H -#define _BITS_TCPIP_H - -/** @file - * - * Transport-network layer interface - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -static inline __attribute__ (( always_inline )) uint16_t -tcpip_continue_chksum ( uint16_t partial, const void *data, size_t len ) { - - /* Not yet optimised */ - return generic_tcpip_continue_chksum ( partial, data, len ); -} - -#endif /* _BITS_TCPIP_H */ diff --git a/src/arch/arm32/include/gdbmach.h b/src/arch/arm32/include/gdbmach.h deleted file mode 100644 index cd152ee..0000000 --- a/src/arch/arm32/include/gdbmach.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef GDBMACH_H -#define GDBMACH_H - -/** @file - * - * GDB architecture specifics - * - * This file declares functions for manipulating the machine state and - * debugging context. - * - */ - -#include <stdint.h> - -typedef unsigned long gdbreg_t; - -/* Register snapshot */ -enum { - /* Not yet implemented */ - GDBMACH_NREGS, -}; - -#define GDBMACH_SIZEOF_REGS ( GDBMACH_NREGS * sizeof ( gdbreg_t ) ) - -static inline void gdbmach_set_pc ( gdbreg_t *regs, gdbreg_t pc ) { - /* Not yet implemented */ - ( void ) regs; - ( void ) pc; -} - -static inline void gdbmach_set_single_step ( gdbreg_t *regs, int step ) { - /* Not yet implemented */ - ( void ) regs; - ( void ) step; -} - -static inline void gdbmach_breakpoint ( void ) { - /* Not yet implemented */ -} - -extern int gdbmach_set_breakpoint ( int type, unsigned long addr, size_t len, - int enable ); -extern void gdbmach_init ( void ); - -#endif /* GDBMACH_H */ diff --git a/src/arch/arm64/Makefile.efi b/src/arch/arm64/Makefile.efi index 998a64d..96f2953 100644 --- a/src/arch/arm64/Makefile.efi +++ b/src/arch/arm64/Makefile.efi @@ -4,10 +4,6 @@ # ELF2EFI = $(ELF2EFI64) -# Specify EFI boot file -# -EFI_BOOT_FILE = bootaa64.efi - # Include generic EFI Makefile # MAKEDEPS += arch/arm/Makefile.efi diff --git a/src/arch/arm64/include/setjmp.h b/src/arch/arm64/include/bits/setjmp.h index 85a7a9c..6ffd2fb 100644 --- a/src/arch/arm64/include/setjmp.h +++ b/src/arch/arm64/include/bits/setjmp.h @@ -1,5 +1,5 @@ -#ifndef _SETJMP_H -#define _SETJMP_H +#ifndef _BITS_SETJMP_H +#define _BITS_SETJMP_H FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); @@ -35,10 +35,4 @@ typedef struct { uint64_t sp; } jmp_buf[1]; -extern int __asmcall __attribute__ (( returns_twice )) -setjmp ( jmp_buf env ); - -extern void __asmcall __attribute__ (( noreturn )) -longjmp ( jmp_buf env, int val ); - -#endif /* _SETJMP_H */ +#endif /* _BITS_SETJMP_H */ diff --git a/src/arch/arm64/include/gdbmach.h b/src/arch/arm64/include/gdbmach.h deleted file mode 100644 index cd152ee..0000000 --- a/src/arch/arm64/include/gdbmach.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef GDBMACH_H -#define GDBMACH_H - -/** @file - * - * GDB architecture specifics - * - * This file declares functions for manipulating the machine state and - * debugging context. - * - */ - -#include <stdint.h> - -typedef unsigned long gdbreg_t; - -/* Register snapshot */ -enum { - /* Not yet implemented */ - GDBMACH_NREGS, -}; - -#define GDBMACH_SIZEOF_REGS ( GDBMACH_NREGS * sizeof ( gdbreg_t ) ) - -static inline void gdbmach_set_pc ( gdbreg_t *regs, gdbreg_t pc ) { - /* Not yet implemented */ - ( void ) regs; - ( void ) pc; -} - -static inline void gdbmach_set_single_step ( gdbreg_t *regs, int step ) { - /* Not yet implemented */ - ( void ) regs; - ( void ) step; -} - -static inline void gdbmach_breakpoint ( void ) { - /* Not yet implemented */ -} - -extern int gdbmach_set_breakpoint ( int type, unsigned long addr, size_t len, - int enable ); -extern void gdbmach_init ( void ); - -#endif /* GDBMACH_H */ diff --git a/src/arch/i386/Makefile.efi b/src/arch/i386/Makefile.efi index 37ede65..aa809eb 100644 --- a/src/arch/i386/Makefile.efi +++ b/src/arch/i386/Makefile.efi @@ -8,10 +8,6 @@ ELF2EFI = $(ELF2EFI32) # CFLAGS += -malign-double -# Specify EFI boot file -# -EFI_BOOT_FILE = bootia32.efi - # Include generic EFI Makefile # MAKEDEPS += arch/x86/Makefile.efi diff --git a/src/arch/i386/include/gdbmach.h b/src/arch/i386/include/bits/gdbmach.h index 52cce78..52cce78 100644 --- a/src/arch/i386/include/gdbmach.h +++ b/src/arch/i386/include/bits/gdbmach.h diff --git a/src/arch/i386/include/setjmp.h b/src/arch/i386/include/bits/setjmp.h index 9856669..6b2ec96 100644 --- a/src/arch/i386/include/setjmp.h +++ b/src/arch/i386/include/bits/setjmp.h @@ -1,5 +1,5 @@ -#ifndef _SETJMP_H -#define _SETJMP_H +#ifndef _BITS_SETJMP_H +#define _BITS_SETJMP_H FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); @@ -21,10 +21,4 @@ typedef struct { uint32_t ebp; } jmp_buf[1]; -extern int __asmcall __attribute__ (( returns_twice )) -setjmp ( jmp_buf env ); - -extern void __asmcall __attribute__ (( noreturn )) -longjmp ( jmp_buf env, int val ); - -#endif /* _SETJMP_H */ +#endif /* _BITS_SETJMP_H */ diff --git a/src/arch/loong64/Makefile b/src/arch/loong64/Makefile index fd0bf13..90d0ec8 100644 --- a/src/arch/loong64/Makefile +++ b/src/arch/loong64/Makefile @@ -18,6 +18,9 @@ endif # EFI requires -fshort-wchar, and nothing else currently uses wchar_t CFLAGS += -fshort-wchar +# Include LoongArch64-specific headers +INCDIRS := arch/$(ARCH)/include $(INCDIRS) + # LoongArch64-specific directories containing source files SRCDIRS += arch/loong64/core SRCDIRS += arch/loong64/interface/efi diff --git a/src/arch/loong64/Makefile.efi b/src/arch/loong64/Makefile.efi index 1c51bcd..611c910 100644 --- a/src/arch/loong64/Makefile.efi +++ b/src/arch/loong64/Makefile.efi @@ -4,10 +4,6 @@ # ELF2EFI = $(ELF2EFI64) -# Specify EFI boot file -# -EFI_BOOT_FILE = bootloongarch64.efi - # Include generic EFI Makefile # MAKEDEPS += Makefile.efi diff --git a/src/arch/loong64/include/bits/acpi.h b/src/arch/loong64/include/bits/acpi.h deleted file mode 100644 index 83dd1df..0000000 --- a/src/arch/loong64/include/bits/acpi.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_ACPI_H -#define _BITS_ACPI_H - -/** @file - * - * LoongArch64-specific ACPI API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_ACPI_H */ diff --git a/src/arch/loong64/include/bits/hyperv.h b/src/arch/loong64/include/bits/hyperv.h deleted file mode 100644 index f0e0c87..0000000 --- a/src/arch/loong64/include/bits/hyperv.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_HYPERV_H -#define _BITS_HYPERV_H - -/** @file - * - * Hyper-V interface - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_HYPERV_H */ diff --git a/src/arch/loong64/include/bits/iomap.h b/src/arch/loong64/include/bits/iomap.h deleted file mode 100644 index 041171d..0000000 --- a/src/arch/loong64/include/bits/iomap.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_IOMAP_H -#define _BITS_IOMAP_H - -/** @file - * - * LoongArch64-specific I/O mapping API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_IOMAP_H */ diff --git a/src/arch/loong64/include/bits/mp.h b/src/arch/loong64/include/bits/mp.h deleted file mode 100644 index fef2fd5..0000000 --- a/src/arch/loong64/include/bits/mp.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_MP_H -#define _BITS_MP_H - -/** @file - * - * LoongArch64-specific multiprocessor API implementation - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_MP_H */ diff --git a/src/arch/loong64/include/bits/nap.h b/src/arch/loong64/include/bits/nap.h index 2deba35..d904db5 100644 --- a/src/arch/loong64/include/bits/nap.h +++ b/src/arch/loong64/include/bits/nap.h @@ -9,6 +9,12 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); -#include <ipxe/efi/efiloong64_nap.h> +/** + * Sleep until next CPU interrupt + * + */ +static inline __attribute__ (( always_inline )) void cpu_halt ( void ) { + __asm__ __volatile__ ( "idle 0" ); +} #endif /* _BITS_NAP_H */ diff --git a/src/arch/loong64/include/bits/pci_io.h b/src/arch/loong64/include/bits/pci_io.h deleted file mode 100644 index fdc5141..0000000 --- a/src/arch/loong64/include/bits/pci_io.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_PCI_IO_H -#define _BITS_PCI_IO_H - -/** @file - * - * LoongArch64-specific PCI I/O API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_PCI_IO_H */ diff --git a/src/arch/loong64/include/bits/reboot.h b/src/arch/loong64/include/bits/reboot.h deleted file mode 100644 index 96a1eb1..0000000 --- a/src/arch/loong64/include/bits/reboot.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_REBOOT_H -#define _BITS_REBOOT_H - -/** @file - * - * LoongArch64-specific reboot API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_REBOOT_H */ diff --git a/src/arch/loong64/include/bits/sanboot.h b/src/arch/loong64/include/bits/sanboot.h deleted file mode 100644 index f9205e2..0000000 --- a/src/arch/loong64/include/bits/sanboot.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_SANBOOT_H -#define _BITS_SANBOOT_H - -/** @file - * - * LoongArch64-specific sanboot API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_SANBOOT_H */ diff --git a/src/arch/loong64/include/bits/setjmp.h b/src/arch/loong64/include/bits/setjmp.h new file mode 100644 index 0000000..c8d7cef --- /dev/null +++ b/src/arch/loong64/include/bits/setjmp.h @@ -0,0 +1,23 @@ +#ifndef _BITS_SETJMP_H +#define _BITS_SETJMP_H + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +/** A jump buffer */ +typedef struct { + uint64_t s0; + uint64_t s1; + uint64_t s2; + uint64_t s3; + uint64_t s4; + uint64_t s5; + uint64_t s6; + uint64_t s7; + uint64_t s8; + + uint64_t fp; + uint64_t sp; + uint64_t ra; +} jmp_buf[1]; + +#endif /* _BITS_SETJMP_H */ diff --git a/src/arch/loong64/include/bits/smbios.h b/src/arch/loong64/include/bits/smbios.h deleted file mode 100644 index 6c87db4..0000000 --- a/src/arch/loong64/include/bits/smbios.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_SMBIOS_H -#define _BITS_SMBIOS_H - -/** @file - * - * LoongArch64-specific SMBIOS API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_SMBIOS_H */ diff --git a/src/arch/loong64/include/bits/tcpip.h b/src/arch/loong64/include/bits/tcpip.h deleted file mode 100644 index fc3c5b3..0000000 --- a/src/arch/loong64/include/bits/tcpip.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _BITS_TCPIP_H -#define _BITS_TCPIP_H - -/** @file - * - * Transport-network layer interface - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -static inline __attribute__ (( always_inline )) uint16_t -tcpip_continue_chksum ( uint16_t partial, const void *data, size_t len ) { - - /* Not yet optimised */ - return generic_tcpip_continue_chksum ( partial, data, len ); -} - -#endif /* _BITS_TCPIP_H */ diff --git a/src/arch/loong64/include/bits/time.h b/src/arch/loong64/include/bits/time.h deleted file mode 100644 index 4cd7485..0000000 --- a/src/arch/loong64/include/bits/time.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_TIME_H -#define _BITS_TIME_H - -/** @file - * - * LoongArch64-specific time API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_TIME_H */ diff --git a/src/arch/loong64/include/bits/uaccess.h b/src/arch/loong64/include/bits/uaccess.h deleted file mode 100644 index dddd9be..0000000 --- a/src/arch/loong64/include/bits/uaccess.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_UACCESS_H -#define _BITS_UACCESS_H - -/** @file - * - * LoongArch64-specific user access API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_UACCESS_H */ diff --git a/src/arch/loong64/include/bits/uart.h b/src/arch/loong64/include/bits/uart.h deleted file mode 100644 index 6f85975..0000000 --- a/src/arch/loong64/include/bits/uart.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_UART_H -#define _BITS_UART_H - -/** @file - * - * 16550-compatible UART - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_UART_H */ diff --git a/src/arch/loong64/include/bits/umalloc.h b/src/arch/loong64/include/bits/umalloc.h deleted file mode 100644 index f6978b8..0000000 --- a/src/arch/loong64/include/bits/umalloc.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _BITS_UMALLOC_H -#define _BITS_UMALLOC_H - -/** @file - * - * LoongArch64-specific user memory allocation API implementations - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#endif /* _BITS_UMALLOC_H */ diff --git a/src/arch/loong64/include/bits/xen.h b/src/arch/loong64/include/bits/xen.h deleted file mode 100644 index 2a3d774..0000000 --- a/src/arch/loong64/include/bits/xen.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _BITS_XEN_H -#define _BITS_XEN_H - -/** @file - * - * Xen interface - * - */ -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#include <ipxe/nonxen.h> - -#endif /* _BITS_XEN_H */ diff --git a/src/arch/loong64/include/gdbmach.h b/src/arch/loong64/include/gdbmach.h deleted file mode 100644 index cd152ee..0000000 --- a/src/arch/loong64/include/gdbmach.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef GDBMACH_H -#define GDBMACH_H - -/** @file - * - * GDB architecture specifics - * - * This file declares functions for manipulating the machine state and - * debugging context. - * - */ - -#include <stdint.h> - -typedef unsigned long gdbreg_t; - -/* Register snapshot */ -enum { - /* Not yet implemented */ - GDBMACH_NREGS, -}; - -#define GDBMACH_SIZEOF_REGS ( GDBMACH_NREGS * sizeof ( gdbreg_t ) ) - -static inline void gdbmach_set_pc ( gdbreg_t *regs, gdbreg_t pc ) { - /* Not yet implemented */ - ( void ) regs; - ( void ) pc; -} - -static inline void gdbmach_set_single_step ( gdbreg_t *regs, int step ) { - /* Not yet implemented */ - ( void ) regs; - ( void ) step; -} - -static inline void gdbmach_breakpoint ( void ) { - /* Not yet implemented */ -} - -extern int gdbmach_set_breakpoint ( int type, unsigned long addr, size_t len, - int enable ); -extern void gdbmach_init ( void ); - -#endif /* GDBMACH_H */ diff --git a/src/arch/loong64/include/ipxe/efi/efiloong64_nap.h b/src/arch/loong64/include/ipxe/efi/efiloong64_nap.h deleted file mode 100644 index 5c0d386..0000000 --- a/src/arch/loong64/include/ipxe/efi/efiloong64_nap.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _IPXE_EFILOONG64_NAP_H -#define _IPXE_EFILOONG64_NAP_H - -/** @file - * - * EFI CPU sleeping - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#ifdef NAP_EFILOONG64 -#define NAP_PREFIX_efiloong64 -#else -#define NAP_PREFIX_efiloong64 __efiloong64_ -#endif - -#endif /* _IPXE_EFILOONG64_NAP_H */ diff --git a/src/arch/loong64/include/setjmp.h b/src/arch/loong64/include/setjmp.h deleted file mode 100644 index 1e51683..0000000 --- a/src/arch/loong64/include/setjmp.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _SETJMP_H -#define _SETJMP_H - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#include <stdint.h> - -/** jump buffer env*/ -typedef struct { - uint64_t s0; - uint64_t s1; - uint64_t s2; - uint64_t s3; - uint64_t s4; - uint64_t s5; - uint64_t s6; - uint64_t s7; - uint64_t s8; - - uint64_t fp; - uint64_t sp; - uint64_t ra; -} jmp_buf[1]; - -extern int __asmcall __attribute__ (( returns_twice )) -setjmp ( jmp_buf env ); - -extern void __asmcall __attribute__ (( noreturn )) -longjmp ( jmp_buf env, int val ); - -#endif /* _SETJMP_H */ diff --git a/src/arch/riscv/Makefile b/src/arch/riscv/Makefile new file mode 100644 index 0000000..668d7db --- /dev/null +++ b/src/arch/riscv/Makefile @@ -0,0 +1,20 @@ +# Assembler section type character +# +ASM_TCHAR := @ +ASM_TCHAR_OPS := @ + +# Include RISCV-specific headers +# +INCDIRS := arch/$(ARCH)/include arch/riscv/include $(INCDIRS) + +# RISCV-specific directories containing source files +# +SRCDIRS += arch/riscv/core + +# RISCV-specific flags +# +CFLAGS += -mno-strict-align -mno-plt + +# EFI requires -fshort-wchar, and nothing else currently uses wchar_t +# +CFLAGS += -fshort-wchar diff --git a/src/arch/riscv/Makefile.efi b/src/arch/riscv/Makefile.efi new file mode 100644 index 0000000..957e8b8 --- /dev/null +++ b/src/arch/riscv/Makefile.efi @@ -0,0 +1,10 @@ +# -*- makefile -*- : Force emacs to use Makefile mode + +# RISCV-specific flags +# +CFLAGS += -mcmodel=medany + +# Include generic EFI Makefile +# +MAKEDEPS += Makefile.efi +include Makefile.efi diff --git a/src/arch/riscv/Makefile.linux b/src/arch/riscv/Makefile.linux new file mode 100644 index 0000000..4259044 --- /dev/null +++ b/src/arch/riscv/Makefile.linux @@ -0,0 +1,6 @@ +# -*- makefile -*- : Force emacs to use Makefile mode + +# Include generic Linux Makefile +# +MAKEDEPS += Makefile.linux +include Makefile.linux diff --git a/src/arch/riscv/core/riscv_bigint.c b/src/arch/riscv/core/riscv_bigint.c new file mode 100644 index 0000000..cbc5631 --- /dev/null +++ b/src/arch/riscv/core/riscv_bigint.c @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2024 Michael Brown <mbrown@fensystems.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * You can also choose to distribute this program under the terms of + * the Unmodified Binary Distribution Licence (as given in the file + * COPYING.UBDL), provided that you have satisfied its requirements. + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#include <stdint.h> +#include <string.h> +#include <ipxe/bigint.h> + +/** @file + * + * Big integer support + */ + +/** + * Multiply big integers + * + * @v multiplicand0 Element 0 of big integer to be multiplied + * @v multiplicand_size Number of elements in multiplicand + * @v multiplier0 Element 0 of big integer to be multiplied + * @v multiplier_size Number of elements in multiplier + * @v result0 Element 0 of big integer to hold result + */ +void bigint_multiply_raw ( const unsigned long *multiplicand0, + unsigned int multiplicand_size, + const unsigned long *multiplier0, + unsigned int multiplier_size, + unsigned long *result0 ) { + unsigned int result_size = ( multiplicand_size + multiplier_size ); + const bigint_t ( multiplicand_size ) __attribute__ (( may_alias )) + *multiplicand = ( ( const void * ) multiplicand0 ); + const bigint_t ( multiplier_size ) __attribute__ (( may_alias )) + *multiplier = ( ( const void * ) multiplier0 ); + bigint_t ( result_size ) __attribute__ (( may_alias )) + *result = ( ( void * ) result0 ); + unsigned int i; + unsigned int j; + unsigned long multiplicand_element; + unsigned long multiplier_element; + unsigned long *result_elements; + unsigned long discard_low; + unsigned long discard_high; + unsigned long discard_temp; + unsigned long discard_carry; + + /* Zero result */ + memset ( result, 0, sizeof ( *result ) ); + + /* Multiply integers one element at a time */ + for ( i = 0 ; i < multiplicand_size ; i++ ) { + multiplicand_element = multiplicand->element[i]; + for ( j = 0 ; j < multiplier_size ; j++ ) { + multiplier_element = multiplier->element[j]; + result_elements = &result->element[ i + j ]; + /* Perform a single multiply, and add the + * resulting double-element into the result, + * carrying as necessary. The carry can + * never overflow beyond the end of the + * result, since: + * + * a < 2^{n}, b < 2^{m} => ab < 2^{n+m} + */ + __asm__ __volatile__ ( /* Perform multiplication */ + "mulhu %2, %6, %7\n\t" + "mul %1, %6, %7\n\t" + /* Accumulate low half */ + LOADN " %3, (%0)\n\t" + "add %3, %3, %1\n\t" + "sltu %4, %3, %1\n\t" + STOREN " %3, 0(%0)\n\t" + /* Carry into high half */ + "add %4, %4, %2\n\t" + /* Propagate as necessary */ + "\n1:\n\t" + "addi %0, %0, %8\n\t" + LOADN " %3, 0(%0)\n\t" + "add %3, %3, %4\n\t" + "sltu %4, %3, %4\n\t" + STOREN " %3, 0(%0)\n\t" + "bnez %4, 1b\n\t" + : "+r" ( result_elements ), + "=r" ( discard_low ), + "=r" ( discard_high ), + "=r" ( discard_temp ), + "=r" ( discard_carry ), + "+m" ( *result ) + : "r" ( multiplicand_element ), + "r" ( multiplier_element ), + "i" ( sizeof ( *result0 ) ) ); + } + } +} diff --git a/src/arch/arm/interface/efi/efiarm_nap.c b/src/arch/riscv/core/riscv_io.c index fba7a5d..756b397 100644 --- a/src/arch/arm/interface/efi/efiarm_nap.c +++ b/src/arch/riscv/core/riscv_io.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Michael Brown <mbrown@fensystems.co.uk>. + * Copyright (C) 2024 Michael Brown <mbrown@fensystems.co.uk>. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -23,35 +23,24 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); -#include <ipxe/nap.h> -#include <ipxe/efi/efi.h> +#include <ipxe/io.h> +#include <ipxe/riscv_io.h> /** @file * - * iPXE CPU sleeping API for EFI + * iPXE I/O API for RISC-V * */ -/** - * Sleep until next interrupt - * - */ -static void efiarm_cpu_nap ( void ) { - /* - * I can't find any EFI API that allows us to put the CPU to - * sleep. The CpuSleep() function is defined in CpuLib.h, but - * isn't part of any exposed protocol so we have no way to - * call it. - * - * The EFI shell doesn't seem to bother sleeping the CPU; it - * just sits there idly burning power. - * - * If a shutdown is in progess, there may be nothing to - * generate an interrupt since the timer is disabled in the - * first step of ExitBootServices(). - */ - if ( ! efi_shutdown_in_progress ) - __asm__ __volatile__ ( "wfi" ); -} - -PROVIDE_NAP ( efiarm, cpu_nap, efiarm_cpu_nap ); +PROVIDE_IOAPI_INLINE ( riscv, phys_to_bus ); +PROVIDE_IOAPI_INLINE ( riscv, bus_to_phys ); +PROVIDE_IOAPI_INLINE ( riscv, readb ); +PROVIDE_IOAPI_INLINE ( riscv, readw ); +PROVIDE_IOAPI_INLINE ( riscv, readl ); +PROVIDE_IOAPI_INLINE ( riscv, writeb ); +PROVIDE_IOAPI_INLINE ( riscv, writew ); +PROVIDE_IOAPI_INLINE ( riscv, writel ); +PROVIDE_IOAPI_INLINE ( riscv, readq ); +PROVIDE_IOAPI_INLINE ( riscv, writeq ); +PROVIDE_IOAPI_INLINE ( riscv, mb ); +PROVIDE_DUMMY_PIO ( riscv ); diff --git a/src/arch/riscv/core/riscv_string.c b/src/arch/riscv/core/riscv_string.c new file mode 100644 index 0000000..3155c3c --- /dev/null +++ b/src/arch/riscv/core/riscv_string.c @@ -0,0 +1,272 @@ +/* + * Copyright (C) 2024 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * You can also choose to distribute this program under the terms of + * the Unmodified Binary Distribution Licence (as given in the file + * COPYING.UBDL), provided that you have satisfied its requirements. + */ + +/** @file + * + * Optimised string operations + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#include <string.h> + +/** + * Copy memory area + * + * @v dest Destination address + * @v src Source address + * @v len Length + * @ret dest Destination address + */ +void riscv_memcpy ( void *dest, const void *src, size_t len ) { + size_t len_pre; + size_t len_mid; + size_t len_post; + unsigned long discard_data; + + /* Calculate pre-aligned, aligned, and post-aligned lengths. + * (Align on the destination address, on the assumption that + * misaligned stores are likely to be more expensive than + * misaligned loads.) + */ + len_pre = ( ( sizeof ( unsigned long ) - ( ( intptr_t ) dest ) ) & + ( sizeof ( unsigned long ) - 1 ) ); + if ( len_pre > len ) + len_pre = len; + len -= len_pre; + len_mid = ( len & ~( sizeof ( unsigned long ) - 1 ) ); + len -= len_mid; + len_post = len; + + /* Copy pre-aligned section */ + __asm__ __volatile__ ( "j 2f\n\t" + "\n1:\n\t" + "lb %2, (%1)\n\t" + "sb %2, (%0)\n\t" + "addi %0, %0, 1\n\t" + "addi %1, %1, 1\n\t" + "\n2:\n\t" + "bne %0, %3, 1b\n\t" + : "+r" ( dest ), "+r" ( src ), + "=&r" ( discard_data ) + : "r" ( dest + len_pre ) + : "memory" ); + + /* Copy aligned section */ + __asm__ __volatile__ ( "j 2f\n\t" + "\n1:\n\t" + LOADN " %2, (%1)\n\t" + STOREN " %2, (%0)\n\t" + "addi %0, %0, %4\n\t" + "addi %1, %1, %4\n\t" + "\n2:\n\t" + "bne %0, %3, 1b\n\t" + : "+r" ( dest ), "+r" ( src ), + "=&r" ( discard_data ) + : "r" ( dest + len_mid ), + "i" ( sizeof ( unsigned long ) ) + : "memory" ); + + /* Copy post-aligned section */ + __asm__ __volatile__ ( "j 2f\n\t" + "\n1:\n\t" + "lb %2, (%1)\n\t" + "sb %2, (%0)\n\t" + "addi %0, %0, 1\n\t" + "addi %1, %1, 1\n\t" + "\n2:\n\t" + "bne %0, %3, 1b\n\t" + : "+r" ( dest ), "+r" ( src ), + "=&r" ( discard_data ) + : "r" ( dest + len_post ) + : "memory" ); +} + +/** + * Zero memory region + * + * @v dest Destination region + * @v len Length + */ +void riscv_bzero ( void *dest, size_t len ) { + size_t len_pre; + size_t len_mid; + size_t len_post; + + /* Calculate pre-aligned, aligned, and post-aligned lengths */ + len_pre = ( ( sizeof ( unsigned long ) - ( ( intptr_t ) dest ) ) & + ( sizeof ( unsigned long ) - 1 ) ); + if ( len_pre > len ) + len_pre = len; + len -= len_pre; + len_mid = ( len & ~( sizeof ( unsigned long ) - 1 ) ); + len -= len_mid; + len_post = len; + + /* Zero pre-aligned section */ + __asm__ __volatile__ ( "j 2f\n\t" + "\n1:\n\t" + "sb zero, (%0)\n\t" + "addi %0, %0, 1\n\t" + "\n2:\n\t" + "bne %0, %1, 1b\n\t" + : "+r" ( dest ) + : "r" ( dest + len_pre ) + : "memory" ); + + /* Zero aligned section */ + __asm__ __volatile__ ( "j 2f\n\t" + "\n1:\n\t" + STOREN " zero, (%0)\n\t" + "addi %0, %0, %2\n\t" + "\n2:\n\t" + "bne %0, %1, 1b\n\t" + : "+r" ( dest ) + : "r" ( dest + len_mid ), + "i" ( sizeof ( unsigned long ) ) + : "memory" ); + + /* Zero post-aligned section */ + __asm__ __volatile__ ( "j 2f\n\t" + "\n1:\n\t" + "sb zero, (%0)\n\t" + "addi %0, %0, 1\n\t" + "\n2:\n\t" + "bne %0, %1, 1b\n\t" + : "+r" ( dest ) + : "r" ( dest + len_post ) + : "memory" ); +} + +/** + * Fill memory region + * + * @v dest Destination region + * @v len Length + * @v character Fill character + * + * The unusual parameter order is to allow for more efficient + * tail-calling to riscv_bzero() when zeroing a region. + */ +void riscv_memset ( void *dest, size_t len, int character ) { + + /* Do nothing if length is zero */ + if ( ! len ) + return; + + /* Use optimised zeroing code if applicable */ + if ( character == 0 ) { + riscv_bzero ( dest, len ); + return; + } + + /* Fill one byte at a time. Calling memset() with a non-zero + * value is relatively rare and unlikely to be + * performance-critical. + */ + __asm__ __volatile__ ( "\n1:\n\t" + "sb %2, (%0)\n\t" + "addi %0, %0, 1\n\t" + "bne %0, %1, 1b\n\t" + : "+r" ( dest ) + : "r" ( dest + len ), "r" ( character ) + : "memory" ); +} + +/** + * Copy (possibly overlapping) memory region forwards + * + * @v dest Destination region + * @v src Source region + * @v len Length + */ +void riscv_memmove_forwards ( void *dest, const void *src, size_t len ) { + unsigned long discard_data; + + /* Do nothing if length is zero */ + if ( ! len ) + return; + + /* Assume memmove() is not performance-critical, and perform a + * bytewise copy for simplicity. + */ + __asm__ __volatile__ ( "\n1:\n\t" + "lb %2, (%1)\n\t" + "sb %2, (%0)\n\t" + "addi %1, %1, 1\n\t" + "addi %0, %0, 1\n\t" + "bne %0, %3, 1b\n\t" + : "+r" ( dest ), "+r" ( src ), + "=&r" ( discard_data ) + : "r" ( dest + len ) + : "memory" ); +} + +/** + * Copy (possibly overlapping) memory region backwards + * + * @v dest Destination region + * @v src Source region + * @v len Length + */ +void riscv_memmove_backwards ( void *dest, const void *src, size_t len ) { + void *orig_dest = dest; + unsigned long discard_data; + + /* Do nothing if length is zero */ + if ( ! len ) + return; + + /* Assume memmove() is not performance-critical, and perform a + * bytewise copy for simplicity. + */ + dest += len; + src += len; + __asm__ __volatile__ ( "\n1:\n\t" + "addi %1, %1, -1\n\t" + "addi %0, %0, -1\n\t" + "lb %2, (%1)\n\t" + "sb %2, (%0)\n\t" + "bne %0, %3, 1b\n\t" + : "+r" ( dest ), "+r" ( src ), + "=&r" ( discard_data ) + : "r" ( orig_dest ) + : "memory" ); +} + +/** + * Copy (possibly overlapping) memory region + * + * @v dest Destination region + * @v src Source region + * @v len Length + */ +void riscv_memmove ( void *dest, const void *src, size_t len ) { + + if ( dest <= src ) { + riscv_memmove_forwards ( dest, src, len ); + } else { + riscv_memmove_backwards ( dest, src, len ); + } +} diff --git a/src/arch/x86/interface/efi/efix86_nap.c b/src/arch/riscv/core/riscv_strings.S index 296876b..eb1b397 100644 --- a/src/arch/x86/interface/efi/efix86_nap.c +++ b/src/arch/riscv/core/riscv_strings.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>. + * Copyright (C) 2024 Michael Brown <mbrown@fensystems.co.uk>. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -21,37 +21,50 @@ * COPYING.UBDL), provided that you have satisfied its requirements. */ -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#include <ipxe/nap.h> -#include <ipxe/efi/efi.h> + FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ) /** @file * - * iPXE CPU sleeping API for EFI + * Byte swapping * */ + .section ".note.GNU-stack", "", @progbits + .text + /** - * Sleep until next interrupt + * Find first (i.e. least significant) set bit * + * @v value Value + * @ret lsb Least significant bit set in value (LSB=1), or zero */ -static void efix86_cpu_nap ( void ) { - /* - * I can't find any EFI API that allows us to put the CPU to - * sleep. The CpuSleep() function is defined in CpuLib.h, but - * isn't part of any exposed protocol so we have no way to - * call it. - * - * The EFI shell doesn't seem to bother sleeping the CPU; it - * just sits there idly burning power. - * - * If a shutdown is in progess, there may be nothing to - * generate an interrupt since the timer is disabled in the - * first step of ExitBootServices(). - */ - if ( ! efi_shutdown_in_progress ) - __asm__ __volatile__ ( "hlt" ); -} + .section ".text.riscv_ffs" + .globl riscv_ffs +riscv_ffs: + beqz a0, 2f + mv t0, a0 + li a0, ( __riscv_xlen + 1 ) +1: slli t0, t0, 1 + addi a0, a0, -1 + bnez t0, 1b +2: ret + .size riscv_ffs, . - riscv_ffs -PROVIDE_NAP ( efix86, cpu_nap, efix86_cpu_nap ); +/** + * Find last (i.e. most significant) set bit + * + * @v value Value + * @ret msb Most significant bit set in value (LSB=1), or zero + */ + .section ".text.riscv_fls" + .globl riscv_fls +riscv_fls: + beqz a0, 2f + mv t0, a0 + li a0, __riscv_xlen + bltz t0, 2f +1: slli t0, t0, 1 + addi a0, a0, -1 + bgez t0, 1b +2: ret + .size riscv_fls, . - riscv_fls diff --git a/src/arch/riscv/core/setjmp.S b/src/arch/riscv/core/setjmp.S new file mode 100644 index 0000000..69d844a --- /dev/null +++ b/src/arch/riscv/core/setjmp.S @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2024 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * You can also choose to distribute this program under the terms of + * the Unmodified Binary Distribution Licence (as given in the file + * COPYING.UBDL), provided that you have satisfied its requirements. + */ + + FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ) + +/** @file + * + * Long jumps + * + */ + + .section ".note.GNU-stack", "", @progbits + .text + + /* Must match jmp_buf structure layout */ + .struct 0 +env_ra: .space ( __riscv_xlen / 8 ) +env_sp: .space ( __riscv_xlen / 8 ) +env_s0: .space ( __riscv_xlen / 8 ) +env_s1: .space ( __riscv_xlen / 8 ) +env_s2: .space ( __riscv_xlen / 8 ) +env_s3: .space ( __riscv_xlen / 8 ) +env_s4: .space ( __riscv_xlen / 8 ) +env_s5: .space ( __riscv_xlen / 8 ) +env_s6: .space ( __riscv_xlen / 8 ) +env_s7: .space ( __riscv_xlen / 8 ) +env_s8: .space ( __riscv_xlen / 8 ) +env_s9: .space ( __riscv_xlen / 8 ) +env_s10: .space ( __riscv_xlen / 8 ) +env_s11: .space ( __riscv_xlen / 8 ) + .previous + +/* + * Save stack context for non-local goto + */ + .section ".text.setjmp", "ax", @progbits + .globl setjmp +setjmp: + /* Save registers */ + STOREN ra, env_ra(a0) + STOREN sp, env_sp(a0) + STOREN s0, env_s0(a0) + STOREN s1, env_s1(a0) + STOREN s2, env_s2(a0) + STOREN s3, env_s3(a0) + STOREN s4, env_s4(a0) + STOREN s5, env_s5(a0) + STOREN s6, env_s6(a0) + STOREN s7, env_s7(a0) + STOREN s8, env_s8(a0) + STOREN s9, env_s9(a0) + STOREN s10, env_s10(a0) + STOREN s11, env_s11(a0) + /* Return zero when returning as setjmp() */ + mv a0, zero + ret + .size setjmp, . - setjmp + +/* + * Non-local jump to a saved stack context + */ + .section ".text.longjmp", "ax", @progbits + .globl longjmp +longjmp: + /* Restore registers */ + LOADN s11, env_s11(a0) + LOADN s10, env_s10(a0) + LOADN s9, env_s9(a0) + LOADN s8, env_s8(a0) + LOADN s7, env_s7(a0) + LOADN s6, env_s6(a0) + LOADN s5, env_s5(a0) + LOADN s4, env_s4(a0) + LOADN s3, env_s3(a0) + LOADN s2, env_s2(a0) + LOADN s1, env_s1(a0) + LOADN s0, env_s0(a0) + LOADN sp, env_sp(a0) + LOADN ra, env_ra(a0) + /* Force result to non-zero */ + seqz a0, a1 + or a0, a0, a1 + /* Return to setjmp() caller */ + ret + .size longjmp, . - longjmp diff --git a/src/arch/riscv/include/bits/bigint.h b/src/arch/riscv/include/bits/bigint.h new file mode 100644 index 0000000..fcc0d51 --- /dev/null +++ b/src/arch/riscv/include/bits/bigint.h @@ -0,0 +1,362 @@ +#ifndef _BITS_BIGINT_H +#define _BITS_BIGINT_H + +/** @file + * + * Big integer support + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#include <stdint.h> +#include <string.h> +#include <strings.h> + +/** Element of a big integer */ +typedef unsigned long bigint_element_t; + +/** + * Initialise big integer + * + * @v value0 Element 0 of big integer to initialise + * @v size Number of elements + * @v data Raw data + * @v len Length of raw data + */ +static inline __attribute__ (( always_inline )) void +bigint_init_raw ( unsigned long *value0, unsigned int size, + const void *data, size_t len ) { + size_t pad_len = ( sizeof ( bigint_t ( size ) ) - len ); + uint8_t *value_byte = ( ( void * ) value0 ); + const uint8_t *data_byte = ( data + len ); + + /* Copy raw data in reverse order, padding with zeros */ + while ( len-- ) + *(value_byte++) = *(--data_byte); + while ( pad_len-- ) + *(value_byte++) = 0; +} + +/** + * Add big integers + * + * @v addend0 Element 0 of big integer to add + * @v value0 Element 0 of big integer to be added to + * @v size Number of elements + */ +static inline __attribute__ (( always_inline )) void +bigint_add_raw ( const unsigned long *addend0, unsigned long *value0, + unsigned int size ) { + bigint_t ( size ) __attribute__ (( may_alias )) *value = + ( ( void * ) value0 ); + unsigned long *valueN = ( value0 + size ); + unsigned long *discard_addend; + unsigned long *discard_value; + unsigned long discard_addend_i; + unsigned long discard_value_i; + unsigned long discard_carry; + unsigned long discard_temp; + + __asm__ __volatile__ ( "\n1:\n\t" + /* Load addend[i] and value[i] */ + LOADN " %2, (%0)\n\t" + LOADN " %3, (%1)\n\t" + /* Add carry flag and addend */ + "add %3, %3, %4\n\t" + "sltu %5, %3, %4\n\t" + "add %3, %3, %2\n\t" + "sltu %4, %3, %2\n\t" + "or %4, %4, %5\n\t" + /* Store value[i] */ + STOREN " %3, (%1)\n\t" + /* Loop */ + "addi %0, %0, %8\n\t" + "addi %1, %1, %8\n\t" + "bne %1, %7, 1b\n\t" + : "=&r" ( discard_addend ), + "=&r" ( discard_value ), + "=&r" ( discard_addend_i ), + "=&r" ( discard_value_i ), + "=&r" ( discard_carry ), + "=&r" ( discard_temp ), + "+m" ( *value ) + : "r" ( valueN ), + "i" ( sizeof ( unsigned long ) ), + "0" ( addend0 ), "1" ( value0 ), "4" ( 0 ) ); +} + +/** + * Subtract big integers + * + * @v subtrahend0 Element 0 of big integer to subtract + * @v value0 Element 0 of big integer to be subtracted from + * @v size Number of elements + */ +static inline __attribute__ (( always_inline )) void +bigint_subtract_raw ( const unsigned long *subtrahend0, unsigned long *value0, + unsigned int size ) { + bigint_t ( size ) __attribute__ (( may_alias )) *value = + ( ( void * ) value0 ); + unsigned long *valueN = ( value0 + size ); + unsigned long *discard_subtrahend; + unsigned long *discard_value; + unsigned long discard_subtrahend_i; + unsigned long discard_value_i; + unsigned long discard_carry; + unsigned long discard_temp; + + __asm__ __volatile__ ( "\n1:\n\t" + /* Load subtrahend[i] and value[i] */ + LOADN " %2, (%0)\n\t" + LOADN " %3, (%1)\n\t" + /* Subtract carry flag and subtrahend */ + "sltu %5, %3, %4\n\t" + "sub %3, %3, %4\n\t" + "sltu %4, %3, %2\n\t" + "sub %3, %3, %2\n\t" + "or %4, %4, %5\n\t" + /* Store value[i] */ + STOREN " %3, (%1)\n\t" + /* Loop */ + "addi %0, %0, %8\n\t" + "addi %1, %1, %8\n\t" + "bne %1, %7, 1b\n\t" + : "=&r" ( discard_subtrahend ), + "=&r" ( discard_value ), + "=&r" ( discard_subtrahend_i ), + "=&r" ( discard_value_i ), + "=&r" ( discard_carry ), + "=&r" ( discard_temp ), + "+m" ( *value ) + : "r" ( valueN ), + "i" ( sizeof ( unsigned long ) ), + "0" ( subtrahend0 ), "1" ( value0 ), + "4" ( 0 ) ); +} + +/** + * Rotate big integer left + * + * @v value0 Element 0 of big integer + * @v size Number of elements + */ +static inline __attribute__ (( always_inline )) void +bigint_rol_raw ( unsigned long *value0, unsigned int size ) { + bigint_t ( size ) __attribute__ (( may_alias )) *value = + ( ( void * ) value0 ); + unsigned long *valueN = ( value0 + size ); + unsigned long *discard_value; + unsigned long discard_value_i; + unsigned long discard_carry; + unsigned long discard_temp; + + __asm__ __volatile__ ( "\n1:\n\t" + /* Load value[i] */ + LOADN " %1, (%0)\n\t" + /* Shift left */ + "slli %3, %1, 1\n\t" + "or %3, %3, %2\n\t" + "srli %2, %1, %7\n\t" + /* Store value[i] */ + STOREN " %3, (%0)\n\t" + /* Loop */ + "addi %0, %0, %6\n\t" + "bne %0, %5, 1b\n\t" + : "=&r" ( discard_value ), + "=&r" ( discard_value_i ), + "=&r" ( discard_carry ), + "=&r" ( discard_temp ), + "+m" ( *value ) + : "r" ( valueN ), + "i" ( sizeof ( unsigned long ) ), + "i" ( ( 8 * sizeof ( unsigned long ) - 1 ) ), + "0" ( value0 ), "2" ( 0 ) ); +} + +/** + * Rotate big integer right + * + * @v value0 Element 0 of big integer + * @v size Number of elements + */ +static inline __attribute__ (( always_inline )) void +bigint_ror_raw ( unsigned long *value0, unsigned int size ) { + bigint_t ( size ) __attribute__ (( may_alias )) *value = + ( ( void * ) value0 ); + unsigned long *valueN = ( value0 + size ); + unsigned long *discard_value; + unsigned long discard_value_i; + unsigned long discard_carry; + unsigned long discard_temp; + + __asm__ __volatile__ ( "\n1:\n\t" + /* Load value[i] */ + LOADN " %1, %6(%0)\n\t" + /* Shift right */ + "srli %3, %1, 1\n\t" + "or %3, %3, %2\n\t" + "slli %2, %1, %7\n\t" + /* Store value[i] */ + STOREN " %3, %6(%0)\n\t" + /* Loop */ + "addi %0, %0, %6\n\t" + "bne %0, %5, 1b\n\t" + : "=&r" ( discard_value ), + "=&r" ( discard_value_i ), + "=&r" ( discard_carry ), + "=&r" ( discard_temp ), + "+m" ( *value ) + : "r" ( value0 ), + "i" ( -( sizeof ( unsigned long ) ) ), + "i" ( ( 8 * sizeof ( unsigned long ) - 1 ) ), + "0" ( valueN ), "2" ( 0 ) ); +} + +/** + * Test if big integer is equal to zero + * + * @v value0 Element 0 of big integer + * @v size Number of elements + * @ret is_zero Big integer is equal to zero + */ +static inline __attribute__ (( always_inline, pure )) int +bigint_is_zero_raw ( const unsigned long *value0, unsigned int size ) { + const unsigned long *value = value0; + unsigned long value_i; + + do { + value_i = *(value++); + if ( value_i ) + break; + } while ( --size ); + + return ( value_i == 0 ); +} + +/** + * Compare big integers + * + * @v value0 Element 0 of big integer + * @v reference0 Element 0 of reference big integer + * @v size Number of elements + * @ret geq Big integer is greater than or equal to the reference + */ +static inline __attribute__ (( always_inline, pure )) int +bigint_is_geq_raw ( const unsigned long *value0, + const unsigned long *reference0, unsigned int size ) { + const unsigned long *value = ( value0 + size ); + const unsigned long *reference = ( reference0 + size ); + unsigned long value_i; + unsigned long reference_i; + + do { + value_i = *(--value); + reference_i = *(--reference); + if ( value_i != reference_i ) + break; + } while ( --size ); + + return ( value_i >= reference_i ); +} + +/** + * Test if bit is set in big integer + * + * @v value0 Element 0 of big integer + * @v size Number of elements + * @v bit Bit to test + * @ret is_set Bit is set + */ +static inline __attribute__ (( always_inline )) int +bigint_bit_is_set_raw ( const unsigned long *value0, unsigned int size, + unsigned int bit ) { + const bigint_t ( size ) __attribute__ (( may_alias )) *value = + ( ( const void * ) value0 ); + unsigned int index = ( bit / ( 8 * sizeof ( *value0 ) ) ); + unsigned int subindex = ( bit % ( 8 * sizeof ( *value0 ) ) ); + + return ( !! ( value->element[index] & ( 1UL << subindex ) ) ); +} + +/** + * Find highest bit set in big integer + * + * @v value0 Element 0 of big integer + * @v size Number of elements + * @ret max_bit Highest bit set + 1 (or 0 if no bits set) + */ +static inline __attribute__ (( always_inline )) int +bigint_max_set_bit_raw ( const unsigned long *value0, unsigned int size ) { + const unsigned long *value = ( value0 + size ); + int max_bit = ( 8 * sizeof ( bigint_t ( size ) ) ); + unsigned long value_i; + + do { + value_i = *(--value); + max_bit -= ( ( 8 * sizeof ( *value0 ) ) - fls ( value_i ) ); + if ( value_i ) + break; + } while ( --size ); + + return max_bit; +} + +/** + * Grow big integer + * + * @v source0 Element 0 of source big integer + * @v source_size Number of elements in source big integer + * @v dest0 Element 0 of destination big integer + * @v dest_size Number of elements in destination big integer + */ +static inline __attribute__ (( always_inline )) void +bigint_grow_raw ( const unsigned long *source0, unsigned int source_size, + unsigned long *dest0, unsigned int dest_size ) { + unsigned int pad_size = ( dest_size - source_size ); + + memcpy ( dest0, source0, sizeof ( bigint_t ( source_size ) ) ); + memset ( ( dest0 + source_size ), 0, sizeof ( bigint_t ( pad_size ) ) ); +} + +/** + * Shrink big integer + * + * @v source0 Element 0 of source big integer + * @v source_size Number of elements in source big integer + * @v dest0 Element 0 of destination big integer + * @v dest_size Number of elements in destination big integer + */ +static inline __attribute__ (( always_inline )) void +bigint_shrink_raw ( const unsigned long *source0, + unsigned int source_size __unused, + unsigned long *dest0, unsigned int dest_size ) { + + memcpy ( dest0, source0, sizeof ( bigint_t ( dest_size ) ) ); +} + +/** + * Finalise big integer + * + * @v value0 Element 0 of big integer to finalise + * @v size Number of elements + * @v out Output buffer + * @v len Length of output buffer + */ +static inline __attribute__ (( always_inline )) void +bigint_done_raw ( const unsigned long *value0, unsigned int size __unused, + void *out, size_t len ) { + const uint8_t *value_byte = ( ( const void * ) value0 ); + uint8_t *out_byte = ( out + len ); + + /* Copy raw data in reverse order */ + while ( len-- ) + *(--out_byte) = *(value_byte++); +} + +extern void bigint_multiply_raw ( const unsigned long *multiplicand0, + unsigned int multiplicand_size, + const unsigned long *multiplier0, + unsigned int multiplier_size, + unsigned long *value0 ); + +#endif /* _BITS_BIGINT_H */ diff --git a/src/arch/riscv/include/bits/bitops.h b/src/arch/riscv/include/bits/bitops.h new file mode 100644 index 0000000..2019db9 --- /dev/null +++ b/src/arch/riscv/include/bits/bitops.h @@ -0,0 +1,82 @@ +#ifndef _BITS_BITOPS_H +#define _BITS_BITOPS_H + +/** @file + * + * RISC-V bit operations + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#include <stdint.h> + +/** + * Test and set bit atomically + * + * @v bit Bit to set + * @v bits Bit field + * @ret old Old value of bit (zero or non-zero) + */ +static inline __attribute__ (( always_inline )) int +test_and_set_bit ( unsigned int bit, volatile void *bits ) { + unsigned int index = ( bit / 32 ); + unsigned int offset = ( bit % 32 ); + volatile uint32_t *word = ( ( ( volatile uint32_t * ) bits ) + index ); + uint32_t mask = ( 1U << offset ); + uint32_t old; + + __asm__ __volatile__ ( "amoor.w %0, %2, %1" + : "=r" ( old ), "+A" ( *word ) + : "r" ( mask ) ); + + return ( !! ( old & mask ) ); +} + +/** + * Test and clear bit atomically + * + * @v bit Bit to set + * @v bits Bit field + * @ret old Old value of bit (zero or non-zero) + */ +static inline __attribute__ (( always_inline )) int +test_and_clear_bit ( unsigned int bit, volatile void *bits ) { + unsigned int index = ( bit / 32 ); + unsigned int offset = ( bit % 32 ); + volatile uint32_t *word = ( ( ( volatile uint32_t * ) bits ) + index ); + uint32_t mask = ( 1U << offset ); + uint32_t old; + + __asm__ __volatile__ ( "amoand.w %0, %2, %1" + : "=r" ( old ), "+A" ( *word ) + : "r" ( ~mask ) ); + + return ( !! ( old & mask ) ); +} + +/** + * Set bit atomically + * + * @v bit Bit to set + * @v bits Bit field + */ +static inline __attribute__ (( always_inline )) void +set_bit ( unsigned int bit, volatile void *bits ) { + + test_and_set_bit ( bit, bits ); +} + +/** + * Clear bit atomically + * + * @v bit Bit to set + * @v bits Bit field + */ +static inline __attribute__ (( always_inline )) void +clear_bit ( unsigned int bit, volatile void *bits ) { + + test_and_clear_bit ( bit, bits ); +} + +#endif /* _BITS_BITOPS_H */ diff --git a/src/arch/riscv/include/bits/byteswap.h b/src/arch/riscv/include/bits/byteswap.h new file mode 100644 index 0000000..56d03f6 --- /dev/null +++ b/src/arch/riscv/include/bits/byteswap.h @@ -0,0 +1,48 @@ +#ifndef _BITS_BYTESWAP_H +#define _BITS_BYTESWAP_H + +/** @file + * + * Byte-order swapping functions + * + */ + +#include <stdint.h> + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +extern __asmcall uint64_t riscv_swap_word ( uint64_t x ); +extern __asmcall unsigned long riscv_swap_half ( unsigned long x ); +extern __asmcall unsigned long riscv_swap_byte ( unsigned long x ); + +static inline __attribute__ (( always_inline, const )) uint16_t +__bswap_variable_16 ( uint16_t x ) { + return riscv_swap_byte ( x ); +} + +static inline __attribute__ (( always_inline )) void +__bswap_16s ( uint16_t *x ) { + *x = riscv_swap_byte ( *x ); +} + +static inline __attribute__ (( always_inline, const )) uint32_t +__bswap_variable_32 ( uint32_t x ) { + return riscv_swap_half ( x ); +} + +static inline __attribute__ (( always_inline )) void +__bswap_32s ( uint32_t *x ) { + *x = riscv_swap_half ( *x ); +} + +static inline __attribute__ (( always_inline, const )) uint64_t +__bswap_variable_64 ( uint64_t x ) { + return riscv_swap_word ( x ); +} + +static inline __attribute__ (( always_inline )) void +__bswap_64s ( uint64_t *x ) { + *x = riscv_swap_word ( *x ); +} + +#endif /* _BITS_BYTESWAP_H */ diff --git a/src/arch/riscv/include/bits/compiler.h b/src/arch/riscv/include/bits/compiler.h new file mode 100644 index 0000000..624a161 --- /dev/null +++ b/src/arch/riscv/include/bits/compiler.h @@ -0,0 +1,40 @@ +#ifndef _BITS_COMPILER_H +#define _BITS_COMPILER_H + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +/** Dummy relocation type */ +#define RELOC_TYPE_NONE R_RISCV_NONE + +/* Determine load/store instructions for natural bit width */ +#if __riscv_xlen == 128 +#define NATURAL_SUFFIX q +#elif __riscv_xlen == 64 +#define NATURAL_SUFFIX d +#elif __riscv_xlen == 32 +#define NATURAL_SUFFIX w +#else +#error "Unsupported bit width" +#endif +#ifdef ASSEMBLY +#define LOADN _C2 ( L, NATURAL_SUFFIX ) +#define STOREN _C2 ( S, NATURAL_SUFFIX ) +#else +#define LOADN "L" _S2 ( NATURAL_SUFFIX ) +#define STOREN "S" _S2 ( NATURAL_SUFFIX ) +#endif + +#ifndef ASSEMBLY + +/** Unprefixed constant operand modifier */ +#define ASM_NO_PREFIX "" + +/** Declare a function with standard calling conventions */ +#define __asmcall + +/** Declare a function with libgcc implicit linkage */ +#define __libgcc + +#endif /* ASSEMBLY */ + +#endif /* _BITS_COMPILER_H */ diff --git a/src/arch/riscv/include/bits/endian.h b/src/arch/riscv/include/bits/endian.h new file mode 100644 index 0000000..85718cf --- /dev/null +++ b/src/arch/riscv/include/bits/endian.h @@ -0,0 +1,8 @@ +#ifndef _BITS_ENDIAN_H +#define _BITS_ENDIAN_H + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#define __BYTE_ORDER __LITTLE_ENDIAN + +#endif /* _BITS_ENDIAN_H */ diff --git a/src/arch/riscv/include/bits/errfile.h b/src/arch/riscv/include/bits/errfile.h new file mode 100644 index 0000000..2b12021 --- /dev/null +++ b/src/arch/riscv/include/bits/errfile.h @@ -0,0 +1,19 @@ +#ifndef _BITS_ERRFILE_H +#define _BITS_ERRFILE_H + +/** @file + * + * RISC-V error file identifiers + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +/** + * @addtogroup errfile Error file identifiers + * @{ + */ + +/** @} */ + +#endif /* _BITS_ERRFILE_H */ diff --git a/src/arch/riscv/include/bits/io.h b/src/arch/riscv/include/bits/io.h new file mode 100644 index 0000000..4296e31 --- /dev/null +++ b/src/arch/riscv/include/bits/io.h @@ -0,0 +1,17 @@ +#ifndef _BITS_IO_H +#define _BITS_IO_H + +/** @file + * + * RISCV-specific I/O API implementations + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +/** Page shift */ +#define PAGE_SHIFT 12 + +#include <ipxe/riscv_io.h> + +#endif /* _BITS_IO_H */ diff --git a/src/arch/riscv/include/bits/nap.h b/src/arch/riscv/include/bits/nap.h new file mode 100644 index 0000000..331399f --- /dev/null +++ b/src/arch/riscv/include/bits/nap.h @@ -0,0 +1,20 @@ +#ifndef _BITS_NAP_H +#define _BITS_NAP_H + +/** @file + * + * RISCV-specific CPU sleeping API implementations + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +/** + * Sleep until next CPU interrupt + * + */ +static inline __attribute__ (( always_inline )) void cpu_halt ( void ) { + __asm__ __volatile__ ( "wfi" ); +} + +#endif /* _BITS_NAP_H */ diff --git a/src/arch/riscv/include/bits/setjmp.h b/src/arch/riscv/include/bits/setjmp.h new file mode 100644 index 0000000..5186fad --- /dev/null +++ b/src/arch/riscv/include/bits/setjmp.h @@ -0,0 +1,16 @@ +#ifndef _BITS_SETJMP_H +#define _BITS_SETJMP_H + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +/** A jump buffer */ +typedef struct { + /** Return address (ra) */ + unsigned long ra; + /** Stack pointer (sp) */ + unsigned long sp; + /** Callee-saved registers (s0-s11) */ + unsigned long s[12]; +} jmp_buf[1]; + +#endif /* _BITS_SETJMP_H */ diff --git a/src/arch/riscv/include/bits/stdint.h b/src/arch/riscv/include/bits/stdint.h new file mode 100644 index 0000000..fe1f994 --- /dev/null +++ b/src/arch/riscv/include/bits/stdint.h @@ -0,0 +1,23 @@ +#ifndef _BITS_STDINT_H +#define _BITS_STDINT_H + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +typedef __SIZE_TYPE__ size_t; +typedef signed long ssize_t; +typedef signed long off_t; + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; + +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +typedef signed long long int64_t; + +typedef unsigned long physaddr_t; +typedef unsigned long intptr_t; + +#endif /* _BITS_STDINT_H */ diff --git a/src/arch/riscv/include/bits/string.h b/src/arch/riscv/include/bits/string.h new file mode 100644 index 0000000..3f78b35 --- /dev/null +++ b/src/arch/riscv/include/bits/string.h @@ -0,0 +1,89 @@ +#ifndef _BITS_STRING_H +#define _BITS_STRING_H + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +/** @file + * + * String functions + * + */ + +extern void riscv_bzero ( void *dest, size_t len ); +extern void riscv_memset ( void *dest, size_t len, int character ); +extern void riscv_memcpy ( void *dest, const void *src, size_t len ); +extern void riscv_memmove_forwards ( void *dest, const void *src, size_t len ); +extern void riscv_memmove_backwards ( void *dest, const void *src, size_t len ); +extern void riscv_memmove ( void *dest, const void *src, size_t len ); + +/** + * Fill memory region + * + * @v dest Destination region + * @v character Fill character + * @v len Length + * @ret dest Destination region + */ +static inline __attribute__ (( always_inline )) void * +memset ( void *dest, int character, size_t len ) { + + /* For zeroing larger or non-constant lengths, use the + * optimised variable-length zeroing code. + */ + if ( __builtin_constant_p ( character ) && ( character == 0 ) ) { + riscv_bzero ( dest, len ); + return dest; + } + + /* Not necessarily zeroing: use basic variable-length code */ + riscv_memset ( dest, len, character ); + return dest; +} + +/** + * Copy memory region + * + * @v dest Destination region + * @v src Source region + * @v len Length + * @ret dest Destination region + */ +static inline __attribute__ (( always_inline )) void * +memcpy ( void *dest, const void *src, size_t len ) { + + /* Otherwise, use variable-length code */ + riscv_memcpy ( dest, src, len ); + return dest; +} + +/** + * Copy (possibly overlapping) memory region + * + * @v dest Destination region + * @v src Source region + * @v len Length + * @ret dest Destination region + */ +static inline __attribute__ (( always_inline )) void * +memmove ( void *dest, const void *src, size_t len ) { + ssize_t offset = ( dest - src ); + + /* If required direction of copy is known at build time, then + * use the appropriate forwards/backwards copy directly. + */ + if ( __builtin_constant_p ( offset ) ) { + if ( offset <= 0 ) { + riscv_memmove_forwards ( dest, src, len ); + return dest; + } else { + riscv_memmove_backwards ( dest, src, len ); + return dest; + } + } + + /* Otherwise, use ambidirectional copy */ + riscv_memmove ( dest, src, len ); + return dest; +} + +#endif /* _BITS_STRING_H */ diff --git a/src/arch/riscv/include/bits/strings.h b/src/arch/riscv/include/bits/strings.h new file mode 100644 index 0000000..dd6d458 --- /dev/null +++ b/src/arch/riscv/include/bits/strings.h @@ -0,0 +1,91 @@ +#ifndef _BITS_STRINGS_H +#define _BITS_STRINGS_H + +/** @file + * + * String functions + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +extern __asmcall unsigned long riscv_ffs ( unsigned long value ); +extern __asmcall unsigned long riscv_fls ( unsigned long value ); + +/** + * Find first (i.e. least significant) set bit + * + * @v value Value + * @ret lsb Least significant bit set in value (LSB=1), or zero + */ +static inline __attribute__ (( always_inline )) int __ffsl ( long value ) { + + return riscv_ffs ( value ); +} + +/** + * Find first (i.e. least significant) set bit + * + * @v value Value + * @ret lsb Least significant bit set in value (LSB=1), or zero + */ +static inline __attribute__ (( always_inline )) int __ffsll ( long long value ){ + unsigned long low = value; + unsigned long high; + + /* Check machine word size */ + if ( sizeof ( value ) > sizeof ( low ) ) { + /* 32-bit */ + high = ( value >> 32 ); + if ( low ) { + return ( __ffsl ( low ) ); + } else if ( high ) { + return ( 32 + __ffsl ( high ) ); + } else { + return 0; + } + } else { + /* 64-bit */ + return ( __ffsl ( low ) ); + } +} + +/** + * Find last (i.e. most significant) set bit + * + * @v value Value + * @ret msb Most significant bit set in value (LSB=1), or zero + */ +static inline __attribute__ (( always_inline )) int __flsl ( long value ) { + + return riscv_fls ( value ); +} + +/** + * Find last (i.e. most significant) set bit + * + * @v value Value + * @ret msb Most significant bit set in value (LSB=1), or zero + */ +static inline __attribute__ (( always_inline )) int __flsll ( long long value ){ + unsigned long low = value; + unsigned long high; + + /* Check machine word size */ + if ( sizeof ( value ) > sizeof ( low ) ) { + /* 32-bit */ + high = ( value >> 32 ); + if ( high ) { + return ( 32 + __flsl ( high ) ); + } else if ( low ) { + return ( __flsl ( low ) ); + } else { + return 0; + } + } else { + /* 64-bit */ + return ( __flsl ( low ) ); + } +} + +#endif /* _BITS_STRINGS_H */ diff --git a/src/arch/riscv/include/ipxe/riscv_io.h b/src/arch/riscv/include/ipxe/riscv_io.h new file mode 100644 index 0000000..8f90304 --- /dev/null +++ b/src/arch/riscv/include/ipxe/riscv_io.h @@ -0,0 +1,137 @@ +#ifndef _IPXE_RISCV_IO_H +#define _IPXE_RISCV_IO_H + +/** @file + * + * iPXE I/O API for RISC-V + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#ifdef IOAPI_RISCV +#define IOAPI_PREFIX_riscv +#else +#define IOAPI_PREFIX_riscv __riscv_ +#endif + +#include <ipxe/dummy_pio.h> + +/* + * Memory space mappings + * + */ + +/* + * Physical<->Bus address mappings + * + */ + +static inline __always_inline unsigned long +IOAPI_INLINE ( riscv, phys_to_bus ) ( unsigned long phys_addr ) { + return phys_addr; +} + +static inline __always_inline unsigned long +IOAPI_INLINE ( riscv, bus_to_phys ) ( unsigned long bus_addr ) { + return bus_addr; +} + +/* + * MMIO reads and writes + * + */ + +/* Single-register read */ +#define RISCV_READX( _suffix, _type, _insn_suffix ) \ +static inline __always_inline _type \ +IOAPI_INLINE ( riscv, read ## _suffix ) ( volatile _type *io_addr ) { \ + unsigned long data; \ + __asm__ __volatile__ ( "l" _insn_suffix " %0, %1" \ + : "=r" ( data ) : "m" ( *io_addr ) ); \ + return data; \ +} + +/* Single-register write */ +#define RISCV_WRITEX( _suffix, _type, _insn_suffix) \ +static inline __always_inline void \ +IOAPI_INLINE ( riscv, write ## _suffix ) ( _type data, \ + volatile _type *io_addr ) { \ + __asm__ __volatile__ ( "s" _insn_suffix " %0, %1" \ + : : "r" ( data ), "m" ( *io_addr ) ); \ +} + +/* Double-register hopefully-fused read */ +#define RISCV_READX_FUSED( _suffix, _type, _insn_suffix ) \ +static inline __always_inline _type \ +IOAPI_INLINE ( riscv, read ## _suffix ) ( volatile _type *io_addr ) { \ + union { \ + unsigned long half[2]; \ + _type data; \ + } u; \ + __asm__ __volatile__ ( "l" _insn_suffix " %0, 0(%2)\n\t" \ + "l" _insn_suffix " %1, %3(%2)\n\t" \ + : "=&r" ( u.half[0] ), \ + "=&r" ( u.half[1] ) \ + : "r" ( io_addr ), \ + "i" ( sizeof ( u.half[0] ) ) ); \ + return u.data; \ +} + +/* Double-register hopefully-fused write */ +#define RISCV_WRITEX_FUSED( _suffix, _type, _insn_suffix ) \ +static inline __always_inline void \ +IOAPI_INLINE ( riscv, write ## _suffix ) ( _type data, \ + volatile _type *io_addr ) { \ + union { \ + unsigned long half[2]; \ + _type data; \ + } u = { .data = data }; \ + __asm__ __volatile__ ( "s" _insn_suffix " %0, 0(%2)\n\t" \ + "s" _insn_suffix " %1, %3(%2)\n\t" : \ + : "r" ( u.half[0] ), \ + "r" ( u.half[1] ), \ + "r" ( io_addr ), \ + "i" ( sizeof ( u.half[0] ) ) ); \ +} + +RISCV_READX ( b, uint8_t, "bu" ); +RISCV_WRITEX ( b, uint8_t, "b" ); + +RISCV_READX ( w, uint16_t, "hu" ); +RISCV_WRITEX ( w, uint16_t, "h" ); + +#if __riscv_xlen > 32 + RISCV_READX ( l, uint32_t, "wu" ); + RISCV_WRITEX ( l, uint32_t, "w" ); +#else + RISCV_READX ( l, uint32_t, "w" ); + RISCV_WRITEX ( l, uint32_t, "w" ); +#endif + +#if __riscv_xlen >= 64 + #if __riscv_xlen > 64 + RISCV_READX ( q, uint64_t, "du" ); + RISCV_WRITEX ( q, uint64_t, "d" ); + #else + RISCV_READX ( q, uint64_t, "d" ); + RISCV_WRITEX ( q, uint64_t, "d" ); + #endif +#else + RISCV_READX_FUSED ( q, uint64_t, "w" ); + RISCV_WRITEX_FUSED ( q, uint64_t, "w" ); +#endif + +/* + * Memory barrier + * + */ +static inline __always_inline void +IOAPI_INLINE ( riscv, mb ) ( void ) { + __asm__ __volatile__ ( "fence rw, rw" ); +} + +/* Dummy PIO */ +DUMMY_PIO ( riscv ); + +#endif /* _IPXE_RISCV_IO_H */ diff --git a/src/arch/riscv32/Makefile b/src/arch/riscv32/Makefile new file mode 100644 index 0000000..0415f7c --- /dev/null +++ b/src/arch/riscv32/Makefile @@ -0,0 +1,20 @@ +# RISCV32-specific directories containing source files +# +SRCDIRS += arch/riscv32/core +SRCDIRS += arch/riscv32/libgcc + +# RISCV32-specific flags +# +CFLAGS += -march=rv32gc -mabi=ilp32d +ASFLAGS += -march=rv32gc -mabi=ilp32d +LDFLAGS += -m elf32lriscv + +# Include common RISCV Makefile +# +MAKEDEPS += arch/riscv/Makefile +include arch/riscv/Makefile + +# Include platform-specific Makefile +# +MAKEDEPS += arch/riscv32/Makefile.$(PLATFORM) +include arch/riscv32/Makefile.$(PLATFORM) diff --git a/src/arch/riscv32/Makefile.efi b/src/arch/riscv32/Makefile.efi new file mode 100644 index 0000000..2cc1a93 --- /dev/null +++ b/src/arch/riscv32/Makefile.efi @@ -0,0 +1,10 @@ +# -*- makefile -*- : Force emacs to use Makefile mode + +# Specify EFI image builder +# +ELF2EFI = $(ELF2EFI32) + +# Include generic EFI Makefile +# +MAKEDEPS += arch/riscv/Makefile.efi +include arch/riscv/Makefile.efi diff --git a/src/arch/riscv32/Makefile.linux b/src/arch/riscv32/Makefile.linux new file mode 100644 index 0000000..86ac6b8 --- /dev/null +++ b/src/arch/riscv32/Makefile.linux @@ -0,0 +1,14 @@ +# -*- makefile -*- : Force emacs to use Makefile mode + +# Starting virtual address +# +LDFLAGS += -Ttext=0x10000 + +# Compiler flags for building host API wrapper +# +LINUX_CFLAGS += -march=rv32gc -mabi=ilp32d + +# Include generic Linux Makefile +# +MAKEDEPS += arch/riscv/Makefile.linux +include arch/riscv/Makefile.linux diff --git a/src/arch/loong64/interface/efi/efiloong64_nap.c b/src/arch/riscv32/core/riscv32_byteswap.S index 0a76097..571431f 100644 --- a/src/arch/loong64/interface/efi/efiloong64_nap.c +++ b/src/arch/riscv32/core/riscv32_byteswap.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Xiaotian Wu <wuxiaotian@loongson.cn> + * Copyright (C) 2024 Michael Brown <mbrown@fensystems.co.uk>. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -21,37 +21,43 @@ * COPYING.UBDL), provided that you have satisfied its requirements. */ -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#include <ipxe/nap.h> -#include <ipxe/efi/efi.h> + FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ) /** @file * - * iPXE CPU sleeping API for EFI + * Byte swapping * */ -/** - * Sleep until next interrupt - * - */ -static void efiloong64_cpu_nap ( void ) { - /* - * I can't find any EFI API that allows us to put the CPU to - * sleep. The CpuSleep() function is defined in CpuLib.h, but - * isn't part of any exposed protocol so we have no way to - * call it. - * - * The EFI shell doesn't seem to bother sleeping the CPU; it - * just sits there idly burning power. - * - * If a shutdown is in progess, there may be nothing to - * generate an interrupt since the timer is disabled in the - * first step of ExitBootServices(). - */ - if ( ! efi_shutdown_in_progress ) - __asm__ __volatile__ ( "idle 0" ); -} + .section ".note.GNU-stack", "", @progbits + .text -PROVIDE_NAP ( efiloong64, cpu_nap, efiloong64_cpu_nap ); + .section ".text.riscv_swap", "ax", @progbits +riscv_swap: + .globl riscv_swap_word + .globl riscv_swap_half + .globl riscv_swap_byte +riscv_swap_word: + /* Swap all bytes in a0 */ + mv t0, ra + jal riscv_swap_half + mv ra, t0 + /* Swap words a0 and a1 */ + mv t1, a0 + mv a0, a1 + mv a1, t1 +riscv_swap_half: + /* Swap half-words within a0 */ + slli t2, a0, 16 + srli a0, a0, 16 + or a0, a0, t2 +riscv_swap_byte: + /* Swap bytes within each half-word of a0 */ + li t3, 0xff00ff00 + slli t4, a0, 8 + and a0, a0, t3 + and t4, t4, t3 + srli a0, a0, 8 + or a0, a0, t4 + ret + .size riscv_swap, . - riscv_swap diff --git a/src/arch/riscv32/include/bits/profile.h b/src/arch/riscv32/include/bits/profile.h new file mode 100644 index 0000000..cb96907 --- /dev/null +++ b/src/arch/riscv32/include/bits/profile.h @@ -0,0 +1,36 @@ +#ifndef _BITS_PROFILE_H +#define _BITS_PROFILE_H + +/** @file + * + * Profiling + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#include <stdint.h> + +/** + * Get profiling timestamp + * + * @ret timestamp Timestamp + */ +static inline __attribute__ (( always_inline )) uint64_t +profile_timestamp ( void ) { + uint32_t cycles_lo; + uint32_t cycles_hi; + uint32_t tmp; + + /* Read timestamp counter */ + __asm__ __volatile__ ( "\n1:\n\t" + "rdcycleh %1\n\t" + "rdcycle %0\n\t" + "rdcycleh %2\n\t" + "bne %1, %2, 1b\n\t" + : "=r" ( cycles_lo ), "=r" ( cycles_hi ), + "=r" ( tmp ) ); + return ( ( ( ( uint64_t ) cycles_hi ) << 32 ) | cycles_lo ); +} + +#endif /* _BITS_PROFILE_H */ diff --git a/src/arch/riscv32/include/ipxe/efi/dhcparch.h b/src/arch/riscv32/include/ipxe/efi/dhcparch.h new file mode 100644 index 0000000..b74df19 --- /dev/null +++ b/src/arch/riscv32/include/ipxe/efi/dhcparch.h @@ -0,0 +1,20 @@ +#ifndef _IPXE_EFI_DHCPARCH_H +#define _IPXE_EFI_DHCPARCH_H + +/** @file + * + * DHCP client architecture definitions + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#include <ipxe/dhcp.h> + +/** DHCP client architecture */ +#define DHCP_ARCH_CLIENT_ARCHITECTURE DHCP_CLIENT_ARCHITECTURE_RISCV32 + +/** DHCP client network device interface */ +#define DHCP_ARCH_CLIENT_NDI 1 /* UNDI */ , 3, 10 /* v3.10 */ + +#endif /* _IPXE_EFI_DHCPARCH_H */ diff --git a/src/arch/riscv32/include/limits.h b/src/arch/riscv32/include/limits.h new file mode 100644 index 0000000..bb48b75 --- /dev/null +++ b/src/arch/riscv32/include/limits.h @@ -0,0 +1,61 @@ +#ifndef LIMITS_H +#define LIMITS_H 1 + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +/* Number of bits in a `char' */ +#define CHAR_BIT 8 + +/* Minimum and maximum values a `signed char' can hold */ +#define SCHAR_MIN (-128) +#define SCHAR_MAX 127 + +/* Maximum value an `unsigned char' can hold. (Minimum is 0.) */ +#define UCHAR_MAX 255 + +/* Minimum and maximum values a `char' can hold */ +#define CHAR_MIN SCHAR_MIN +#define CHAR_MAX SCHAR_MAX + +/* Minimum and maximum values a `signed short int' can hold */ +#define SHRT_MIN (-32768) +#define SHRT_MAX 32767 + +/* Maximum value an `unsigned short' can hold. (Minimum is 0.) */ +#define USHRT_MAX 65535 + + +/* Minimum and maximum values a `signed int' can hold */ +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 + +/* Maximum value an `unsigned int' can hold. (Minimum is 0.) */ +#define UINT_MAX 4294967295U + + +/* Minimum and maximum values a `signed int' can hold */ +#define INT_MAX 2147483647 +#define INT_MIN (-INT_MAX - 1) + + +/* Maximum value an `unsigned int' can hold. (Minimum is 0.) */ +#define UINT_MAX 4294967295U + + +/* Minimum and maximum values a `signed long' can hold */ +#define LONG_MAX 2147483647 +#define LONG_MIN (-LONG_MAX - 1L) + +/* Maximum value an `unsigned long' can hold. (Minimum is 0.) */ +#define ULONG_MAX 4294967295UL + +/* Minimum and maximum values a `signed long long' can hold */ +#define LLONG_MAX 9223372036854775807LL +#define LLONG_MIN (-LONG_MAX - 1LL) + + +/* Maximum value an `unsigned long long' can hold. (Minimum is 0.) */ +#define ULLONG_MAX 18446744073709551615ULL + + +#endif /* LIMITS_H */ diff --git a/src/arch/riscv32/libgcc/llshift.S b/src/arch/riscv32/libgcc/llshift.S new file mode 100644 index 0000000..8ad6a6d --- /dev/null +++ b/src/arch/riscv32/libgcc/llshift.S @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2024 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * You can also choose to distribute this program under the terms of + * the Unmodified Binary Distribution Licence (as given in the file + * COPYING.UBDL), provided that you have satisfied its requirements. + */ + + FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ) + +/** @file + * + * Long shifts + * + */ + + .section ".note.GNU-stack", "", @progbits + .text + +/** + * Shift left + * + * @v a1:a0 Value to shift + * @v a2 Shift amount + * @ret a1:a0 Shifted value + */ + .section ".text.__ashldi3", "ax", @progbits + .globl __ashldi3 +__ashldi3: + /* Perform shift by 32 bits, if applicable */ + li t0, 32 + sub t1, t0, a2 + bgtz t1, 1f + mv a1, a0 + mv a0, zero +1: /* Perform shift by modulo-32 bits, if applicable */ + andi a2, a2, 0x1f + beqz a2, 2f + srl t2, a0, t1 + sll a0, a0, a2 + sll a1, a1, a2 + or a1, a1, t2 +2: ret + .size __ashldi3, . - __ashldi3 + +/** + * Logical shift right + * + * @v a1:a0 Value to shift + * @v a2 Shift amount + * @ret a1:a0 Shifted value + */ + .section ".text.__lshrdi3", "ax", @progbits + .globl __lshrdi3 +__lshrdi3: + /* Perform shift by 32 bits, if applicable */ + li t0, 32 + sub t1, t0, a2 + bgtz t1, 1f + mv a0, a1 + mv a1, zero +1: /* Perform shift by modulo-32 bits, if applicable */ + andi a2, a2, 0x1f + beqz a2, 2f + sll t2, a1, t1 + srl a1, a1, a2 + srl a0, a0, a2 + or a0, a0, t2 +2: ret + .size __lshrdi3, . - __lshrdi3 + +/** + * Arithmetic shift right + * + * @v a1:a0 Value to shift + * @v a2 Shift amount + * @ret a1:a0 Shifted value + */ + .section ".text.__ashrdi3", "ax", @progbits + .globl __ashrdi3 +__ashrdi3: + /* Perform shift by 32 bits, if applicable */ + li t0, 32 + sub t1, t0, a2 + bgtz t1, 1f + mv a0, a1 + srai a1, a1, 16 + srai a1, a1, 16 +1: /* Perform shift by modulo-32 bits, if applicable */ + andi a2, a2, 0x1f + beqz a2, 2f + sll t2, a1, t1 + sra a1, a1, a2 + srl a0, a0, a2 + or a0, a0, t2 +2: ret + .size __ashrdi3, . - __ashrdi3 diff --git a/src/arch/riscv64/Makefile b/src/arch/riscv64/Makefile new file mode 100644 index 0000000..2fd18fc --- /dev/null +++ b/src/arch/riscv64/Makefile @@ -0,0 +1,19 @@ +# RISCV64-specific directories containing source files +# +SRCDIRS += arch/riscv64/core + +# RISCV64-specific flags +# +CFLAGS += -march=rv64gc -mabi=lp64d +ASFLAGS += -march=rv64gc -mabi=lp64d +LDFLAGS += -m elf64lriscv + +# Include common RISCV Makefile +# +MAKEDEPS += arch/riscv/Makefile +include arch/riscv/Makefile + +# Include platform-specific Makefile +# +MAKEDEPS += arch/riscv64/Makefile.$(PLATFORM) +include arch/riscv64/Makefile.$(PLATFORM) diff --git a/src/arch/riscv64/Makefile.efi b/src/arch/riscv64/Makefile.efi new file mode 100644 index 0000000..3948ca1 --- /dev/null +++ b/src/arch/riscv64/Makefile.efi @@ -0,0 +1,10 @@ +# -*- makefile -*- : Force emacs to use Makefile mode + +# Specify EFI image builder +# +ELF2EFI = $(ELF2EFI64) + +# Include generic EFI Makefile +# +MAKEDEPS += arch/riscv/Makefile.efi +include arch/riscv/Makefile.efi diff --git a/src/arch/riscv64/Makefile.linux b/src/arch/riscv64/Makefile.linux new file mode 100644 index 0000000..5ceafed --- /dev/null +++ b/src/arch/riscv64/Makefile.linux @@ -0,0 +1,10 @@ +# -*- makefile -*- : Force emacs to use Makefile mode + +# Starting virtual address +# +LDFLAGS += -Ttext=0x10000 + +# Include generic Linux Makefile +# +MAKEDEPS += arch/riscv/Makefile.linux +include arch/riscv/Makefile.linux diff --git a/src/arch/riscv64/core/riscv64_byteswap.S b/src/arch/riscv64/core/riscv64_byteswap.S new file mode 100644 index 0000000..ec2b0b9 --- /dev/null +++ b/src/arch/riscv64/core/riscv64_byteswap.S @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2024 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * You can also choose to distribute this program under the terms of + * the Unmodified Binary Distribution Licence (as given in the file + * COPYING.UBDL), provided that you have satisfied its requirements. + */ + + FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ) + +/** @file + * + * Byte swapping + * + */ + + .section ".note.GNU-stack", "", @progbits + .text + + .section ".text.riscv_swap", "ax", @progbits +riscv_swap: + .globl riscv_swap_word + .globl riscv_swap_half + .globl riscv_swap_byte +riscv_swap_word: + /* Swap low and high words of a0 */ + slli t0, a0, 32 + srli a0, a0, 32 + or a0, a0, t0 +riscv_swap_half: + /* Swap half-words within each word of a0 */ + ld t1, mask16 + slli t2, a0, 16 + and a0, a0, t1 + and t2, t2, t1 + srli a0, a0, 16 + or a0, a0, t2 +riscv_swap_byte: + /* Swap bytes within each half-word of a0 */ + ld t3, mask8 + slli t4, a0, 8 + and a0, a0, t3 + and t4, t4, t3 + srli a0, a0, 8 + or a0, a0, t4 + ret +mask16: .dword 0xffff0000ffff0000 +mask8: .dword 0xff00ff00ff00ff00 + .size riscv_swap, . - riscv_swap diff --git a/src/arch/riscv64/include/bits/profile.h b/src/arch/riscv64/include/bits/profile.h new file mode 100644 index 0000000..2c8e29a --- /dev/null +++ b/src/arch/riscv64/include/bits/profile.h @@ -0,0 +1,28 @@ +#ifndef _BITS_PROFILE_H +#define _BITS_PROFILE_H + +/** @file + * + * Profiling + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#include <stdint.h> + +/** + * Get profiling timestamp + * + * @ret timestamp Timestamp + */ +static inline __attribute__ (( always_inline )) uint64_t +profile_timestamp ( void ) { + uint64_t cycles; + + /* Read timestamp counter */ + __asm__ __volatile__ ( "rdcycle %0" : "=r" ( cycles ) ); + return cycles; +} + +#endif /* _BITS_PROFILE_H */ diff --git a/src/arch/riscv64/include/ipxe/efi/dhcparch.h b/src/arch/riscv64/include/ipxe/efi/dhcparch.h new file mode 100644 index 0000000..33bca04 --- /dev/null +++ b/src/arch/riscv64/include/ipxe/efi/dhcparch.h @@ -0,0 +1,20 @@ +#ifndef _IPXE_EFI_DHCPARCH_H +#define _IPXE_EFI_DHCPARCH_H + +/** @file + * + * DHCP client architecture definitions + * + */ + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +#include <ipxe/dhcp.h> + +/** DHCP client architecture */ +#define DHCP_ARCH_CLIENT_ARCHITECTURE DHCP_CLIENT_ARCHITECTURE_RISCV64 + +/** DHCP client network device interface */ +#define DHCP_ARCH_CLIENT_NDI 1 /* UNDI */ , 3, 10 /* v3.10 */ + +#endif /* _IPXE_EFI_DHCPARCH_H */ diff --git a/src/arch/riscv64/include/limits.h b/src/arch/riscv64/include/limits.h new file mode 100644 index 0000000..a1374a1 --- /dev/null +++ b/src/arch/riscv64/include/limits.h @@ -0,0 +1,61 @@ +#ifndef LIMITS_H +#define LIMITS_H 1 + +FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); + +/* Number of bits in a `char' */ +#define CHAR_BIT 8 + +/* Minimum and maximum values a `signed char' can hold */ +#define SCHAR_MIN (-128) +#define SCHAR_MAX 127 + +/* Maximum value an `unsigned char' can hold. (Minimum is 0.) */ +#define UCHAR_MAX 255 + +/* Minimum and maximum values a `char' can hold */ +#define CHAR_MIN SCHAR_MIN +#define CHAR_MAX SCHAR_MAX + +/* Minimum and maximum values a `signed short int' can hold */ +#define SHRT_MIN (-32768) +#define SHRT_MAX 32767 + +/* Maximum value an `unsigned short' can hold. (Minimum is 0.) */ +#define USHRT_MAX 65535 + + +/* Minimum and maximum values a `signed int' can hold */ +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 + +/* Maximum value an `unsigned int' can hold. (Minimum is 0.) */ +#define UINT_MAX 4294967295U + + +/* Minimum and maximum values a `signed int' can hold */ +#define INT_MAX 2147483647 +#define INT_MIN (-INT_MAX - 1) + + +/* Maximum value an `unsigned int' can hold. (Minimum is 0.) */ +#define UINT_MAX 4294967295U + + +/* Minimum and maximum values a `signed long' can hold */ +#define LONG_MAX 9223372036854775807L +#define LONG_MIN (-LONG_MAX - 1L) + +/* Maximum value an `unsigned long' can hold. (Minimum is 0.) */ +#define ULONG_MAX 18446744073709551615UL + +/* Minimum and maximum values a `signed long long' can hold */ +#define LLONG_MAX 9223372036854775807LL +#define LLONG_MIN (-LONG_MAX - 1LL) + + +/* Maximum value an `unsigned long long' can hold. (Minimum is 0.) */ +#define ULLONG_MAX 18446744073709551615ULL + + +#endif /* LIMITS_H */ diff --git a/src/arch/x86/Makefile b/src/arch/x86/Makefile index ef80136..4a4d8ee 100644 --- a/src/arch/x86/Makefile +++ b/src/arch/x86/Makefile @@ -3,9 +3,9 @@ ASM_TCHAR := @ ASM_TCHAR_OPS := @ -# Include common x86 headers +# Include x86-specific headers # -INCDIRS += arch/x86/include +INCDIRS := arch/$(ARCH)/include arch/x86/include $(INCDIRS) # x86-specific directories containing source files # diff --git a/src/arch/x86/core/cpuid.c b/src/arch/x86/core/cpuid.c index 1a7c93e..b7d9fb6 100644 --- a/src/arch/x86/core/cpuid.c +++ b/src/arch/x86/core/cpuid.c @@ -84,8 +84,8 @@ int cpuid_supported ( uint32_t function ) { return rc; /* Find highest supported function number within this family */ - cpuid ( ( function & CPUID_EXTENDED ), 0, &max_function, &discard_b, - &discard_c, &discard_d ); + cpuid ( ( function & ( CPUID_EXTENDED | CPUID_HYPERVISOR ) ), 0, + &max_function, &discard_b, &discard_c, &discard_d ); /* Fail if maximum function number is meaningless (e.g. if we * are attempting to call an extended function on a CPU which diff --git a/src/arch/x86/core/cpuid_settings.c b/src/arch/x86/core/cpuid_settings.c index 0b67ee9..9bc69f4 100644 --- a/src/arch/x86/core/cpuid_settings.c +++ b/src/arch/x86/core/cpuid_settings.c @@ -38,7 +38,8 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); * * Bit 31 Extended function * Bits 30-24 (bit 22 = 1) Subfunction number - * (bit 22 = 0) Number of consecutive functions to call, minus one + * Bit 30 (bit 22 = 0) Hypervisor function + * Bits 29-24 (bit 22 = 0) Number of consecutive functions to call, minus one * Bit 23 Return result as little-endian (used for strings) * Bit 22 Interpret bits 30-24 as a subfunction number * Bits 21-18 Unused @@ -98,7 +99,7 @@ enum cpuid_flags { * @v tag Setting tag * @ret function Starting function number */ -#define CPUID_FUNCTION( tag ) ( (tag) & 0x800000ffUL ) +#define CPUID_FUNCTION( tag ) ( (tag) & 0xc00000ffUL ) /** * Extract subfunction number from CPUID setting tag @@ -109,6 +110,14 @@ enum cpuid_flags { #define CPUID_SUBFUNCTION( tag ) ( ( (tag) >> 24 ) & 0x7f ) /** + * Extract number of consecutive functions from CPUID setting tag + * + * @v tag Setting tag + * @ret num_functions Number of consecutive functions + */ +#define CPUID_NUM_FUNCTIONS( tag ) ( ( ( (tag) >> 24 ) & 0x3f ) + 1 ) + +/** * Extract register array from CPUID setting tag * * @v tag Setting tag @@ -165,12 +174,13 @@ static int cpuid_settings_fetch ( struct settings *settings, /* Call each function in turn */ function = CPUID_FUNCTION ( setting->tag ); - subfunction = CPUID_SUBFUNCTION ( setting->tag ); if ( setting->tag & CPUID_USE_SUBFUNCTION ) { + function &= ~CPUID_HYPERVISOR; + subfunction = CPUID_SUBFUNCTION ( setting->tag ); num_functions = 1; } else { - num_functions = ( subfunction + 1 ); subfunction = 0; + num_functions = CPUID_NUM_FUNCTIONS ( setting->tag ); } for ( ; num_functions-- ; function++ ) { diff --git a/src/arch/x86/core/gdbmach.c b/src/arch/x86/core/gdbmach.c index af6abfe..d4d187e 100644 --- a/src/arch/x86/core/gdbmach.c +++ b/src/arch/x86/core/gdbmach.c @@ -31,7 +31,6 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); #include <ipxe/uaccess.h> #include <ipxe/gdbstub.h> #include <librm.h> -#include <gdbmach.h> /** @file * diff --git a/src/arch/x86/core/pcidirect.c b/src/arch/x86/core/pcidirect.c index f4659a1..90d4623 100644 --- a/src/arch/x86/core/pcidirect.c +++ b/src/arch/x86/core/pcidirect.c @@ -45,6 +45,7 @@ void pcidirect_prepare ( struct pci_device *pci, int where ) { PCIDIRECT_CONFIG_ADDRESS ); } +PROVIDE_PCIAPI_INLINE ( direct, pci_can_probe ); PROVIDE_PCIAPI_INLINE ( direct, pci_discover ); PROVIDE_PCIAPI_INLINE ( direct, pci_read_config_byte ); PROVIDE_PCIAPI_INLINE ( direct, pci_read_config_word ); diff --git a/src/arch/x86/include/bits/nap.h b/src/arch/x86/include/bits/nap.h index 7103b94..b7dea73 100644 --- a/src/arch/x86/include/bits/nap.h +++ b/src/arch/x86/include/bits/nap.h @@ -10,6 +10,13 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); #include <ipxe/bios_nap.h> -#include <ipxe/efi/efix86_nap.h> -#endif /* _BITS_MAP_H */ +/** + * Sleep until next CPU interrupt + * + */ +static inline __attribute__ (( always_inline )) void cpu_halt ( void ) { + __asm__ __volatile__ ( "hlt" ); +} + +#endif /* _BITS_NAP_H */ diff --git a/src/arch/x86/include/ipxe/cpuid.h b/src/arch/x86/include/ipxe/cpuid.h index 90d1bf0..99b91c5 100644 --- a/src/arch/x86/include/ipxe/cpuid.h +++ b/src/arch/x86/include/ipxe/cpuid.h @@ -33,6 +33,9 @@ struct x86_features { /** CPUID extended function */ #define CPUID_EXTENDED 0x80000000UL +/** CPUID hypervisor function */ +#define CPUID_HYPERVISOR 0x40000000UL + /** Get vendor ID and largest standard function */ #define CPUID_VENDOR_ID 0x00000000UL diff --git a/src/arch/x86/include/ipxe/efi/efix86_nap.h b/src/arch/x86/include/ipxe/efi/efix86_nap.h deleted file mode 100644 index 1a391c9..0000000 --- a/src/arch/x86/include/ipxe/efi/efix86_nap.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _IPXE_EFIX86_NAP_H -#define _IPXE_EFIX86_NAP_H - -/** @file - * - * EFI CPU sleeping - * - */ - -FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); - -#ifdef NAP_EFIX86 -#define NAP_PREFIX_efix86 -#else -#define NAP_PREFIX_efix86 __efix86_ -#endif - -#endif /* _IPXE_EFIX86_NAP_H */ diff --git a/src/arch/x86/include/ipxe/pcibios.h b/src/arch/x86/include/ipxe/pcibios.h index 3caea1c..ef95856 100644 --- a/src/arch/x86/include/ipxe/pcibios.h +++ b/src/arch/x86/include/ipxe/pcibios.h @@ -33,6 +33,16 @@ extern int pcibios_write ( struct pci_device *pci, uint32_t command, uint32_t value ); /** + * Check if PCI bus probing is allowed + * + * @ret ok Bus probing is allowed + */ +static inline __always_inline int +PCIAPI_INLINE ( pcbios, pci_can_probe ) ( void ) { + return 1; +} + +/** * Read byte from PCI configuration space via PCI BIOS * * @v pci PCI device diff --git a/src/arch/x86/include/ipxe/pcicloud.h b/src/arch/x86/include/ipxe/pcicloud.h index 5226890..1feef56 100644 --- a/src/arch/x86/include/ipxe/pcicloud.h +++ b/src/arch/x86/include/ipxe/pcicloud.h @@ -15,4 +15,14 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); #define PCIAPI_PREFIX_cloud __cloud_ #endif +/** + * Check if PCI bus probing is allowed + * + * @ret ok Bus probing is allowed + */ +static inline __always_inline int +PCIAPI_INLINE ( cloud, pci_can_probe ) ( void ) { + return 1; +} + #endif /* _IPXE_PCICLOUD_H */ diff --git a/src/arch/x86/include/ipxe/pcidirect.h b/src/arch/x86/include/ipxe/pcidirect.h index 98c6a2b..999b527 100644 --- a/src/arch/x86/include/ipxe/pcidirect.h +++ b/src/arch/x86/include/ipxe/pcidirect.h @@ -26,6 +26,16 @@ struct pci_device; extern void pcidirect_prepare ( struct pci_device *pci, int where ); /** + * Check if PCI bus probing is allowed + * + * @ret ok Bus probing is allowed + */ +static inline __always_inline int +PCIAPI_INLINE ( direct, pci_can_probe ) ( void ) { + return 1; +} + +/** * Find next PCI bus:dev.fn address range in system * * @v busdevfn Starting PCI bus:dev.fn address diff --git a/src/arch/x86/interface/pcbios/pcibios.c b/src/arch/x86/interface/pcbios/pcibios.c index 7b7a769..ebe40ba 100644 --- a/src/arch/x86/interface/pcbios/pcibios.c +++ b/src/arch/x86/interface/pcbios/pcibios.c @@ -120,6 +120,7 @@ int pcibios_write ( struct pci_device *pci, uint32_t command, uint32_t value ){ return ( status >> 8 ); } +PROVIDE_PCIAPI_INLINE ( pcbios, pci_can_probe ); PROVIDE_PCIAPI ( pcbios, pci_discover, pcibios_discover ); PROVIDE_PCIAPI_INLINE ( pcbios, pci_read_config_byte ); PROVIDE_PCIAPI_INLINE ( pcbios, pci_read_config_word ); diff --git a/src/arch/x86/interface/pcbios/pcicloud.c b/src/arch/x86/interface/pcbios/pcicloud.c index 98ba38b..f7d4a2d 100644 --- a/src/arch/x86/interface/pcbios/pcicloud.c +++ b/src/arch/x86/interface/pcbios/pcicloud.c @@ -148,6 +148,7 @@ static void * pcicloud_ioremap ( struct pci_device *pci, return pcicloud->pci_ioremap ( pci, bus_addr, len ); } +PROVIDE_PCIAPI_INLINE ( cloud, pci_can_probe ); PROVIDE_PCIAPI ( cloud, pci_discover, pcicloud_discover ); PROVIDE_PCIAPI ( cloud, pci_read_config_byte, pcicloud_read_config_byte ); PROVIDE_PCIAPI ( cloud, pci_read_config_word, pcicloud_read_config_word ); diff --git a/src/arch/x86_64/Makefile.efi b/src/arch/x86_64/Makefile.efi index 0041bb8..f383756 100644 --- a/src/arch/x86_64/Makefile.efi +++ b/src/arch/x86_64/Makefile.efi @@ -12,10 +12,6 @@ CFLAGS += -mno-red-zone # ELF2EFI = $(ELF2EFI64) -# Specify EFI boot file -# -EFI_BOOT_FILE = bootx64.efi - # Include generic EFI Makefile # MAKEDEPS += arch/x86/Makefile.efi diff --git a/src/arch/x86_64/include/gdbmach.h b/src/arch/x86_64/include/bits/gdbmach.h index 367405f..367405f 100644 --- a/src/arch/x86_64/include/gdbmach.h +++ b/src/arch/x86_64/include/bits/gdbmach.h diff --git a/src/arch/x86_64/include/setjmp.h b/src/arch/x86_64/include/bits/setjmp.h index 69835d9..adfb869 100644 --- a/src/arch/x86_64/include/setjmp.h +++ b/src/arch/x86_64/include/bits/setjmp.h @@ -1,5 +1,5 @@ -#ifndef _SETJMP_H -#define _SETJMP_H +#ifndef _BITS_SETJMP_H +#define _BITS_SETJMP_H FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); @@ -25,10 +25,4 @@ typedef struct { uint64_t r15; } jmp_buf[1]; -extern int __asmcall __attribute__ (( returns_twice )) -setjmp ( jmp_buf env ); - -extern void __asmcall __attribute__ (( noreturn )) -longjmp ( jmp_buf env, int val ); - -#endif /* _SETJMP_H */ +#endif /* _BITS_SETJMP_H */ |