rocket-tools/riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2025-07-04	target: riscv: Add Svrsw60t59b extension support	Alexandre Ghiti	1	-0/+8
2025-07-04	target/riscv/cpu.c: add 'sdtrig' in riscv,isa	Daniel Henrique Barboza	1	-0/+9
2025-07-04	target/riscv: remove capital 'Z' CPU properties	Daniel Henrique Barboza	1	-30/+1
2025-07-04	target/riscv: add profile->present flag	Daniel Henrique Barboza	1	-8/+3
2025-07-04	target/riscv/tcg: decouple profile enablement from user prop	Daniel Henrique Barboza	1	-60/+67
2025-07-04	target/riscv/tcg: restrict satp_mode changes in cpu_set_profile	Daniel Henrique Barboza	1	-7/+7
2025-05-28	target/riscv: Fill in TCGCPUOps.pointer_wrap	Richard Henderson	1	-0/+26
2025-05-20	target/riscv: store RISCVCPUDef struct directly in the class	Paolo Bonzini	1	-5/+5
2025-05-20	target/riscv: cpu: store max SATP mode as a single integer	Paolo Bonzini	1	-1/+2
2025-04-30	accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps	Richard Henderson	1	-1/+2
2025-04-30	accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state	Richard Henderson	1	-6/+6
2025-04-30	target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.c	Richard Henderson	1	-0/+98
2025-04-30	accel/tcg: Introduce TCGCPUOps.cpu_exec_reset	Richard Henderson	1	-0/+1
2025-04-30	include: Remove 'exec/exec-all.h'	Philippe Mathieu-Daudé	1	-1/+0
2025-04-25	qom: Have class_init() take a const data argument	Philippe Mathieu-Daudé	1	-1/+1
2025-04-23	tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field	Philippe Mathieu-Daudé	1	-0/+1
2025-04-23	target/riscv: Remove AccelCPUClass::cpu_class_init need	Philippe Mathieu-Daudé	2	-15/+3
2025-04-23	tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h'	Philippe Mathieu-Daudé	1	-0/+1
2025-04-23	tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally	Philippe Mathieu-Daudé	1	-1/+1
2025-04-23	tcg: Define guest_default_memory_order in TCGCPUOps	Philippe Mathieu-Daudé	1	-0/+2
2025-04-23	target/riscv: Do not expose rv128 CPU on user mode emulation	Philippe Mathieu-Daudé	1	-2/+3
2025-04-23	exec/cpu-all: remove exec/target_page include	Pierrick Bouvier	1	-0/+1
2025-04-23	target/riscv: Restrict SoftMMU mmu_index() to TCG	Philippe Mathieu-Daudé	1	-0/+6
2025-03-06	accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h'	Philippe Mathieu-Daudé	1	-1/+1
2025-03-06	accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h'	Philippe Mathieu-Daudé	1	-1/+1
2025-03-04	target/riscv/cpu.c: create flag for ziccrse	Daniel Henrique Barboza	1	-0/+2
2025-03-04	target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.	Rajnesh Kanwal	1	-0/+11
2025-03-04	target/riscv: remove warnings about Smdbltrp/Smrnmi being disabled	Clément Léger	1	-5/+3
2025-03-04	target/riscv: change priv_ver check in validate_profile()	Daniel Henrique Barboza	1	-1/+1
2025-03-04	target/riscv: add profile u_parent and s_parent	Daniel Henrique Barboza	1	-9/+26
2025-02-25	target/riscv: move 128-bit check to TCG realize	Paolo Bonzini	1	-0/+9
2025-01-19	target/riscv: Add Smdbltrp ISA extension enable switch	Clément Léger	1	-0/+10
2025-01-19	target/riscv: Invoke pmu init after feature enable	Atish Patra	1	-14/+14
2025-01-19	target/riscv: Add Smrnmi cpu extension	Tommy Wu	1	-0/+9
2025-01-19	target/riscv: Remove obsolete pointer masking extension code.	Alexey Baturo	1	-3/+2
2025-01-19	target/riscv/tcg: add sha	Daniel Henrique Barboza	1	-0/+8
2024-12-24	accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core	Richard Henderson	1	-0/+1
2024-12-21	Merge tag 'exec-20241220' of https://github.com/philmd/qemu into staging	Stefan Hajnoczi	1	-0/+1
2024-12-20	accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h'	Philippe Mathieu-Daudé	1	-0/+1
2024-12-20	target/riscv: add ssstateen	Daniel Henrique Barboza	1	-1/+8
2024-12-20	target/riscv/tcg: hide warn for named feats when disabling via priv_ver	Daniel Henrique Barboza	1	-3/+10
2024-12-20	target/riscv: Check svukte is not enabled in RV32	Fea.Wang	1	-0/+5
2024-10-30	target/riscv: AMO operations always raise store/AMO fault	Deepak Gupta	1	-0/+1
2024-10-30	target/riscv: Add zicfiss extension	Deepak Gupta	1	-0/+23
2024-10-30	target/riscv: Add zicfilp extension	Deepak Gupta	1	-0/+5
2024-10-02	target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule	Daniel Henrique Barboza	1	-3/+10
2024-07-18	target/riscv: Add zcmop extension	LIU Zhiwei	1	-0/+5
2024-07-11	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	Peter Maydell	1	-0/+2
2024-06-26	target/riscv: Remove extension auto-update check statements	Frank Chang	1	-119/+0
2024-06-26	target/riscv: Add Zc extension implied rule	Frank Chang	1	-0/+34