| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-07-25 | target/arm: LD1Q, ST1Q are vector + scalar, not scalar + vector | Peter Maydell | 1 | -6/+6 |
| 2025-07-21 | target/arm: Make LD1Q decode and trans fn agree about a->u | Peter Maydell | 1 | -1/+1 |
| 2025-07-21 | target/arm: Add BFMLA, BFMLS (indexed) | Peter Maydell | 1 | -0/+2 |
| 2025-07-21 | target/arm: Add BFMUL (indexed) | Peter Maydell | 1 | -0/+1 |
| 2025-07-04 | target/arm: Implement LD1Q, ST1Q for SVE2p1 | Richard Henderson | 1 | -0/+8 |
| 2025-07-04 | target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1 | Richard Henderson | 1 | -0/+31 |
| 2025-07-04 | target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1 | Richard Henderson | 1 | -0/+20 |
| 2025-07-04 | target/arm: Split the ST_zpri and ST_zprr patterns | Richard Henderson | 1 | -8/+18 |
| 2025-07-04 | target/arm: Implement SME2 counted predicate register load/store | Richard Henderson | 1 | -0/+50 |
| 2025-07-04 | target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1 | Richard Henderson | 1 | -0/+3 |
| 2025-07-04 | target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1 | Richard Henderson | 1 | -0/+6 |
| 2025-07-04 | target/arm: Implement PMOV for SME2p1/SVE2p1 | Richard Henderson | 1 | -0/+17 |
| 2025-07-04 | target/arm: Implement EXTQ for SME2p1/SVE2p1 | Richard Henderson | 1 | -0/+2 |
| 2025-07-04 | target/arm: Implement DUPQ for SME2p1/SVE2p1 | Richard Henderson | 1 | -0/+6 |
| 2025-07-04 | target/arm: Implement CNTP (predicate as counter) for SME2/SVE2p1 | Richard Henderson | 1 | -1/+2 |
| 2025-07-04 | target/arm: Implement BFMLSLB{L, T} for SME2/SVE2p1 | Richard Henderson | 1 | -0/+6 |
| 2025-07-04 | target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1 | Richard Henderson | 1 | -0/+8 |
| 2025-07-04 | target/arm: Implement ANDQV, ORQV, EORQV for SVE2p1 | Richard Henderson | 1 | -0/+5 |
| 2025-07-04 | target/arm: Implement SVE2p1 PEXT | Richard Henderson | 1 | -0/+6 |
| 2025-07-04 | target/arm: Implement {ADD, SMIN, SMAX, UMIN, UMAX}QV for SVE2p1 | Richard Henderson | 1 | -0/+7 |
| 2025-07-04 | target/arm: Implement SVE2p1 PTRUE (predicate as counter) | Richard Henderson | 1 | -0/+1 |
| 2025-07-04 | target/arm: Implement SVE2p1 WHILE (predicate as counter) | Richard Henderson | 1 | -0/+11 |
| 2025-07-04 | target/arm: Implement SVE2p1 WHILE (predicate pair) | Richard Henderson | 1 | -0/+8 |
| 2025-07-04 | target/arm: Split trans_WHILE to lt and gt | Richard Henderson | 1 | -1/+3 |
| 2025-07-04 | target/arm: Implement FCLAMP for SME2, SVE2p1 | Richard Henderson | 1 | -0/+2 |
| 2025-07-04 | target/arm: Implement SQCVTN, UQCVTN, SQCVTUN for SME2/SVE2p1 | Richard Henderson | 1 | -4/+16 |
| 2025-07-04 | target/arm: Implement SDOT, UDOT (2-way) for SME2/SVE2p1 | Richard Henderson | 1 | -1/+7 |
| 2025-07-04 | target/arm: Tighten USDOT (vectors) decode | Richard Henderson | 1 | -1/+1 |
| 2025-07-04 | target/arm: Rename SVE SDOT and UDOT patterns | Richard Henderson | 1 | -6/+6 |
| 2025-07-04 | target/arm: Implement SME2 FDOT | Richard Henderson | 1 | -2/+5 |
| 2025-07-04 | target/arm: Replace @rda_rn_rm_e0 in sve.decode | Richard Henderson | 1 | -24/+24 |
| 2023-07-08 | target/arm: Demultiplex AESE and AESMC | Richard Henderson | 1 | -2/+2 |
| 2023-02-27 | target/arm: move translate modules to tcg/ | Fabiano Rosas | 1 | -0/+1702 |
