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9 dayspage-vary: Build finalize_target_page_bits as common codeRichard Henderson1-4/+0
Use target_info->page_bits_init to merge finalize_target_page_bits_common into finalize_target_page_bits in page-vary-common.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20260217095106.598486-6-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9 dayspage-vary: Build set_preferred_target_page_bits as common codeRichard Henderson1-1/+0
Use target_info->page_bits_vary to merge set_preferred_target_page_bits_common into set_preferred_target_page_bits in page-vary-common.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260217095106.598486-5-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9 dayspage-vary: Expose TARGET_PAGE_BITS_MIN definitionPhilippe Mathieu-Daudé1-0/+14
We'll use TARGET_PAGE_BITS_MIN in page-vary-common.c, so expose it via "exec/page-vary.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260213182713.44924-3-philmd@linaro.org>
9 daysexec: Drop TARGET_PHYS_ADDR_SPACE_BITSAnton Johansson1-3/+0
The macro is no longer in use and can safely be dropped. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Anton Johansson <anjo@rev.ng> Message-ID: <20260218-phys_addr-v6-7-a603bf363218@rev.ng> [PMD: Keep TARGET_PHYS_ADDR_SPACE_BITS poisoned] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-02-09target/or1k: Rename from openriscRichard Henderson1-1/+1
This is the minimal change beginning with TARGET_ARCH in configs/targets/or1k-* from openrisc to or1k, then adjust TARGET_OR1K, QEMU_ARCH_OR1K, directory names, and meson.build to match. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260205030244.266447-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-02-02accel/tcg: Fix iotlb_to_section() for different AddressSpaceJim Shu1-2/+2
'CPUTLBEntryFull.xlat_section' stores section_index in last 12 bits to find the correct section when CPU access the IO region over the IOTLB. However, section_index is only unique inside single AddressSpace. If address space translation is over IOMMUMemoryRegion, it could return section from other AddressSpace. 'iotlb_to_section()' API only finds the sections from CPU's AddressSpace so that it couldn't find section in other AddressSpace. Thus, using 'iotlb_to_section()' API will find the wrong section and QEMU will have wrong load/store access. To fix this bug of iotlb_to_section(), store complete MemoryRegionSection pointer in CPUTLBEntryFull to replace the section_index in xlat_section. Rename 'xlat_section' to 'xlat' as we remove last 12 bits section_index inside. Also, since we directly use section pointer in the CPUTLBEntryFull (full->section), we can remove the unused functions: iotlb_to_section(), memory_region_section_get_iotlb(). This bug occurs only when (1) IOMMUMemoryRegion is in the path of CPU access. (2) IOMMUMemoryRegion returns different target_as and the section is in the IO region. Common IOMMU devices don't have this issue since they are only in the path of DMA access. Currently, the bug only occurs when ARM MPC device (hw/misc/tz-mpc.c) returns 'blocked_io_as' to emulate blocked access handling. Upcoming RISC-V wgChecker [1] and IOPMP [2] devices are also affected by this bug. [1] RISC-V WG: https://patchew.org/QEMU/20251021155548.584543-1-jim.shu@sifive.com/ [2] RISC-V IOPMP: https://patchew.org/QEMU/20250312093735.1517740-1-ethan84@andestech.com/ Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Burton <mburton@qti.qualcomm.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20260128152348.2095427-3-jim.shu@sifive.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-01-22cpus: Allocate maximum number of ASes supported by the archPhilippe Mathieu-Daudé1-4/+0
Instead of computing the number of address spaces used for a given architecture, machine, and CPU configuration, simplify the code by always allocating the maximum number of CPUAddressSpaces supported by the architecture. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260116185814.108560-5-gustavo.romero@linaro.org>
2026-01-22system: Allow restricting the legacy MO_TE* 'native-endian' definitionsPhilippe Mathieu-Daudé1-0/+4
Guard the native endian definitions we want to remove by surrounding them with TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API #ifdef'ry. Once a target gets cleaned we'll set the definition in the target config, then the target won't be able to use the legacy API anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260109165058.59144-20-philmd@linaro.org>
2026-01-22system: Allow restricting the legacy tswap() 'native-endian' APIPhilippe Mathieu-Daudé1-0/+3
Guard the native endian APIs we want to remove by surrounding them with TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API #ifdef'ry. Once a target gets cleaned we'll set the definition in the target config, then the target won't be able to use the legacy API anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260109165058.59144-19-philmd@linaro.org>
2026-01-22system: Allow restricting the legacy translator_ld() 'native-endian' APIPhilippe Mathieu-Daudé1-2/+3
Guard the native endian APIs we want to remove by surrounding them with TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API #ifdef'ry. Once a target gets cleaned we'll set the definition in the target config, then the target won't be able to use the legacy API anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260109165058.59144-18-philmd@linaro.org>
2026-01-12accel/tcg: Un-inline WatchPoint API user-emulation stubsPhilippe Mathieu-Daudé1-23/+0
Currently we can not build files including "exec/watchpoint.h" as meson common objects because the CONFIG_USER_ONLY definition is poisoned. We can easily fix that by un-inlining the user-emulation stubs. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20260106231908.16756-5-philmd@linaro.org>
2025-12-27include: reorganize memory API headersPaolo Bonzini4-160/+3
Move RAMBlock functions out of ram_addr.h and cpu-common.h; move memory API headers out of include/exec and into include/system. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-12-27include: move memory_ldst* to include/systemPaolo Bonzini3-322/+0
These partial headers are only included via system/memory.h, so keep them in the same directory. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-11-03exec/cpu: Declare cpu_memory_rw_debug() in 'hw/core/cpu.h' and documentPhilippe Mathieu-Daudé1-4/+0
cpu_memory_rw_debug() dispatches to CPUClass::memory_rw_debug(), move its declaration closer to the CPU API. Document. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20251001150529.14122-22-philmd@linaro.org>
2025-10-31accel/tcg: Introduce and use MO_ALIGN_TLB_ONLYRichard Henderson1-23/+20
For Arm, we need 3 cases: (1) the alignment required when accessing Normal memory, (2) the alignment required when accessing Device memory, and (3) the atomicity of the access. When we added TLB_CHECK_ALIGNED, we assumed that cases 2 and 3 were identical, and thus used memop_atomicity_bits for TLB_CHECK_ALIGNED. This is incorrect for multiple reasons, including that the atomicity of the access is adjusted depending on whether or not we are executing within a serial context. For Arm, what is true is that there is an underlying alignment requirement of the access, and for that access Normal memory will support unalignement. Introduce MO_ALIGN_TLB_ONLY to indicate that the alignment specified in MO_AMASK only applies when the TLB entry has TLB_CHECK_ALIGNED set; otherwise no alignment required. Introduce memop_tlb_alignment_bits with an additional bool argument that specifies whether TLB_CHECK_ALIGNED is set. All other usage of memop_alignment_bits assumes it is not. Remove memop_atomicity_bits as unused; it didn't properly support MO_ATOM_SUBWORD anyway. Update target/arm finalize_memop_atom to set MO_ALIGN_TLB_ONLY when strict alignment isn't otherwise required. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3171 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-10-14linux-user: Support MADV_DONTDUMP, MADV_DODUMPJon Wilson1-1/+5
Set and clear PAGE_DONTDUMP, and honor that in vma_dump_size. Signed-off-by: Jon Wilson <jonwilson030981@gmail.com> [rth: Use new page_set_flags semantics; also handle DODUMP] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-10-14accel/tcg: Add clear_flags argument to page_set_flagsRichard Henderson1-8/+5
Expand the interface of page_set_flags to separate the set of flags to be set and the set of flags to be cleared. This allows us to replace PAGE_RESET with the PAGE_VALID bit within clear_flags. Replace PAGE_TARGET_STICKY with TARGET_PAGE_NOTSTICKY; aarch64-linux-user is the only user. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-10-10include/exec/memopidx: Adjust for 32 mmu indexesRichard Henderson1-4/+5
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20251008215613.300150-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07system/physmem: Remove legacy cpu_physical_memory_rw()Philippe Mathieu-Daudé1-2/+0
The legacy cpu_physical_memory_rw() method is no more used, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-16-philmd@linaro.org>
2025-10-07system/physmem: Un-inline cpu_physical_memory_read/write()Philippe Mathieu-Daudé1-10/+2
In order to remove cpu_physical_memory_rw() in a pair of commits, and due to a cyclic dependency between "exec/cpu-common.h" and "system/memory.h", un-inline cpu_physical_memory_read() and cpu_physical_memory_write() as a prerequired step. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-14-philmd@linaro.org>
2025-10-07system/physmem: Pass address space argument to cpu_flush_icache_range()Philippe Mathieu-Daudé1-2/+0
Rename cpu_flush_icache_range() as address_space_flush_icache_range(), passing an address space by argument. The single caller, rom_reset(), already operates on an address space. Use it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-7-philmd@linaro.org>
2025-10-07system/physmem: Remove cpu_physical_memory_is_io()Philippe Mathieu-Daudé1-2/+0
There are no more uses of the legacy cpu_physical_memory_is_io() method. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20251002084203.63899-6-philmd@linaro.org>
2025-10-07system/ramblock: Move ram_block_discard_*_range() declarationsPhilippe Mathieu-Daudé1-3/+0
Keep RAM blocks API in the same header: "system/ramblock.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Message-Id: <20251002032812.26069-4-philmd@linaro.org>
2025-10-03physmem: Destroy all CPU AddressSpaces on unrealizePeter Maydell1-5/+5
When we unrealize a CPU object (which happens on vCPU hot-unplug), we should destroy all the AddressSpace objects we created via calls to cpu_address_space_init() when the CPU was realized. Commit 24bec42f3d6eae added a function to do this for a specific AddressSpace, but did not add any places where the function was called. Since we always want to destroy all the AddressSpaces on unrealize, regardless of the target architecture, we don't need to try to keep track of how many are still undestroyed, or make the target architecture code manually call a destroy function for each AS it created. Instead we can adjust the function to always completely destroy the whole cpu->ases array, and arrange for it to be called during CPU unrealize as part of the common code. Without this fix, AddressSanitizer will report a leak like this from a run where we hot-plugged and then hot-unplugged an x86 KVM vCPU: Direct leak of 416 byte(s) in 1 object(s) allocated from: #0 0x5b638565053d in calloc (/data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/qemu-system-x86_64+0x1ee153d) (BuildId: c1cd6022b195142106e1bffeca23498c2b752bca) #1 0x7c28083f77b1 in g_malloc0 (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x637b1) (BuildId: 1eb6131419edb83b2178b682829a6913cf682d75) #2 0x5b6386999c7c in cpu_address_space_init /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../system/physmem.c:797:25 #3 0x5b638727f049 in kvm_cpu_realizefn /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../target/i386/kvm/kvm-cpu.c:102:5 #4 0x5b6385745f40 in accel_cpu_common_realize /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../accel/accel-common.c:101:13 #5 0x5b638568fe3c in cpu_exec_realizefn /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../hw/core/cpu-common.c:232:10 #6 0x5b63874a2cd5 in x86_cpu_realizefn /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../target/i386/cpu.c:9321:5 #7 0x5b6387a0469a in device_set_realized /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../hw/core/qdev.c:494:13 #8 0x5b6387a27d9e in property_set_bool /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../qom/object.c:2375:5 #9 0x5b6387a2090b in object_property_set /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../qom/object.c:1450:5 #10 0x5b6387a35b05 in object_property_set_qobject /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../qom/qom-qobject.c:28:10 #11 0x5b6387a21739 in object_property_set_bool /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../qom/object.c:1520:15 #12 0x5b63879fe510 in qdev_realize /data_nvme1n1/linaro/qemu-from-laptop/qemu/build/x86-tgts-asan/../../hw/core/qdev.c:276:12 Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2517 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/r/20250929144228.1994037-4-peter.maydell@linaro.org Signed-off-by: Peter Xu <peterx@redhat.com>
2025-09-30monitor: Clean up HMP gdbserver error reportingMarkus Armbruster1-3/+0
HMP command gdbserver used to emit two error messages for certain errors. For instance, with -M none: (qemu) gdbserver gdbstub: meaningless to attach gdb to a machine without any CPU. Could not open gdbserver on device 'tcp::1234' The first message is the specific error, and the second one a generic additional message that feels superfluous to me. Commit c0e6b8b798b (system: propagate Error to gdbserver_start (and other device setups)) turned the first message into a warning: warning: gdbstub: meaningless to attach gdb to a machine without any CPU. Could not open gdbserver on device 'tcp::1234' This is arguably worse. hmp_gdbserver() passes &error_warn to gdbserver_start(), so that failure gets reported as warning, and then additionally emits the generic error on failure. This is a misuse of &error_warn. Instead, receive the error in &err and report it, as usual. With this, gdbserver reports just the error: gdbstub: meaningless to attach gdb to a machine without any CPU. Cc: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250923091000.3180122-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
2025-09-24accel/tcg: Remove cpu_loop_exit_restore() stubPhilippe Mathieu-Daudé1-1/+1
Not needed since commit 63e7af20352 ("hw/mips: Restrict ITU to TCG"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250924165039.52250-1-philmd@linaro.org>
2025-09-24accel/tcg: Create queue_tb_flush from tb_flushRichard Henderson1-11/+6
Rename the function and remove the path which performs the flush immediately. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-09-24accel/tcg: Split out tb_flush__exclusive_or_serialRichard Henderson1-0/+15
Expose a routine to be called when no cpus are running. Simplify the do_tb_flush run_on_cpu callback, because that is explicitly called with start_exclusive; there is no need for the mmap_lock as well. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-09-23include/hw/core/cpu: Introduce MMUIdxMapRichard Henderson1-16/+16
Use a typedef instead of uint16_t directly when describing sets of mmu indexes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-09-02include/exec/target_page.h: move page-target.c to headerPierrick Bouvier1-1/+10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250730220519.1140447-3-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-07-15qemu: Declare all load/store helper in 'qemu/bswap.h'Philippe Mathieu-Daudé1-70/+0
Restrict "exec/tswap.h" to the tswap*() methods, move the load/store helpers with the other ones declared in "qemu/bswap.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20250708215320.70426-8-philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-07-15qemu: Convert target_words_bigendian() to TargetInfo APIPhilippe Mathieu-Daudé1-12/+1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250708215320.70426-6-philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-07-15pci: Add a memory attribute for pre-translated DMA operationsCLEMENT MATHIEU--DRIF1-0/+3
The address_type bit will be set to PCI_AT_TRANSLATED by devices that use cached addresses obtained via ATS. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250628180226.133285-2-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-07-03physmem: qemu_ram_get_fd_offsetSteve Sistare1-0/+1
Define qemu_ram_get_fd_offset, so CPR can map a memory region using IOMMU_IOAS_MAP_FILE in a subsequent patch. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Link: https://lore.kernel.org/qemu-devel/1751493538-202042-8-git-send-email-steven.sistare@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-07-02gdbstub: Expose gdb_write_register function to consumers of gdbstubRowan Hart1-0/+14
This patch exposes the gdb_write_register function from gdbstub/gdbstub.c via the exec/gdbstub.h header file to support use in plugins to write register contents. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Julian Ganz <neither@nut.email> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Message-ID: <20250624175351.440780-2-rowanbhart@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250627112512.1880708-6-alex.bennee@linaro.org>
2025-06-07include/exec: fix assert in size_memopAlex Bennée1-2/+2
We can handle larger sized memops now, expand the range of the assert. Fixes: 4b473e0c60 (tcg: Expand MO_SIZE to 3 bits) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250603110204.838117-14-alex.bennee@linaro.org>
2025-05-14tcg: add vaddr type for helpersPierrick Bouvier1-0/+11
Defined as an alias of i32/i64 depending on host pointer size. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-13-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-09include/exec/cpu-common.h: fix "the the" typo in commentMichael Tokarev1-1/+1
Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2025-04-30include: Remove 'exec/exec-all.h'Philippe Mathieu-Daudé1-23/+0
"exec/exec-all.h" is now fully empty, let's remove it. Mechanical change running: $ sed -i '/exec\/exec-all.h/d' $(git grep -wl exec/exec-all.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-14-philmd@linaro.org>
2025-04-30accel/tcg: Extract probe API out of 'exec/exec-all.h'Philippe Mathieu-Daudé1-100/+0
Declare probe methods in "accel/tcg/probe.h" to emphasize they are specific to TCG accelerator. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-13-philmd@linaro.org>
2025-04-30physmem: Restrict TCG IOTLB code to TCG accelPhilippe Mathieu-Daudé1-26/+0
Restrict iotlb_to_section(), address_space_translate_for_iotlb() and memory_region_section_get_iotlb() to TCG. Declare them in the new "accel/tcg/iommu.h" header. Declare iotlb_to_section() using the MemoryRegionSection typedef. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-12-philmd@linaro.org>
2025-04-30accel/tcg: Include 'accel/tcg/getpc.h' in 'exec/helper-proto'Philippe Mathieu-Daudé2-1/+2
Most files including "exec/helper-proto.h" call GETPC(). Include it there (in the common part) instead of the unspecific "exec/exec-all.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-10-philmd@linaro.org>
2025-04-30include/exec: Move tb_invalidate_phys_range to translation-block.hRichard Henderson2-5/+4
Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30include/exec: Include missing headers in exec-all.hPhilippe Mathieu-Daudé1-0/+3
"exec/exec-all.h" declares prototypes such: void *probe_access(CPUArchState *env, vaddr addr, int size, ^^^^^ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, ^^^^^^ MemTxAttrs attrs); ^^^^^^^^^^ vaddr is defined in "exec/vaddr.h", hwaddr in "exec/hwaddr.h" and MemTxAttrs in "exec/memattrs.h". All these headers are indirectly pulled in via "exec/translation-block.h". Since we will remove "exec/translation-block.h" in the next commit, include the missing ones, otherwise we'd get errors such: include/exec/exec-all.h:51:1: error: unknown type name 'hwaddr' 51 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-5-philmd@linaro.org>
2025-04-30accel/tcg: Reduce scope of tb_phys_invalidate, tb_set_jmp_targetRichard Henderson1-2/+0
Move the declarations of these functions out of exec/exec-all.h to accel/tcg/internal-common.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smcRichard Henderson1-1/+0
Instead of having a compile-time TARGET_HAS_PRECISE_SMC definition, have each target set the 'precise_smc' field in the TCGCPUOps structure. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Add CPUState arg to tb_invalidate_phys_rangeRichard Henderson1-1/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-25system/memory: Remove DEVICE_HOST_ENDIAN definitionPhilippe Mathieu-Daudé1-6/+0
Since the previous commit ("exec/memory.h: make devend_memop "target defines" agnostic") there is a single use of the DEVICE_HOST_ENDIAN definition in ram_device_mem_ops: inline it and remove its definition altogether. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250423111625.10424-1-philmd@linaro.org>
2025-04-25exec: Rename target_words_bigendian() -> target_big_endian()Philippe Mathieu-Daudé1-6/+6
In commit 98ed8ecfc9d ("exec: introduce target_words_bigendian() helper") target_words_bigendian() was matching the definition it was depending on (TARGET_WORDS_BIGENDIAN). Later in commit ee3eb3a7ce7 ("Replace TARGET_WORDS_BIGENDIAN") the definition was renamed as TARGET_BIG_ENDIAN but we didn't update the helper. Do it now mechanically using: $ sed -i -e s/target_words_bigendian/target_big_endian/g \ $(git grep -wl target_words_bigendian) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20250417210025.68322-1-philmd@linaro.org>
2025-04-23tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported fieldPhilippe Mathieu-Daudé1-1/+0
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition, have each target set the 'mttcg_supported' field in the TCGCPUOps structure. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250405161320.76854-17-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2026-03-06 14:41:53 +0000