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5 dayshw/accel: add a per-accelerator callback to change VM accelerator handleAni Sinha1-0/+2
2026-02-02accel/tcg: Fix iotlb_to_section() for different AddressSpaceJim Shu1-15/+0
2026-01-22system: Allow restricting the legacy cpu_ld/st() 'native-endian' APIPhilippe Mathieu-Daudé1-0/+2
2026-01-17tcg: Unconditionally define atomic64 helpersRichard Henderson1-9/+0
2026-01-16accel: Introduce AccelOpsClass::cpu_target_realize() hookPhilippe Mathieu-Daudé1-0/+1
2026-01-12accel/tcg: Un-inline WatchPoint API user-emulation stubsPhilippe Mathieu-Daudé1-17/+0
2025-08-30accel/tcg: Add cpu_atomic_*_mmu for 16-byte xchg, fetch_and, fetch_orRichard Henderson1-3/+10
2025-07-15accel/system: Introduce @x-accel-stats QMP commandPhilippe Mathieu-Daudé2-0/+5
2025-07-15accel: Extract AccelClass definition to 'accel/accel-ops.h'Philippe Mathieu-Daudé1-0/+49
2025-07-15accel: Rename 'system/accel-ops.h' -> 'accel/accel-cpu-ops.h'Philippe Mathieu-Daudé1-0/+92
2025-05-28target: Use cpu_pointer_wrap_uint32 for 32-bit targetsRichard Henderson1-0/+1
2025-05-28target: Use cpu_pointer_wrap_notreached for strict align targetsRichard Henderson1-0/+5
2025-05-28accel/tcg: Add TCGCPUOps.pointer_wrapRichard Henderson1-0/+7
2025-05-05accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addrRichard Henderson1-0/+7
2025-05-05accel/tcg: Move tlb_vaddr_to_host declaration to probe.hRichard Henderson2-16/+16
2025-05-05accel/tcg: Move user-only tlb_vaddr_to_host out of lineRichard Henderson1-8/+0
2025-04-30accel/tcg: Split out accel/tcg/helper-retaddr.hRichard Henderson2-34/+43
2025-04-30accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOpsRichard Henderson1-2/+6
2025-04-30accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_stateRichard Henderson2-2/+20
2025-04-30accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.hRichard Henderson1-0/+3
2025-04-30accel/tcg: Introduce TCGCPUOps.cpu_exec_resetRichard Henderson1-0/+2
2025-04-30accel/tcg: Extract probe API out of 'exec/exec-all.h'Philippe Mathieu-Daudé1-0/+106
2025-04-30physmem: Restrict TCG IOTLB code to TCG accelPhilippe Mathieu-Daudé1-0/+41
2025-04-30accel/tcg: Remove #error for non-tcg in getpc.hRichard Henderson1-4/+0
2025-04-30accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smcRichard Henderson1-0/+7
2025-04-25accel: Make AccelCPUClass structure target-agnosticPhilippe Mathieu-Daudé2-11/+24
2025-04-23tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported fieldPhilippe Mathieu-Daudé1-0/+8
2025-04-23tcg: Define guest_default_memory_order in TCGCPUOpsPhilippe Mathieu-Daudé1-0/+8
2025-04-23exec: Restrict 'cpu_ldst.h' to accel/tcg/Philippe Mathieu-Daudé1-0/+563
2025-04-23exec: Restrict 'cpu-ldst-common.h' to accel/tcg/Philippe Mathieu-Daudé1-0/+122
2025-04-23hw/core/cpu: Remove CPUClass::mmu_index()Philippe Mathieu-Daudé1-3/+1
2025-04-23accel/tcg: Introduce TCGCPUOps::mmu_index() callbackPhilippe Mathieu-Daudé2-1/+7
2025-04-23include/exec: Split out accel/tcg/cpu-mmu-index.hRichard Henderson1-0/+41
2025-03-09cpus: Introduce SysemuCPUOps::has_work() handlerPhilippe Mathieu-Daudé1-1/+1
2025-03-08accel/tcg: Split out getpc.hRichard Henderson1-0/+24
2025-03-06accel/accel-cpu-target.h: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé1-0/+3
2025-03-06accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h'Philippe Mathieu-Daudé1-0/+38
2025-03-06accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h'Philippe Mathieu-Daudé1-0/+278