aboutsummaryrefslogtreecommitdiff
path: root/hw/i386/intel_iommu_internal.h
AgeCommit message (Expand)AuthorFilesLines
2025-07-15intel_iommu: Declare supported PASID sizeCLEMENT MATHIEU--DRIF1-0/+1
2025-01-15intel_iommu: Introduce a property x-flts for stage-1 translationZhenzhong Duan1-0/+2
2025-01-15intel_iommu: Add support for PASID-based device IOTLB invalidationClément Mathieu--Drif1-0/+11
2025-01-15intel_iommu: Process PASID-based iotlb invalidationZhenzhong Duan1-0/+3
2025-01-15intel_iommu: Set accessed and dirty bits during stage-1 translationClément Mathieu--Drif1-0/+3
2025-01-15intel_iommu: Check if the input address is canonicalClément Mathieu--Drif1-0/+1
2025-01-15intel_iommu: Implement stage-1 translationYi Liu1-0/+34
2025-01-15intel_iommu: Rename slpte to pteYi Liu1-12/+12
2025-01-15intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalid...Zhenzhong Duan1-5/+9
2025-01-15intel_iommu: Use the latest fault reasons defined by specYu Zhang1-1/+8
2024-11-04intel_iommu: Add missed reserved bit check for IEC descriptorZhenzhong Duan1-0/+3
2024-11-04intel_iommu: Add missed sanity check for 256-bit invalidation queueZhenzhong Duan1-0/+1
2024-11-04intel_iommu: Introduce property "stale-tm" to control Transient Mapping (TM) ...Zhenzhong Duan1-6/+6
2024-09-11intel_iommu: Fix invalidation descriptor type fieldZhenzhong Duan1-5/+6
2024-07-21intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfoClément Mathieu--Drif1-1/+1
2024-07-21intel_iommu: move VTD_FRCD_PV and VTD_FRCD_PP declarationsClément Mathieu--Drif1-2/+2
2024-07-21intel_iommu: fix FRCD construction macroClément Mathieu--Drif1-1/+1
2023-10-22intel-iommu: Report interrupt remapping faults, fix return valueDavid Woodhouse1-0/+1
2023-08-03hw/i386/intel_iommu: Fix struct VTDInvDescIEC on big endian hostsThomas Huth1-0/+9
2023-04-24intel_iommu: refine iotlb hash calculationJason Wang1-3/+3
2022-11-07intel-iommu: PASID supportJason Wang1-2/+14
2022-05-16intel-iommu: block output address in interrupt address rangeJason Wang1-0/+4
2022-05-16intel-iommu: remove VTD_FR_RESERVED_ERRJason Wang1-5/+0
2022-03-06intel_iommu: support snoop controlJason Wang1-0/+1
2021-11-29intel-iommu: ignore leaf SNP bit in scalable modeJason Wang1-0/+2
2020-07-22intel_iommu: Use correct shift for 256 bits qi descriptorLiu Yi L1-1/+2
2020-01-06intel_iommu: add present bit check for pasid table entriesLiu Yi L1-0/+1
2019-11-25intel_iommu: TM field should not be in reserved bitsQi, Yadong1-3/+10
2019-11-25intel_iommu: refine SL-PEs reserved fields checkingQi, Yadong1-4/+1
2019-04-02intel_iommu: Drop extended root fieldPeter Xu1-1/+0
2019-03-12intel_iommu: add scalable-mode option to make scalable mode workYi Sun1-0/+4
2019-03-12intel_iommu: add 256 bits qi_desc supportLiu, Yi L1-1/+8
2019-03-12intel_iommu: scalable mode emulationLiu, Yi L1-2/+39
2018-12-19intel_iommu: dma read/write draining supportPeter Xu1-0/+3
2018-01-18intel-iommu: Extend address width to 48 bitsPrasad Singamsetty1-6/+3
2018-01-18intel-iommu: Redefine macros to enable supporting 48 bit address widthPrasad Singamsetty1-8/+26
2017-08-02intel_iommu: fix iova for ptPeter Xu1-1/+0
2017-06-16intel_iommu: cleanup vtd_{do_}iommu_translate()Peter Xu1-0/+1
2017-05-25intel_iommu: support passthrough (PT)Peter Xu1-0/+1
2017-04-20intel_iommu: enable remote IOTLBPeter Xu1-0/+1
2017-02-17intel_iommu: add "caching-mode" optionAviv Ben-David1-0/+1
2017-01-10intel_iommu: support device iotlb descriptorJason Wang1-2/+11
2016-11-15intel_iommu: fixing source id during IOTLB hash key calculationJason Wang1-1/+1
2016-07-21intel_iommu: support all masks in interrupt entry cache invalidationRadim Krčmář1-0/+1
2016-07-21intel_iommu: Add support for Extended Interrupt ModeJan Kiszka1-0/+2
2016-07-21x86-iommu: introduce IEC notifiersPeter Xu1-4/+20
2016-07-20intel_iommu: Add support for PCI MSI remapPeter Xu1-0/+2
2016-07-20intel_iommu: add IR translation faults definesPeter Xu1-0/+13
2016-07-20intel_iommu: define interrupt remap table addr registerPeter Xu1-0/+4
2016-07-20intel_iommu: set IR bit for ECAP registerPeter Xu1-0/+2
generated by cgit v1.1 at 2025-08-03 21:59:21 +0000