rocket-tools/riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2025-07-15	accel: Extract AccelClass definition to 'accel/accel-ops.h'	Philippe Mathieu-Daudé	1	-0/+1
2025-07-04	accel: Propagate AccelState to AccelClass::init_machine()	Philippe Mathieu-Daudé	1	-1/+1
2025-05-08	bsd-user: add option to enable plugins	Pierrick Bouvier	1	-0/+12
2025-05-05	include/user: Convert GUEST_ADDR_MAX to a variable	Richard Henderson	1	-0/+8
2025-05-05	accel/tcg: Use vaddr in cpu_loop.h	Richard Henderson	1	-2/+2
2025-04-30	include: Remove 'exec/exec-all.h'	Philippe Mathieu-Daudé	2	-2/+0
2025-04-24	Merge tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru into staging	Stefan Hajnoczi	1	-1/+0
2025-04-24	cleanup: Drop pointless return at end of function	Markus Armbruster	1	-1/+0
2025-04-23	exec: Restrict 'cpu_ldst.h' to accel/tcg/	Philippe Mathieu-Daudé	1	-1/+1
2025-04-23	include/exec: Split out mmap-lock.h	Richard Henderson	2	-0/+2
2025-03-21	exec/cpu-all: remove BSWAP_NEEDED	Pierrick Bouvier	1	-3/+3
2025-03-10	plugins/api: split out binary path/start/end/entry code	Alex Bennée	2	-0/+16
2025-03-09	user: Prefer cached CpuClass over CPU_GET_CLASS() macro	Philippe Mathieu-Daudé	1	-2/+2
2025-03-09	user: Extract common MMAP API to 'user/mmap.h'	Philippe Mathieu-Daudé	1	-11/+1
2025-03-09	bsd-user: Propagate alignment argument to mmap_find_vma()	Philippe Mathieu-Daudé	3	-10/+6
2025-03-09	bsd-user: Always use mmap_find_vma_aligned() in target_mmap()	Philippe Mathieu-Daudé	1	-5/+4
2025-03-06	accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h'	Philippe Mathieu-Daudé	1	-1/+1
2025-03-06	qemu/compiler: Absorb 'clang-tsa.h'	Philippe Mathieu-Daudé	1	-1/+0
2025-02-10	gdbstub: Allow late attachment	Ilya Leoshkevich	1	-1/+0
2025-02-10	user: Introduce host_interrupt_signal	Ilya Leoshkevich	1	-0/+12
2025-02-10	user: Introduce user/signal.h	Ilya Leoshkevich	2	-1/+1
2025-01-17	system: propagate Error to gdbserver_start (and other device setups)	Alex Bennée	1	-1/+1
2024-12-20	user: Move various declarations out of 'exec/exec-all.h'	Philippe Mathieu-Daudé	1	-0/+1
2024-12-20	user: Declare cpu_loop() once in 'user/cpu_loop.h'	Philippe Mathieu-Daudé	6	-6/+6
2024-12-20	accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (4/4)	Philippe Mathieu-Daudé	1	-0/+1
2024-12-20	accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (3/4)	Philippe Mathieu-Daudé	1	-0/+1
2024-12-20	accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (2/4)	Philippe Mathieu-Daudé	1	-0/+1
2024-12-20	accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (1/4)	Philippe Mathieu-Daudé	2	-0/+2
2024-11-04	bsd-user: Set TaskState ts_tid for initial threads	Jessica Clarke	1	-0/+1
2024-11-04	bsd-user/main: Allow setting tb-size	Ilya Leoshkevich	1	-0/+9
2024-11-04	bsd-user/x86_64/target_arch_thread.h: Align stack	Ilya Leoshkevich	1	-1/+1
2024-10-02	bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV	Mark Corbin	1	-0/+54
2024-10-02	bsd-user: Implement 'get_mcontext' for RISC-V	Mark Corbin	1	-0/+53
2024-10-02	bsd-user: Implement RISC-V signal trampoline setup functions	Mark Corbin	1	-0/+63
2024-10-02	bsd-user: Define RISC-V signal handling structures and constants	Mark Corbin	1	-0/+75
2024-10-02	bsd-user: Add generic RISC-V64 target definitions	Warner Losh	1	-0/+20
2024-10-02	bsd-user: Define RISC-V system call structures and constants	Mark Corbin	1	-0/+38
2024-10-02	bsd-user: Define RISC-V VM parameters and helper functions	Mark Corbin	1	-0/+53
2024-10-02	bsd-user: Add RISC-V thread setup and initialization support	Mark Corbin	1	-0/+47
2024-10-02	bsd-user: Implement RISC-V sysarch system call emulation	Mark Corbin	1	-0/+41
2024-10-02	bsd-user: Add RISC-V signal trampoline setup function	Mark Corbin	1	-0/+41
2024-10-02	bsd-user: Define RISC-V register structures and register copying	Mark Corbin	1	-0/+88
2024-10-02	bsd-user: Add RISC-V ELF definitions and hardware capability detection	Mark Corbin	1	-0/+42
2024-10-02	bsd-user: Implement RISC-V TLS register setup	Mark Corbin	2	-0/+56
2024-10-02	bsd-user: Implement RISC-V CPU register cloning and reset functions	Mark Corbin	1	-0/+14
2024-10-02	bsd-user: Add RISC-V CPU execution loop and syscall handling	Mark Corbin	1	-0/+94
2024-10-02	bsd-user: Implement RISC-V CPU initialization and main loop	Mark Corbin	1	-0/+40
2024-08-21	bsd-user: Handle short reads in mmap_h_gt_g	Richard Henderson	1	-2/+36
2024-07-24	bsd-user: Add target.h for aarch64.	Warner Losh	1	-0/+20
2024-07-23	bsd-user: Define TARGET_SIGSTACK_ALIGN and use it to round stack	Warner Losh	5	-8/+9