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2025-08-30linux-user: Move elf_core_copy_regs to openrisc/elfload.cRichard Henderson3-16/+22
Move elf_core_copy_regs to elfload.c. Move HAVE_ELF_CORE_DUMP, ELF_NREGS, target_elf_gregset_t to target_elf.h. For now, duplicate the definitions of target_elf_greg_t and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Move elf_core_copy_regs to microblaze/elfload.cRichard Henderson3-21/+26
Move elf_core_copy_regs to elfload.c. Move HAVE_ELF_CORE_DUMP, ELF_NREGS, target_elf_gregset_t to target_elf.h. For now, duplicate the definitions of target_elf_greg_t and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Move elf_core_copy_regs to mips/elfload.cRichard Henderson4-46/+68
Move elf_core_copy_regs to elfload.c. Move HAVE_ELF_CORE_DUMP, ELF_NREGS, target_elf_gregset_t to target_elf.h. For now, duplicate the definitions of target_elf_greg_t and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Move elf_core_copy_regs to loongarch64/elfload.cRichard Henderson3-25/+30
Move elf_core_copy_regs to elfload.c. Move HAVE_ELF_CORE_DUMP, ELF_NREGS, target_elf_gregset_t to target_elf.h. For now, duplicate the definitions of target_elf_greg_t and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Move elf_core_copy_regs to ppc/elfload.cRichard Henderson3-26/+31
Move elf_core_copy_regs to elfload.c. Move HAVE_ELF_CORE_DUMP, ELF_NREGS, target_elf_gregset_t to target_elf.h. For now, duplicate the definitions of target_elf_greg_t and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Move elf_core_copy_regs to aarch64/elfload.cRichard Henderson3-15/+20
Move elf_core_copy_regs to elfload.c. Move HAVE_ELF_CORE_DUMP, ELF_NREGS, target_elf_gregset_t to target_elf.h. For now, duplicate the definitions of target_elf_greg_t and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Move elf_core_copy_regs to arm/elfload.cRichard Henderson3-15/+20
Move elf_core_copy_regs to elfload.c. Move HAVE_ELF_CORE_DUMP, ELF_NREGS, target_elf_gregset_t to target_elf.h. For now, duplicate the definitions of target_elf_greg_t and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Move elf_core_copy_regs to {i386,x86_64}/elfload.cRichard Henderson5-77/+88
Move elf_core_copy_regs to elfload.c. Move HAVE_ELF_CORE_DUMP, ELF_NREGS, target_elf_gregset_t to target_elf.h. For now, duplicate the definitions of target_elf_greg_t and tswapreg. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Rename USE_ELF_CORE_DUMP to HAVE_ELF_CORE_DUMPRichard Henderson1-19/+19
The other knobs in target_elf.h are all HAVE_*. Rename this USE_ELF_CORE_DUMP to match. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Declare elf_core_copy_regs in loader.hRichard Henderson2-19/+17
Drop the static from all implementations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Update comment for target_elf_gregset_tRichard Henderson1-6/+2
The only thing now used by generic core dump code is target_elf_gregset_t; ELF_NREG and target_elf_greg_t are now private to the implementation. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/xtensa: Convert target_elf_gregset_t to a structRichard Henderson1-12/+14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/s390x: Convert target_elf_gregset_t to a structRichard Henderson1-7/+9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/m68k: Convert target_elf_gregset_t to a structRichard Henderson1-23/+25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/sh4: Convert target_elf_gregset_t to a structRichard Henderson1-14/+13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/openrisc: Convert target_elf_gregset_t to a structRichard Henderson1-8/+8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/microblaze: Convert target_elf_gregset_t to a structRichard Henderson1-12/+12
While we're at it, drop "pos++" and simply open-code indexes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/mips: Convert target_elf_gregset_t to a structRichard Henderson1-15/+15
While we're at it, merge the store of TARGET_EF_R0 into the loop over all R0 registers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/loongarch64: Convert target_elf_gregset_t to a structRichard Henderson1-9/+9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/ppc: Convert target_elf_gregset_t to a structRichard Henderson1-9/+11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/aarch64: Convert target_elf_gregset_t to a structRichard Henderson1-9/+8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/arm: Convert target_elf_gregset_t to a structRichard Henderson1-22/+10
While we're at it, loop over the general registers rather than open-code them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/i386: Convert target_elf_gregset_t to a structRichard Henderson1-20/+22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user/x86_64: Convert target_elf_gregset_t to a structRichard Henderson1-30/+32
A structure typedef may be abstract, while an array typedef cannot. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30linux-user: Drop deprecated -p optionPeter Maydell5-33/+8
The user-mode '-p' option has been deprecated since 9.0 and doesn't do anything except emit a warning. We are well past our minimum deprecation period, so drop the option. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250828162012.3307647-1-peter.maydell@linaro.org>
2025-08-30linux-user: Tidy print_socket_protocolRichard Henderson1-47/+49
Sink all of the qemu_log calls to the end, collecting only a string for the name, if identified. Merge separate if blocks into one switch. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30hw/core: Use qemu_log_trylock/unlock in cpu_common_reset_exitRichard Henderson1-3/+8
Ensure that the "CPU Reset" message won't be separated from the cpu_dump_state output. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30hw/core: Dump cpu_reset in the reset.exit phaseRichard Henderson1-5/+11
During reset.hold, the cpu is in an inconsistent state, where the leaf class has not had a chance to initialize state at all. This is visible as a SIGSEGV in "qemu-system-sparc64 -d cpu_reset". Move the dump to the exit phase, where all initialization is certain to be complete. Reported-by: Henk van der Laak <henk@laaksoft.nl> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-29tcg: move interrupt caching and single step masking closer to userIgor Mammedov1-9/+6
in cpu_handle_interrupt() the only place where cached interrupt_request might have effect is when CPU_INTERRUPT_SSTEP_MASK applied and cached interrupt_request handed over to cpu_exec_interrupt() and need_replay_interrupt(). Simplify code by moving interrupt_request caching and CPU_INTERRUPT_SSTEP_MASK masking into the block where it actually matters and drop reloading cached value from CPUState:interrupt_request as the rest of the code directly uses CPUState:interrupt_request. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Link: https://lore.kernel.org/r/20250814160600.2327672-9-imammedo@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29kvm: i386: irqchip: take BQL only if there is an interruptIgor Mammedov1-7/+5
when kernel-irqchip=split is used, QEMU still hits BQL contention issue when reading ACPI PM/HPET timers (despite of timer[s] access being lock-less). So Windows with more than 255 cpus is still not able to boot (since it requires iommu -> split irqchip). Problematic path is in kvm_arch_pre_run() where BQL is taken unconditionally when split irqchip is in use. There are a few parts that BQL protects there: 1. interrupt check and injecting however we do not take BQL when checking for pending interrupt (even within the same function), so the patch takes the same approach for cpu->interrupt_request checks and takes BQL only if there is a job to do. 2. request_interrupt_window access CPUState::kvm_run::request_interrupt_window doesn't need BQL as it's accessed by its own vCPU thread. 3. cr8/cpu_get_apic_tpr access the same (as #2) applies to CPUState::kvm_run::cr8, and APIC registers are also cached/synced (get/put) within the vCPU thread it belongs to. Taking BQL only when is necessary, eleminates BQL bottleneck on IO/MMIO only exit path, improoving latency by 80% on HPET micro benchmark. This lets Windows to boot succesfully (in case hv-time isn't used) when more than 255 vCPUs are in use. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20250814160600.2327672-8-imammedo@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hpet: make main counter read lock-lessIgor Mammedov1-6/+20
Make access to main HPET counter lock-less. In unlikely event of an update in progress, readers will busy wait untill update is finished. As result micro benchmark of concurrent reading of HPET counter with large number of vCPU shows over 80% better (less) latency. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20250814160600.2327672-6-imammedo@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hpet: move out main counter read into a separate blockIgor Mammedov1-8/+10
Follow up patche will switch main counter read to lock-less mode. As preparation for that move relevant branch into a separate top level block to make followup patch cleaner/simplier by reducing contextual noise when lock-less read is introduced. no functional changes. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20250814160600.2327672-5-imammedo@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hpet: switch to fine-grained device lockingIgor Mammedov1-0/+6
as a step towards lock-less HPET counter read, use per device locking instead of BQL. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20250814160600.2327672-4-imammedo@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29acpi: mark PMTIMER as unlockedIgor Mammedov1-0/+1
Reading QEMU_CLOCK_VIRTUAL is thread-safe, write access is NOP. This makes possible to boot Windows with large vCPUs count when hv-time is not used. Reproducer: -M q35,hpet=off -cpu host -enable-kvm -smp 240,sockets=4 -m 8G WS2025.img fails to boot within 30min. With this fix it boots within 2-1min. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Link: https://lore.kernel.org/r/20250814160600.2327672-3-imammedo@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29memory: reintroduce BQL-free fine-grained PIO/MMIOIgor Mammedov3-1/+28
This patch brings back Jan's idea [1] of BQL-free IO access This will let us make access to ACPI PM/HPET timers cheaper, and prevent BQL contention in case of workload that heavily uses the timers with a lot of vCPUs. 1) 196ea13104f (memory: Add global-locking property to memory regions) ... de7ea885c539 (kvm: Switch to unlocked MMIO) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20250814160600.2327672-2-imammedo@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wideIgor Mammedov34-119/+145
The helpers form load-acquire/store-release pair and ensure that appropriate barriers are in place in case checks happen outside of BQL. Use them to replace open-coded checkers/setters across the code, to make sure that barriers are not missed. Helpers also make code a bit more readable. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Jason J. Herne <jjherne@linux.ibm.com> Link: https://lore.kernel.org/r/20250821155603.2422553-1-imammedo@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29user-exec: ensure interrupt_request is not usedPaolo Bonzini3-5/+6
cpu_interrupt() is not called anymore except by ARM but even there it is dead code; disentangling the various cpregs accessors from user-mode emulation is a work in progress. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/isapc.c: replace rom_memory with system_memoryMark Cave-Ayland1-2/+1
Now that we can guarantee the isapc machine will never have a PCI bus, any instances of rom_memory can be replaced by system_memory and rom_memory removed completely. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-20-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: replace rom_memory with pci_memoryMark Cave-Ayland1-3/+1
Now that we can guarantee the i440fx-pc machine will always have a PCI bus, any instances of rom_memory can be replaced by pci_memory and rom_memory removed completely. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-19-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: remove unused headers after isapc machine splitMark Cave-Ayland1-3/+0
The headers for isapc-only devices can be removed from pc_piix.c since they are no longer used by the i440fx-pc machine. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-18-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386: move isapc machine to separate isapc.c fileMark Cave-Ayland4-175/+191
Now that pc_init_isa() is independent of any PCI initialisation, move it into a separate isapc.c file including the ISA IDE variables which are now no longer needed for the pc-i440fx machine. This enables us to finally fix the dependency of ISAPC on I440FX in hw/i386/Kconfig. Note that as part of the move to a separate file we can see that the licence text is a verbatim copy of the MIT licence. The text originates from commit 1df912cf9e ("VL license of the day is MIT/BSD") so we can be sure that this was the original intent. As a consequence we can update the file header to use a SPDX tag as per the current project contribution guidelines. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-17-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: assume pcmc->pci_enabled is always true in pc_init1()Mark Cave-Ayland1-117/+77
PCI is always enabled on the pc-i440fx machine so hardcode the relevant logic in pc_init1(). Add an assert() to ensure that this is always the case at runtime as already done in pc_q35_init(). Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-16-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: always initialise ISA IDE drives in pc_init_isa()Mark Cave-Ayland1-20/+15
By definition an isapc machine must always use ISA IDE drives so ensure that they are always enabled. At the same time also remove the surrounding CONFIG_IDE_ISA define since it will be enabled via the ISAPC Kconfig. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-15-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: remove pc_system_flash_cleanup_unused() from pc_init_isa()Mark Cave-Ayland1-1/+0
This function contains 'assert(PC_MACHINE_GET_CLASS(pcms)->pci_enabled)' and so we can safely assume that it should never be used for the isapc machine. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20250828111057.468712-14-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: hardcode hole64_size to 0 in pc_init_isa()Mark Cave-Ayland1-2/+1
All isapc machines must have 32-bit CPUs and have no PCI 64-bit hole so it can be hardcoded to 0. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-13-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: simplify RAM size logic in pc_init_isa()Mark Cave-Ayland1-54/+4
All isapc machines must have 32-bit CPUs and so the RAM split logic can be hardcoded accordingly. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20250828111057.468712-12-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: remove nvdimm initialisation from pc_init_isa()Mark Cave-Ayland1-6/+0
NVDIMMs cannot be used by PCs from a pre-PCI era. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-11-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: remove SGX initialisation from pc_init_isa()Mark Cave-Ayland1-1/+0
The Intel SGX instructions only exist on recent CPUs and so would never be available on a CPU from the pre-PCI era. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-10-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: remove SMI and piix4_pm initialisation from pc_init_isa()Mark Cave-Ayland1-19/+0
These are based upon the PIIX4 PCI chipset and so can never be used on an isapc machine. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250828111057.468712-9-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29hw/i386/pc_piix.c: remove igvm initialisation from pc_init_isa()Mark Cave-Ayland1-10/+0
According to the QEMU documentation igvm is only supported for the pc and q35 machines so remove igvm support from the isapc machine. Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Link: https://lore.kernel.org/r/20250828111057.468712-8-mark.caveayland@nutanix.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-09-18 12:36:49 +0000