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-rw-r--r--target/arm/cpregs-pmu.c29
-rw-r--r--target/arm/debug_helper.c29
-rw-r--r--target/arm/gdbstub64.c35
-rw-r--r--target/i386/cpu.c3
4 files changed, 82 insertions, 14 deletions
diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c
index 0f295b1..9c4431c 100644
--- a/target/arm/cpregs-pmu.c
+++ b/target/arm/cpregs-pmu.c
@@ -1067,11 +1067,6 @@ static const ARMCPRegInfo v7_pm_reginfo[] = {
.fgt = FGT_PMSELR_EL0,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
.writefn = pmselr_write, .raw_writefn = raw_write, },
- { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
- .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
- .fgt = FGT_PMCCNTR_EL0,
- .readfn = pmccntr_read, .writefn = pmccntr_write32,
- .accessfn = pmreg_access_ccntr },
{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
.access = PL0_RW, .accessfn = pmreg_access_ccntr,
@@ -1211,6 +1206,23 @@ void define_pm_cpregs(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, &pmcr);
define_one_arm_cp_reg(cpu, &pmcr64);
define_arm_cp_regs(cpu, v7_pm_reginfo);
+ /*
+ * 32-bit AArch32 PMCCNTR. We don't expose this to GDB if the
+ * new-in-v8 PMUv3 64-bit AArch32 PMCCNTR register is implemented
+ * (as that will provide the GDB user's view of "PMCCNTR").
+ */
+ ARMCPRegInfo pmccntr = {
+ .name = "PMCCNTR",
+ .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
+ .access = PL0_RW, .accessfn = pmreg_access_ccntr,
+ .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
+ .fgt = FGT_PMCCNTR_EL0,
+ .readfn = pmccntr_read, .writefn = pmccntr_write32,
+ };
+ if (arm_feature(env, ARM_FEATURE_V8)) {
+ pmccntr.type |= ARM_CP_NO_GDB;
+ }
+ define_one_arm_cp_reg(cpu, &pmccntr);
for (unsigned i = 0, pmcrn = pmu_num_counters(env); i < pmcrn; i++) {
g_autofree char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
@@ -1276,6 +1288,13 @@ void define_pm_cpregs(ARMCPU *cpu)
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
.fgt = FGT_PMCEIDN_EL0,
.resetvalue = cpu->pmceid1 },
+ /* AArch32 64-bit PMCCNTR view: added in PMUv3 with Armv8 */
+ { .name = "PMCCNTR", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .crm = 9, .opc1 = 0,
+ .access = PL0_RW, .accessfn = pmreg_access_ccntr, .resetvalue = 0,
+ .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_64BIT,
+ .fgt = FGT_PMCCNTR_EL0, .readfn = pmccntr_read,
+ .writefn = pmccntr_write, },
};
define_arm_cp_regs(cpu, v8_pm_reginfo);
}
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index aee06d4..579516e 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -940,6 +940,13 @@ static void dbgclaimclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
env->cp15.dbgclaim &= ~(value & 0xFF);
}
+static CPAccessResult access_bogus(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ /* Always UNDEF, as if this cpreg didn't exist */
+ return CP_ACCESS_UNDEFINED;
+}
+
static const ARMCPRegInfo debug_cp_reginfo[] = {
/*
* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
@@ -1003,6 +1010,28 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.access = PL0_RW, .accessfn = access_tdcc,
.type = ARM_CP_CONST, .resetvalue = 0 },
/*
+ * This is not a real AArch32 register. We used to incorrectly expose
+ * this due to a QEMU bug; to avoid breaking migration compatibility we
+ * need to continue to provide it so that we don't fail the inbound
+ * migration when it tells us about a sysreg that we don't have.
+ * We set an always-fails .accessfn, which means that the guest doesn't
+ * actually see this register (it will always UNDEF, identically to if
+ * there were no cpreg definition for it other than that we won't print
+ * a LOG_UNIMP message about it), and we set the ARM_CP_NO_GDB flag so the
+ * gdbstub won't see it either.
+ * (We can't just set .access = 0, because add_cpreg_to_hashtable()
+ * helpfully ignores cpregs which aren't accessible to the highest
+ * implemented EL.)
+ *
+ * TODO: implement a system for being able to describe "this register
+ * can be ignored if it appears in the inbound stream"; then we can
+ * remove this temporary hack.
+ */
+ { .name = "BOGUS_DBGDTR_EL0", .state = ARM_CP_STATE_AA32,
+ .cp = 14, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0,
+ .access = PL0_RW, .accessfn = access_bogus,
+ .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
+ /*
* OSECCR_EL1 provides a mechanism for an operating system
* to access the contents of EDECCR. EDECCR is not implemented though,
* as is the rest of external device mechanism.
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 64ee9b3..08e2858 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -115,8 +115,22 @@ int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg)
/* 128 bit FP register */
{
uint64_t *q = aa64_vfp_qreg(env, reg);
- q[0] = ldq_le_p(buf);
- q[1] = ldq_le_p(buf + 8);
+
+ /*
+ * On the wire these are target-endian 128 bit values.
+ * In the CPU state these are host-order uint64_t values
+ * with the least-significant one first. This means they're
+ * the other way around for target_big_endian() (which is
+ * only true for us for aarch64_be-linux-user).
+ */
+ if (target_big_endian()) {
+ q[1] = ldq_p(buf);
+ q[0] = ldq_p(buf + 8);
+ } else{
+ q[0] = ldq_p(buf);
+ q[1] = ldq_p(buf + 8);
+ }
+
return 16;
}
case 32:
@@ -192,10 +206,17 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg)
case 0 ... 31:
{
int vq, len = 0;
- uint64_t *p = (uint64_t *) buf;
for (vq = 0; vq < cpu->sve_max_vq; vq++) {
- env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
- env->vfp.zregs[reg].d[vq * 2] = *p++;
+ if (target_big_endian()) {
+ env->vfp.zregs[reg].d[vq * 2 + 1] = ldq_p(buf);
+ buf += 8;
+ env->vfp.zregs[reg].d[vq * 2] = ldq_p(buf);
+ } else{
+ env->vfp.zregs[reg].d[vq * 2] = ldq_p(buf);
+ buf += 8;
+ env->vfp.zregs[reg].d[vq * 2 + 1] = ldq_p(buf);
+ }
+ buf += 8;
len += 16;
}
return len;
@@ -210,9 +231,9 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg)
{
int preg = reg - 34;
int vq, len = 0;
- uint64_t *p = (uint64_t *) buf;
for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
- env->vfp.pregs[preg].p[vq / 4] = *p++;
+ env->vfp.pregs[preg].p[vq / 4] = ldq_p(buf);
+ buf += 8;
len += 8;
}
return len;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 251d576..673f858 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7885,8 +7885,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
* count, but Intel needs maximum number of addressable IDs for
* logical processors per package.
*/
- if (cpu->vendor_cpuid_only_v2 &&
- (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) {
+ if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) {
num = 1 << apicid_pkg_offset(topo_info);
} else {
num = threads_per_pkg;
generated by cgit v1.1 at 2025-08-07 17:44:05 +0000