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-rw-r--r--target/mips/cpu-defs.c.inc10
-rw-r--r--target/mips/helper.h2
-rw-r--r--target/mips/meson.build1
-rw-r--r--target/mips/system/mips-qmp-cmds.c3
-rw-r--r--target/mips/tcg/micromips_translate.c.inc2
-rw-r--r--target/mips/tcg/msa_translate.c4
-rw-r--r--target/mips/tcg/nanomips_translate.c.inc7
-rw-r--r--target/mips/tcg/octeon.decode8
-rw-r--r--target/mips/tcg/octeon_translate.c12
-rw-r--r--target/mips/tcg/op_helper.c26
-rw-r--r--target/mips/tcg/rel6.decode5
-rw-r--r--target/mips/tcg/rel6_translate.c16
-rw-r--r--target/mips/tcg/translate.c102
-rw-r--r--target/mips/tcg/translate.h4
-rw-r--r--target/mips/tcg/translate_addr_const.c4
15 files changed, 139 insertions, 67 deletions
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 922fc39..d93b9d3 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -756,8 +756,9 @@ const mips_def_t mips_defs[] =
(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
(1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
- (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_XNP) |
+ (1 << CP0C5_VP) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP) |
+ (3 << CP0C5_GI),
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
.CP0_LLAddr_rw_bitmask = 0,
@@ -796,8 +797,9 @@ const mips_def_t mips_defs[] =
(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
(1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
- (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_XNP) |
+ (1 << CP0C5_VP) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP) |
+ (3 << CP0C5_GI),
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
.CP0_LLAddr_rw_bitmask = 0,
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 7e40041..b6cd53c 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -21,6 +21,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
#endif
+DEF_HELPER_3(crc32, tl, tl, tl, i32)
+DEF_HELPER_3(crc32c, tl, tl, tl, i32)
DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
/* microMIPS functions */
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 247979a..abf0ce3 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -7,6 +7,7 @@ mips_ss.add(files(
'gdbstub.c',
'msa.c',
))
+mips_ss.add(zlib)
if have_system
subdir('system')
diff --git a/target/mips/system/mips-qmp-cmds.c b/target/mips/system/mips-qmp-cmds.c
index d98d662..b6a2874 100644
--- a/target/mips/system/mips-qmp-cmds.c
+++ b/target/mips/system/mips-qmp-cmds.c
@@ -7,6 +7,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/target-info.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-machine.h"
#include "cpu.h"
@@ -40,7 +41,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
CpuDefinitionInfoList *cpu_list = NULL;
GSList *list;
- list = object_class_get_list(TYPE_MIPS_CPU, false);
+ list = object_class_get_list(target_cpu_type(), false);
g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
g_slist_free(list);
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index c479bec..8fda7c8 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -1795,7 +1795,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
return;
case LSA:
check_insn(ctx, ISA_MIPS_R6);
- gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
+ gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1);
break;
case ALIGN:
check_insn(ctx, ISA_MIPS_R6);
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 75cf80a..82b1499 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -780,7 +780,7 @@ TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);
static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
- return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+ return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}
static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@@ -788,5 +788,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
if (TARGET_LONG_BITS != 64) {
return false;
}
- return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
+ return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 1e27414..9d4e0be 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -3626,12 +3626,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_p_lsx(ctx, rd, rs, rt);
break;
case NM_LSA:
- /*
- * In nanoMIPS, the shift field directly encodes the shift
- * amount, meaning that the supported shift values are in
- * the range 0 to 3 (instead of 1 to 4 in MIPSR6).
- */
- gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1);
+ gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
break;
case NM_EXTW:
gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index 0c787cb..102a058 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -1,6 +1,7 @@
# Octeon Architecture Module instruction set
#
# Copyright (C) 2022 Pavel Dovgalyuk
+# Copyright (C) 2024 Philippe Mathieu-Daudé
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
@@ -39,3 +40,10 @@ CINS 011100 ..... ..... ..... ..... 11001 . @bitfield
POP 011100 rs:5 00000 rd:5 00000 10110 dw:1
SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1
SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1
+
+&lx base index rd
+@lx ...... base:5 index:5 rd:5 ...... ..... &lx
+LWX 011111 ..... ..... ..... 00000 001010 @lx
+LHX 011111 ..... ..... ..... 00100 001010 @lx
+LBUX 011111 ..... ..... ..... 00110 001010 @lx
+LDX 011111 ..... ..... ..... 01000 001010 @lx
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index d9eb437..b2eca29 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -174,3 +174,15 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
}
return true;
}
+
+static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)
+{
+ gen_lx(ctx, a->rd, a->base, a->index, mop);
+
+ return true;
+}
+
+TRANS(LBUX, trans_lx, MO_UB);
+TRANS(LHX, trans_lx, MO_SW);
+TRANS(LWX, trans_lx, MO_SL);
+TRANS(LDX, trans_lx, MO_UQ);
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
index b906d10..4502ae2 100644
--- a/target/mips/tcg/op_helper.c
+++ b/target/mips/tcg/op_helper.c
@@ -24,6 +24,8 @@
#include "exec/helper-proto.h"
#include "exec/memop.h"
#include "fpu_helper.h"
+#include "qemu/crc32c.h"
+#include <zlib.h>
static inline target_ulong bitswap(target_ulong v)
{
@@ -142,6 +144,30 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
return (int64_t)(int32_t)(uint32_t)tmp5;
}
+/* these crc32 functions are based on target/loongarch/tcg/op_helper.c */
+target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz)
+{
+ uint8_t buf[8];
+ target_ulong mask = ((sz * 8) == 64) ?
+ (target_ulong) -1ULL :
+ ((1ULL << (sz * 8)) - 1);
+
+ m &= mask;
+ stq_le_p(buf, m);
+ return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
+}
+
+target_ulong helper_crc32c(target_ulong val, target_ulong m, uint32_t sz)
+{
+ uint8_t buf[8];
+ target_ulong mask = ((sz * 8) == 64) ?
+ (target_ulong) -1ULL :
+ ((1ULL << (sz * 8)) - 1);
+ m &= mask;
+ stq_le_p(buf, m);
+ return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff);
+}
+
void helper_fork(target_ulong arg1, target_ulong arg2)
{
/*
diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode
index d6989cf..7fbcb10 100644
--- a/target/mips/tcg/rel6.decode
+++ b/target/mips/tcg/rel6.decode
@@ -16,11 +16,16 @@
&r rs rt rd sa
+&special3_crc rs rt c sz
+
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
+@crc32 ...... rs:5 rt:5 ..... c:3 sz:2 ...... &special3_crc
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
+CRC32 011111 ..... ..... 00000 ... .. 001111 @crc32
+
REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c
index 59f237b..4c05662 100644
--- a/target/mips/tcg/rel6_translate.c
+++ b/target/mips/tcg/rel6_translate.c
@@ -23,7 +23,7 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
- return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+ return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}
static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@@ -31,5 +31,17 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
if (TARGET_LONG_BITS != 64) {
return false;
}
- return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
+ return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
+}
+
+static bool trans_CRC32(DisasContext *ctx, arg_special3_crc *a)
+{
+ if (unlikely(!ctx->crcp)
+ || unlikely((a->sz == 3) && (!(ctx->hflags & MIPS_HFLAG_64)))
+ || unlikely((a->c >= 2))) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+ gen_crc32(ctx, a->rt, a->rs, a->rt, a->sz, a->c);
+ return true;
}
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 8658315..d91d6ef 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1957,6 +1957,17 @@ void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
}
}
+void gen_base_index_addr(DisasContext *ctx, TCGv addr, int base, int index)
+{
+ if (base == 0) {
+ gen_load_gpr(addr, index);
+ } else if (index == 0) {
+ gen_load_gpr(addr, base);
+ } else {
+ gen_op_addr_add(ctx, addr, cpu_gpr[base], cpu_gpr[index]);
+ }
+}
+
static target_ulong pc_relative_pc(DisasContext *ctx)
{
target_ulong pc = ctx->base.pc_next;
@@ -2025,6 +2036,15 @@ static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr,
tcg_gen_or_tl(reg, t0, t1);
}
+void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop)
+{
+ TCGv t0 = tcg_temp_new();
+
+ gen_base_index_addr(ctx, t0, base, index);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | mop);
+ gen_store_gpr(t0, rd);
+}
+
/* Load */
static void gen_ld(DisasContext *ctx, uint32_t opc,
int rt, int base, int offset)
@@ -10546,13 +10566,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv t0 = tcg_temp_new();
- if (base == 0) {
- gen_load_gpr(t0, index);
- } else if (index == 0) {
- gen_load_gpr(t0, base);
- } else {
- gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
- }
+ gen_base_index_addr(ctx, t0, base, index);
/*
* Don't do NOP if destination is zero: we must perform the actual
* memory access.
@@ -11323,47 +11337,6 @@ enum {
/* MIPSDSP functions. */
-/* Indexed load is not for DSP only */
-static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
- int rd, int base, int offset)
-{
- TCGv t0;
-
- if (!(ctx->insn_flags & INSN_OCTEON)) {
- check_dsp(ctx);
- }
- t0 = tcg_temp_new();
-
- if (base == 0) {
- gen_load_gpr(t0, offset);
- } else if (offset == 0) {
- gen_load_gpr(t0, base);
- } else {
- gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
- }
-
- switch (opc) {
- case OPC_LBUX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
- gen_store_gpr(t0, rd);
- break;
- case OPC_LHX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW);
- gen_store_gpr(t0, rd);
- break;
- case OPC_LWX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
- gen_store_gpr(t0, rd);
- break;
-#if defined(TARGET_MIPS64)
- case OPC_LDX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
- gen_store_gpr(t0, rd);
- break;
-#endif
- }
-}
-
static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
int ret, int v1, int v2)
{
@@ -13449,6 +13422,29 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
+void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz,
+ int crc32c)
+{
+ TCGv t0;
+ TCGv t1;
+ TCGv_i32 tsz = tcg_constant_i32(1 << sz);
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return;
+ }
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rt);
+ gen_load_gpr(t1, rs);
+
+ if (crc32c) {
+ gen_helper_crc32c(cpu_gpr[rd], t0, t1, tsz);
+ } else {
+ gen_helper_crc32(cpu_gpr[rd], t0, t1, tsz);
+ }
+}
+
static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
@@ -13611,15 +13607,22 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_LX_DSP:
+ check_dsp(ctx);
op2 = MASK_LX(ctx->opcode);
switch (op2) {
#if defined(TARGET_MIPS64)
case OPC_LDX:
+ gen_lx(ctx, rd, rs, rt, MO_UQ);
+ break;
#endif
case OPC_LBUX:
+ gen_lx(ctx, rd, rs, rt, MO_UB);
+ break;
case OPC_LHX:
+ gen_lx(ctx, rd, rs, rt, MO_SW);
+ break;
case OPC_LWX:
- gen_mips_lx(ctx, op2, rd, rs, rt);
+ gen_lx(ctx, rd, rs, rt, MO_SL);
break;
default: /* Invalid */
MIPS_INVAL("MASK LX");
@@ -15095,6 +15098,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1;
ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3;
+ ctx->crcp = (env->CP0_Config5 >> CP0C5_CRCP) & 1;
restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
ctx->mem_idx = MIPS_HFLAG_UM;
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 1bf153d..89dde1e 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -51,6 +51,7 @@ typedef struct DisasContext {
bool abs2008;
bool mi;
int gi;
+ bool crcp;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@@ -153,6 +154,7 @@ void check_cp1_registers(DisasContext *ctx, int regs);
void check_cop1x(DisasContext *ctx);
void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
+void gen_base_index_addr(DisasContext *ctx, TCGv addr, int base, int index);
void gen_move_low32(TCGv ret, TCGv_i64 arg);
void gen_move_high32(TCGv ret, TCGv_i64 arg);
void gen_load_gpr(TCGv t, int reg);
@@ -167,6 +169,7 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
int get_fp_bit(int cc);
+void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop);
void gen_ldxs(DisasContext *ctx, int base, int index, int rd);
void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp);
void gen_addiupc(DisasContext *ctx, int rx, int imm,
@@ -181,6 +184,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
+void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz, int crc32c);
extern TCGv cpu_gpr[32], cpu_PC;
#if defined(TARGET_MIPS64)
diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/translate_addr_const.c
index 6f4b39f..1d140e9 100644
--- a/target/mips/tcg/translate_addr_const.c
+++ b/target/mips/tcg/translate_addr_const.c
@@ -26,7 +26,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
- tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_shli_tl(t0, t0, sa);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
return true;
@@ -47,7 +47,7 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
- tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_shli_tl(t0, t0, sa);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
return true;
}
generated by cgit v1.1 at 2025-07-25 12:03:38 +0000