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Diffstat (limited to 'target/arm/tcg/cpu32.c')
-rw-r--r--target/arm/tcg/cpu32.c34
1 files changed, 17 insertions, 17 deletions
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 942b636..a2a23ea 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -225,7 +225,7 @@ static void arm1136_r2_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x111);
SET_IDREG(isar, ID_PFR1, 0x1);
SET_IDREG(isar, ID_DFR0, 0x2);
- cpu->id_afr0 = 0x3;
+ SET_IDREG(isar, ID_AFR0, 0x3);
SET_IDREG(isar, ID_MMFR0, 0x01130003);
SET_IDREG(isar, ID_MMFR1, 0x10030302);
SET_IDREG(isar, ID_MMFR2, 0x01222110);
@@ -257,7 +257,7 @@ static void arm1136_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x111);
SET_IDREG(isar, ID_PFR1, 0x1);
SET_IDREG(isar, ID_DFR0, 0x2);
- cpu->id_afr0 = 0x3;
+ SET_IDREG(isar, ID_AFR0, 0x3);
SET_IDREG(isar, ID_MMFR0, 0x01130003);
SET_IDREG(isar, ID_MMFR1, 0x10030302);
SET_IDREG(isar, ID_MMFR2, 0x01222110);
@@ -290,7 +290,7 @@ static void arm1176_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x111);
SET_IDREG(isar, ID_PFR1, 0x11);
SET_IDREG(isar, ID_DFR0, 0x33);
- cpu->id_afr0 = 0;
+ SET_IDREG(isar, ID_AFR0, 0);
SET_IDREG(isar, ID_MMFR0, 0x01130003);
SET_IDREG(isar, ID_MMFR1, 0x10030302);
SET_IDREG(isar, ID_MMFR2, 0x01222100);
@@ -320,7 +320,7 @@ static void arm11mpcore_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x111);
SET_IDREG(isar, ID_PFR1, 0x1);
SET_IDREG(isar, ID_DFR0, 0);
- cpu->id_afr0 = 0x2;
+ SET_IDREG(isar, ID_AFR0, 0x2);
SET_IDREG(isar, ID_MMFR0, 0x01100103);
SET_IDREG(isar, ID_MMFR1, 0x10020302);
SET_IDREG(isar, ID_MMFR2, 0x01222000);
@@ -360,7 +360,7 @@ static void cortex_a8_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x1031);
SET_IDREG(isar, ID_PFR1, 0x11);
SET_IDREG(isar, ID_DFR0, 0x400);
- cpu->id_afr0 = 0;
+ SET_IDREG(isar, ID_AFR0, 0);
SET_IDREG(isar, ID_MMFR0, 0x31100003);
SET_IDREG(isar, ID_MMFR1, 0x20000000);
SET_IDREG(isar, ID_MMFR2, 0x01202000);
@@ -371,7 +371,7 @@ static void cortex_a8_initfn(Object *obj)
SET_IDREG(isar, ID_ISAR3, 0x11112131);
SET_IDREG(isar, ID_ISAR4, 0x00111142);
cpu->isar.dbgdidr = 0x15141000;
- cpu->clidr = (1 << 27) | (2 << 24) | 3;
+ SET_IDREG(isar, CLIDR, (1 << 27) | (2 << 24) | 3);
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
@@ -436,7 +436,7 @@ static void cortex_a9_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x1031);
SET_IDREG(isar, ID_PFR1, 0x11);
SET_IDREG(isar, ID_DFR0, 0x000);
- cpu->id_afr0 = 0;
+ SET_IDREG(isar, ID_AFR0, 0);
SET_IDREG(isar, ID_MMFR0, 0x00100103);
SET_IDREG(isar, ID_MMFR1, 0x20000000);
SET_IDREG(isar, ID_MMFR2, 0x01230000);
@@ -447,7 +447,7 @@ static void cortex_a9_initfn(Object *obj)
SET_IDREG(isar, ID_ISAR3, 0x11112131);
SET_IDREG(isar, ID_ISAR4, 0x00111142);
cpu->isar.dbgdidr = 0x35141000;
- cpu->clidr = (1 << 27) | (1 << 24) | 3;
+ SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 3);
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
cpu->isar.reset_pmcr_el0 = 0x41093000;
@@ -502,7 +502,7 @@ static void cortex_a7_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x00001131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x02010555);
- cpu->id_afr0 = 0x00000000;
+ SET_IDREG(isar, ID_AFR0, 0x00000000);
SET_IDREG(isar, ID_MMFR0, 0x10101105);
SET_IDREG(isar, ID_MMFR1, 0x40000000);
SET_IDREG(isar, ID_MMFR2, 0x01240000);
@@ -519,7 +519,7 @@ static void cortex_a7_initfn(Object *obj)
cpu->isar.dbgdidr = 0x3515f005;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x1;
- cpu->clidr = 0x0a200023;
+ SET_IDREG(isar, CLIDR, 0x0a200023);
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
@@ -554,7 +554,7 @@ static void cortex_a15_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x00001131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x02010555);
- cpu->id_afr0 = 0x00000000;
+ SET_IDREG(isar, ID_AFR0, 0x00000000);
SET_IDREG(isar, ID_MMFR0, 0x10201105);
SET_IDREG(isar, ID_MMFR1, 0x20000000);
SET_IDREG(isar, ID_MMFR2, 0x01240000);
@@ -567,7 +567,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->isar.dbgdidr = 0x3515f021;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x0;
- cpu->clidr = 0x0a200023;
+ SET_IDREG(isar, CLIDR, 0x0a200023);
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
@@ -598,7 +598,7 @@ static void cortex_r5_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x0131);
SET_IDREG(isar, ID_PFR1, 0x001);
SET_IDREG(isar, ID_DFR0, 0x010400);
- cpu->id_afr0 = 0x0;
+ SET_IDREG(isar, ID_AFR0, 0x0);
SET_IDREG(isar, ID_MMFR0, 0x0210030);
SET_IDREG(isar, ID_MMFR1, 0x00000000);
SET_IDREG(isar, ID_MMFR2, 0x01200000);
@@ -745,7 +745,7 @@ static void cortex_r52_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x00000131);
SET_IDREG(isar, ID_PFR1, 0x10111001);
SET_IDREG(isar, ID_DFR0, 0x03010006);
- cpu->id_afr0 = 0x00000000;
+ SET_IDREG(isar, ID_AFR0, 0x00000000);
SET_IDREG(isar, ID_MMFR0, 0x00211040);
SET_IDREG(isar, ID_MMFR1, 0x40000000);
SET_IDREG(isar, ID_MMFR2, 0x01200000);
@@ -758,7 +758,7 @@ static void cortex_r52_initfn(Object *obj)
SET_IDREG(isar, ID_ISAR4, 0x00010142);
SET_IDREG(isar, ID_ISAR5, 0x00010001);
cpu->isar.dbgdidr = 0x77168000;
- cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
+ SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 0x3);
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
@@ -977,7 +977,7 @@ static void arm_max_initfn(Object *obj)
SET_IDREG(isar, ID_PFR0, 0x00000131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x03010066);
- cpu->id_afr0 = 0x00000000;
+ SET_IDREG(isar, ID_AFR0, 0x00000000);
SET_IDREG(isar, ID_MMFR0, 0x10101105);
SET_IDREG(isar, ID_MMFR1, 0x40000000);
SET_IDREG(isar, ID_MMFR2, 0x01260000);
@@ -990,7 +990,7 @@ static void arm_max_initfn(Object *obj)
SET_IDREG(isar, ID_ISAR5, 0x00011121);
SET_IDREG(isar, ID_ISAR6, 0);
cpu->isar.reset_pmcr_el0 = 0x41013000;
- cpu->clidr = 0x0a200023;
+ SET_IDREG(isar, CLIDR, 0x0a200023);
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
generated by cgit v1.1 at 2025-07-16 10:31:48 +0000