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-rw-r--r--linux-user/mips/cpu_loop.c16
-rw-r--r--linux-user/mips/elfload.c142
-rw-r--r--linux-user/mips/target_elf.h29
-rw-r--r--linux-user/mips/target_ptrace.h17
-rw-r--r--linux-user/mips/target_signal.h1
-rw-r--r--linux-user/mips/target_syscall.h19
6 files changed, 184 insertions, 40 deletions
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 6405806..e67b8a2 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -211,12 +211,9 @@ done_syscall:
}
}
-void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
+void init_main_thread(CPUState *cs, struct image_info *info)
{
- CPUState *cpu = env_cpu(env);
- TaskState *ts = get_task_state(cpu);
- struct image_info *info = ts->info;
- int i;
+ CPUArchState *env = cpu_env(cs);
struct mode_req {
bool single;
@@ -245,12 +242,11 @@ void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs)
struct mode_req prog_req;
struct mode_req interp_req;
+ target_ulong entry = info->entry;
- for(i = 0; i < 32; i++) {
- env->active_tc.gpr[i] = regs->regs[i];
- }
- env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
- if (regs->cp0_epc & 1) {
+ env->active_tc.gpr[29] = info->start_stack;
+ env->active_tc.PC = entry & ~(target_ulong)1;
+ if (entry & 1) {
env->hflags |= MIPS_HFLAG_M16;
}
diff --git a/linux-user/mips/elfload.c b/linux-user/mips/elfload.c
new file mode 100644
index 0000000..e0c50f5
--- /dev/null
+++ b/linux-user/mips/elfload.c
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "qemu/osdep.h"
+#include "qemu.h"
+#include "loader.h"
+#include "elf.h"
+#include "target_elf.h"
+
+
+const char *get_elf_cpu_model(uint32_t eflags)
+{
+#ifdef TARGET_MIPS64
+ switch (eflags & EF_MIPS_MACH) {
+ case EF_MIPS_MACH_OCTEON:
+ case EF_MIPS_MACH_OCTEON2:
+ case EF_MIPS_MACH_OCTEON3:
+ return "Octeon68XX";
+ case EF_MIPS_MACH_LS2E:
+ return "Loongson-2E";
+ case EF_MIPS_MACH_LS2F:
+ return "Loongson-2F";
+ case EF_MIPS_MACH_LS3A:
+ return "Loongson-3A1000";
+ default:
+ break;
+ }
+ switch (eflags & EF_MIPS_ARCH) {
+ case EF_MIPS_ARCH_64R6:
+ return "I6400";
+ case EF_MIPS_ARCH_64R2:
+ return "MIPS64R2-generic";
+ default:
+ break;
+ }
+ return "5KEf";
+#else
+ if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6) {
+ return "mips32r6-generic";
+ }
+ if (eflags & EF_MIPS_NAN2008) {
+ return "P5600";
+ }
+ return "24Kf";
+#endif
+}
+
+/* See arch/mips/include/uapi/asm/hwcap.h. */
+enum {
+ HWCAP_MIPS_R6 = (1 << 0),
+ HWCAP_MIPS_MSA = (1 << 1),
+ HWCAP_MIPS_CRC32 = (1 << 2),
+ HWCAP_MIPS_MIPS16 = (1 << 3),
+ HWCAP_MIPS_MDMX = (1 << 4),
+ HWCAP_MIPS_MIPS3D = (1 << 5),
+ HWCAP_MIPS_SMARTMIPS = (1 << 6),
+ HWCAP_MIPS_DSP = (1 << 7),
+ HWCAP_MIPS_DSP2 = (1 << 8),
+ HWCAP_MIPS_DSP3 = (1 << 9),
+ HWCAP_MIPS_MIPS16E2 = (1 << 10),
+ HWCAP_LOONGSON_MMI = (1 << 11),
+ HWCAP_LOONGSON_EXT = (1 << 12),
+ HWCAP_LOONGSON_EXT2 = (1 << 13),
+ HWCAP_LOONGSON_CPUCFG = (1 << 14),
+};
+
+#define GET_FEATURE_INSN(_flag, _hwcap) \
+ do { if (cpu->env.insn_flags & (_flag)) { hwcaps |= _hwcap; } } while (0)
+
+#define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \
+ do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0)
+
+#define GET_FEATURE_REG_EQU(_reg, _start, _length, _val, _hwcap) \
+ do { \
+ if (extract32(cpu->env._reg, (_start), (_length)) == (_val)) { \
+ hwcaps |= _hwcap; \
+ } \
+ } while (0)
+
+abi_ulong get_elf_hwcap(CPUState *cs)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ abi_ulong hwcaps = 0;
+
+ GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, CP0C0_AR_LENGTH,
+ 2, HWCAP_MIPS_R6);
+ GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
+ GET_FEATURE_INSN(ASE_LMMI, HWCAP_LOONGSON_MMI);
+ GET_FEATURE_INSN(ASE_LEXT, HWCAP_LOONGSON_EXT);
+
+ return hwcaps;
+}
+
+#undef GET_FEATURE_REG_EQU
+#undef GET_FEATURE_REG_SET
+#undef GET_FEATURE_INSN
+
+#define MATCH_PLATFORM_INSN(_flags, _base_platform) \
+ do { if ((cpu->env.insn_flags & (_flags)) == _flags) \
+ { return _base_platform; } } while (0)
+
+const char *get_elf_base_platform(CPUState *cs)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+
+ /* 64 bit ISAs goes first */
+ MATCH_PLATFORM_INSN(CPU_MIPS64R6, "mips64r6");
+ MATCH_PLATFORM_INSN(CPU_MIPS64R5, "mips64r5");
+ MATCH_PLATFORM_INSN(CPU_MIPS64R2, "mips64r2");
+ MATCH_PLATFORM_INSN(CPU_MIPS64R1, "mips64");
+ MATCH_PLATFORM_INSN(CPU_MIPS5, "mips5");
+ MATCH_PLATFORM_INSN(CPU_MIPS4, "mips4");
+ MATCH_PLATFORM_INSN(CPU_MIPS3, "mips3");
+
+ /* 32 bit ISAs */
+ MATCH_PLATFORM_INSN(CPU_MIPS32R6, "mips32r6");
+ MATCH_PLATFORM_INSN(CPU_MIPS32R5, "mips32r5");
+ MATCH_PLATFORM_INSN(CPU_MIPS32R2, "mips32r2");
+ MATCH_PLATFORM_INSN(CPU_MIPS32R1, "mips32");
+ MATCH_PLATFORM_INSN(CPU_MIPS2, "mips2");
+
+ /* Fallback */
+ return "mips";
+}
+
+#undef MATCH_PLATFORM_INSN
+
+/* See linux kernel: arch/mips/kernel/process.c:elf_dump_regs. */
+void elf_core_copy_regs(target_elf_gregset_t *r, const CPUMIPSState *env)
+{
+ for (int i = 1; i < ARRAY_SIZE(env->active_tc.gpr); i++) {
+ r->pt.regs[i] = tswapl(env->active_tc.gpr[i]);
+ }
+
+ r->pt.regs[26] = 0;
+ r->pt.regs[27] = 0;
+ r->pt.lo = tswapl(env->active_tc.LO[0]);
+ r->pt.hi = tswapl(env->active_tc.HI[0]);
+ r->pt.cp0_epc = tswapl(env->active_tc.PC);
+ r->pt.cp0_badvaddr = tswapl(env->CP0_BadVAddr);
+ r->pt.cp0_status = tswapl(env->CP0_Status);
+ r->pt.cp0_cause = tswapl(env->CP0_Cause);
+}
diff --git a/linux-user/mips/target_elf.h b/linux-user/mips/target_elf.h
index 71a3231..157306f 100644
--- a/linux-user/mips/target_elf.h
+++ b/linux-user/mips/target_elf.h
@@ -7,14 +7,23 @@
#ifndef MIPS_TARGET_ELF_H
#define MIPS_TARGET_ELF_H
-static inline const char *cpu_get_model(uint32_t eflags)
-{
- if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6) {
- return "mips32r6-generic";
- }
- if (eflags & EF_MIPS_NAN2008) {
- return "P5600";
- }
- return "24Kf";
-}
+
+#include "target_ptrace.h"
+
+#define ELF_CLASS ELFCLASS32
+#define ELF_MACHINE EM_MIPS
+#define EXSTACK_DEFAULT true
+
+#define HAVE_ELF_HWCAP 1
+#define HAVE_ELF_BASE_PLATFORM 1
+#define HAVE_ELF_CORE_DUMP 1
+
+/* See linux kernel: arch/mips/include/asm/elf.h. */
+typedef struct target_elf_gregset_t {
+ union {
+ abi_ulong reserved[45];
+ struct target_pt_regs pt;
+ };
+} target_elf_gregset_t;
+
#endif
diff --git a/linux-user/mips/target_ptrace.h b/linux-user/mips/target_ptrace.h
new file mode 100644
index 0000000..2f63b27
--- /dev/null
+++ b/linux-user/mips/target_ptrace.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MIPS_TARGET_PTRACE_H
+#define MIPS_TARGET_PTRACE_H
+
+struct target_pt_regs {
+ abi_ulong pad0[6];
+ abi_ulong regs[32];
+ abi_ulong lo;
+ abi_ulong hi;
+ abi_ulong cp0_epc;
+ abi_ulong cp0_badvaddr;
+ abi_ulong cp0_status;
+ abi_ulong cp0_cause;
+};
+
+#endif /* MIPS_TARGET_PTRACE_H */
diff --git a/linux-user/mips/target_signal.h b/linux-user/mips/target_signal.h
index fa542c1..4481426 100644
--- a/linux-user/mips/target_signal.h
+++ b/linux-user/mips/target_signal.h
@@ -64,7 +64,6 @@ typedef struct target_sigaltstack {
#define TARGET_SA_NODEFER 0x40000000
#define TARGET_SA_RESTART 0x10000000
#define TARGET_SA_RESETHAND 0x80000000
-#define TARGET_SA_RESTORER 0x04000000 /* Only for O32 */
#define TARGET_MINSIGSTKSZ 2048
diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h
index 08ead67..dfcdf32 100644
--- a/linux-user/mips/target_syscall.h
+++ b/linux-user/mips/target_syscall.h
@@ -1,25 +1,6 @@
#ifndef MIPS_TARGET_SYSCALL_H
#define MIPS_TARGET_SYSCALL_H
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-struct target_pt_regs {
- /* Pad bytes for argument save space on the stack. */
- abi_ulong pad0[6];
-
- /* Saved main processor registers. */
- abi_ulong regs[32];
-
- /* Saved special registers. */
- abi_ulong cp0_status;
- abi_ulong lo;
- abi_ulong hi;
- abi_ulong cp0_badvaddr;
- abi_ulong cp0_cause;
- abi_ulong cp0_epc;
-};
-
#define UNAME_MACHINE "mips"
#define UNAME_MINIMUM_RELEASE "2.6.32"
generated by cgit v1.1 at 2025-09-02 10:44:36 +0000