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-rw-r--r--include/hw/intc/arm_gic.h3
-rw-r--r--include/hw/intc/arm_gic_common.h2
-rw-r--r--include/hw/intc/armv7m_nvic.h14
-rw-r--r--include/hw/intc/aspeed_intc.h5
-rw-r--r--include/hw/intc/loongarch_extioi.h6
-rw-r--r--include/hw/intc/loongarch_extioi_common.h3
-rw-r--r--include/hw/intc/loongarch_ipi.h6
-rw-r--r--include/hw/intc/loongarch_pch_pic.h6
-rw-r--r--include/hw/intc/loongarch_pic_common.h59
-rw-r--r--include/hw/intc/loongson_ipi_common.h2
10 files changed, 61 insertions, 45 deletions
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index 48f6a51..be923f7 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -27,6 +27,9 @@
* implement the security extensions
* + QOM property "has-virtualization-extensions": set true if the GIC should
* implement the virtualization extensions
+ * + QOM property "first-cpu-index": index of the first cpu attached to the
+ * GIC (default 0). The CPUs connected to the GIC are assumed to be
+ * first-cpu-index, first-cpu-index + 1, ... first-cpu-index + num-cpu - 1.
* + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
* [0..P-1] SPIs
* [P..P+31] PPIs for CPU 0
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index 97fea41..93a3cc2 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -129,6 +129,8 @@ struct GICState {
uint32_t num_lrs;
uint32_t num_cpu;
+ /* cpu_index of the first CPU, attached to this GIC. */
+ uint32_t first_cpu_index;
MemoryRegion iomem; /* Distributor */
/* This is just so we can have an opaque pointer which identifies
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 89fe8ae..7b9964f 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -189,21 +189,7 @@ int armv7m_nvic_raw_execution_priority(NVICState *s);
* @secure: the security state to test
* This corresponds to the pseudocode IsReqExecPriNeg().
*/
-#ifndef CONFIG_USER_ONLY
bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
-#else
-static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
-{
- return false;
-}
-#endif
-#ifndef CONFIG_USER_ONLY
bool armv7m_nvic_can_take_pending_exception(NVICState *s);
-#else
-static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
-{
- return true;
-}
-#endif
#endif
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 3727ba2..5128838 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -15,6 +15,11 @@
#define TYPE_ASPEED_INTC "aspeed.intc"
#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
+#define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
+#define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
+#define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
+#define TYPE_ASPEED_2700TSP_INTCIO TYPE_ASPEED_INTC "io-ast2700tsp"
+
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_MAX_INPINS 10
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
index 351f18a..9be1d73 100644
--- a/include/hw/intc/loongarch_extioi.h
+++ b/include/hw/intc/loongarch_extioi.h
@@ -15,6 +15,7 @@ OBJECT_DECLARE_TYPE(LoongArchExtIOIState, LoongArchExtIOIClass, LOONGARCH_EXTIOI
struct LoongArchExtIOIState {
LoongArchExtIOICommonState parent_obj;
+ int dev_fd;
};
struct LoongArchExtIOIClass {
@@ -22,6 +23,11 @@ struct LoongArchExtIOIClass {
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
+ ResettablePhases parent_phases;
};
+void kvm_extioi_realize(DeviceState *dev, Error **errp);
+int kvm_extioi_get(void *opaque);
+int kvm_extioi_put(void *opaque, int version_id);
+
#endif /* LOONGARCH_EXTIOI_H */
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
index 22d7880..dca25ff 100644
--- a/include/hw/intc/loongarch_extioi_common.h
+++ b/include/hw/intc/loongarch_extioi_common.h
@@ -35,7 +35,7 @@
#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
-#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
+#define EXTIOI_COREISR_END (0x820 - APIC_OFFSET)
#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
#define EXTIOI_SIZE 0x800
@@ -94,6 +94,7 @@ struct LoongArchExtIOICommonClass {
SysBusDeviceClass parent_class;
DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
int (*pre_save)(void *s);
int (*post_load)(void *s, int version_id);
};
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
index 923bf21..5175a6b 100644
--- a/include/hw/intc/loongarch_ipi.h
+++ b/include/hw/intc/loongarch_ipi.h
@@ -16,11 +16,17 @@ OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI)
struct LoongarchIPIState {
LoongsonIPICommonState parent_obj;
+ int dev_fd;
};
struct LoongarchIPIClass {
LoongsonIPICommonClass parent_class;
DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
};
+void kvm_ipi_realize(DeviceState *dev, Error **errp);
+int kvm_ipi_get(void *opaque);
+int kvm_ipi_put(void *opaque, int version_id);
+
#endif
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
index 481cc58..a46b6f8 100644
--- a/include/hw/intc/loongarch_pch_pic.h
+++ b/include/hw/intc/loongarch_pch_pic.h
@@ -16,12 +16,18 @@ OBJECT_DECLARE_TYPE(LoongarchPICState, LoongarchPICClass, LOONGARCH_PIC)
struct LoongarchPICState {
LoongArchPICCommonState parent_obj;
+ int dev_fd;
};
struct LoongarchPICClass {
LoongArchPICCommonClass parent_class;
DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
};
+void kvm_pic_realize(DeviceState *dev, Error **errp);
+int kvm_pic_get(void *opaque);
+int kvm_pic_put(void *opaque, int version_id);
+
#endif /* HW_LOONGARCH_PCH_PIC_H */
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
index 43cce48..f774c97 100644
--- a/include/hw/intc/loongarch_pic_common.h
+++ b/include/hw/intc/loongarch_pic_common.h
@@ -10,44 +10,44 @@
#include "hw/pci-host/ls7a.h"
#include "hw/sysbus.h"
-#define PCH_PIC_INT_ID_VAL 0x7000000UL
-#define PCH_PIC_INT_ID_VER 0x1UL
-#define PCH_PIC_INT_ID_LO 0x00
-#define PCH_PIC_INT_ID_HI 0x04
-#define PCH_PIC_INT_MASK_LO 0x20
-#define PCH_PIC_INT_MASK_HI 0x24
-#define PCH_PIC_HTMSI_EN_LO 0x40
-#define PCH_PIC_HTMSI_EN_HI 0x44
-#define PCH_PIC_INT_EDGE_LO 0x60
-#define PCH_PIC_INT_EDGE_HI 0x64
-#define PCH_PIC_INT_CLEAR_LO 0x80
-#define PCH_PIC_INT_CLEAR_HI 0x84
-#define PCH_PIC_AUTO_CTRL0_LO 0xc0
-#define PCH_PIC_AUTO_CTRL0_HI 0xc4
-#define PCH_PIC_AUTO_CTRL1_LO 0xe0
-#define PCH_PIC_AUTO_CTRL1_HI 0xe4
-#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
+#define PCH_PIC_INT_ID 0x00
+#define PCH_PIC_INT_ID_VAL 0x7
+#define PCH_PIC_INT_ID_VER 0x1
+#define PCH_PIC_INT_MASK 0x20
+#define PCH_PIC_HTMSI_EN 0x40
+#define PCH_PIC_INT_EDGE 0x60
+#define PCH_PIC_INT_CLEAR 0x80
+#define PCH_PIC_AUTO_CTRL0 0xc0
+#define PCH_PIC_AUTO_CTRL1 0xe0
+#define PCH_PIC_ROUTE_ENTRY 0x100
#define PCH_PIC_ROUTE_ENTRY_END 0x13f
-#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
+#define PCH_PIC_HTMSI_VEC 0x200
#define PCH_PIC_HTMSI_VEC_END 0x23f
-#define PCH_PIC_INT_STATUS_LO 0x3a0
-#define PCH_PIC_INT_STATUS_HI 0x3a4
-#define PCH_PIC_INT_POL_LO 0x3e0
-#define PCH_PIC_INT_POL_HI 0x3e4
-
-#define STATUS_LO_START 0
-#define STATUS_HI_START 0x4
-#define POL_LO_START 0x40
-#define POL_HI_START 0x44
+#define PCH_PIC_INT_REQUEST 0x380
+#define PCH_PIC_INT_STATUS 0x3a0
+#define PCH_PIC_INT_POL 0x3e0
#define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
+union LoongArchPIC_ID {
+ struct {
+ uint8_t _reserved_0[3];
+ uint8_t id;
+ uint8_t version;
+ uint8_t _reserved_1;
+ uint8_t irq_num;
+ uint8_t _reserved_2;
+ } QEMU_PACKED desc;
+ uint64_t data;
+};
+
struct LoongArchPICCommonState {
SysBusDevice parent_obj;
qemu_irq parent_irq[64];
+ union LoongArchPIC_ID id; /* 0x00 interrupt ID register */
uint64_t int_mask; /* 0x020 interrupt mask register */
uint64_t htmsi_en; /* 0x040 1=msi */
uint64_t intedge; /* 0x060 edge=1 level=0 */
@@ -66,9 +66,7 @@ struct LoongArchPICCommonState {
uint8_t route_entry[64]; /* 0x100 - 0x138 */
uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
- MemoryRegion iomem32_low;
- MemoryRegion iomem32_high;
- MemoryRegion iomem8;
+ MemoryRegion iomem;
unsigned int irq_num;
};
@@ -76,6 +74,7 @@ struct LoongArchPICCommonClass {
SysBusDeviceClass parent_class;
DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
int (*pre_save)(LoongArchPICCommonState *s);
int (*post_load)(LoongArchPICCommonState *s, int version_id);
};
diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h
index b587f9c..e58ce2a 100644
--- a/include/hw/intc/loongson_ipi_common.h
+++ b/include/hw/intc/loongson_ipi_common.h
@@ -48,6 +48,8 @@ struct LoongsonIPICommonClass {
AddressSpace *(*get_iocsr_as)(CPUState *cpu);
int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id,
int *index, CPUState **pcs);
+ int (*pre_save)(void *opaque);
+ int (*post_load)(void *opaque, int version_id);
};
MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
generated by cgit v1.1 at 2025-07-01 22:56:15 +0000