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-rw-r--r--include/hw/arm/aspeed.h2
-rw-r--r--include/hw/arm/boot.h3
-rw-r--r--include/hw/arm/max78000_soc.h50
-rw-r--r--include/hw/arm/npcm8xx.h5
-rw-r--r--include/hw/arm/omap.h536
-rw-r--r--include/hw/arm/sharpsl.h2
-rw-r--r--include/hw/arm/soc_dma.h4
-rw-r--r--include/hw/arm/stm32f205_soc.h2
-rw-r--r--include/hw/arm/virt.h5
-rw-r--r--include/hw/arm/xen_arch_hvm.h9
10 files changed, 336 insertions, 282 deletions
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index 973277b..6c36455 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -35,7 +35,9 @@ struct AspeedMachineClass {
uint32_t hw_strap2;
const char *fmc_model;
const char *spi_model;
+ const char *spi2_model;
uint32_t num_cs;
+ uint32_t num_cs2;
uint32_t macs_mask;
void (*i2c_init)(AspeedMachineState *bmc);
uint32_t uart_default;
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
index b12bf61..a2e22bd 100644
--- a/include/hw/arm/boot.h
+++ b/include/hw/arm/boot.h
@@ -132,6 +132,9 @@ struct arm_boot_info {
bool secure_board_setup;
arm_endianness endianness;
+
+ /* CPU having load the kernel and that should be the first to boot. */
+ ARMCPU *primary_cpu;
};
/**
diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h
new file mode 100644
index 0000000..a203079
--- /dev/null
+++ b/include/hw/arm/max78000_soc.h
@@ -0,0 +1,50 @@
+/*
+ * MAX78000 SOC
+ *
+ * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_ARM_MAX78000_SOC_H
+#define HW_ARM_MAX78000_SOC_H
+
+#include "hw/or-irq.h"
+#include "hw/arm/armv7m.h"
+#include "hw/misc/max78000_aes.h"
+#include "hw/misc/max78000_gcr.h"
+#include "hw/misc/max78000_icc.h"
+#include "hw/char/max78000_uart.h"
+#include "hw/misc/max78000_trng.h"
+#include "qom/object.h"
+
+#define TYPE_MAX78000_SOC "max78000-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC)
+
+#define FLASH_BASE_ADDRESS 0x10000000
+#define FLASH_SIZE (512 * 1024)
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (128 * 1024)
+
+/* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RISC */
+#define MAX78000_NUM_ICC 2
+#define MAX78000_NUM_UART 3
+
+struct MAX78000State {
+ SysBusDevice parent_obj;
+
+ ARMv7MState armv7m;
+
+ MemoryRegion sram;
+ MemoryRegion flash;
+
+ Max78000GcrState gcr;
+ Max78000IccState icc[MAX78000_NUM_ICC];
+ Max78000UartState uart[MAX78000_NUM_UART];
+ Max78000TrngState trng;
+ Max78000AesState aes;
+
+ Clock *sysclk;
+};
+
+#endif
diff --git a/include/hw/arm/npcm8xx.h b/include/hw/arm/npcm8xx.h
index 3436abf..a8377db 100644
--- a/include/hw/arm/npcm8xx.h
+++ b/include/hw/arm/npcm8xx.h
@@ -28,7 +28,8 @@
#include "hw/misc/npcm7xx_mft.h"
#include "hw/misc/npcm7xx_pwm.h"
#include "hw/misc/npcm7xx_rng.h"
-#include "hw/net/npcm7xx_emc.h"
+#include "hw/net/npcm_gmac.h"
+#include "hw/net/npcm_pcs.h"
#include "hw/nvram/npcm7xx_otp.h"
#include "hw/sd/npcm7xx_sdhci.h"
#include "hw/timer/npcm7xx_timer.h"
@@ -99,6 +100,8 @@ struct NPCM8xxState {
EHCISysBusState ehci[2];
OHCISysBusState ohci[2];
NPCM7xxFIUState fiu[3];
+ NPCMGMACState gmac[4];
+ NPCMPCSState pcs;
NPCM7xxSDHCIState mmc;
NPCMPSPIState pspi;
};
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index 6185507..bdb2e88 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -25,24 +25,24 @@
#include "qemu/log.h"
#include "qom/object.h"
-# define OMAP_EMIFS_BASE 0x00000000
-# define OMAP_CS0_BASE 0x00000000
-# define OMAP_CS1_BASE 0x04000000
-# define OMAP_CS2_BASE 0x08000000
-# define OMAP_CS3_BASE 0x0c000000
-# define OMAP_EMIFF_BASE 0x10000000
-# define OMAP_IMIF_BASE 0x20000000
-# define OMAP_LOCALBUS_BASE 0x30000000
-# define OMAP_MPUI_BASE 0xe1000000
-
-# define OMAP730_SRAM_SIZE 0x00032000
-# define OMAP15XX_SRAM_SIZE 0x00030000
-# define OMAP16XX_SRAM_SIZE 0x00004000
-# define OMAP1611_SRAM_SIZE 0x0003e800
-# define OMAP_CS0_SIZE 0x04000000
-# define OMAP_CS1_SIZE 0x04000000
-# define OMAP_CS2_SIZE 0x04000000
-# define OMAP_CS3_SIZE 0x04000000
+#define OMAP_EMIFS_BASE 0x00000000
+#define OMAP_CS0_BASE 0x00000000
+#define OMAP_CS1_BASE 0x04000000
+#define OMAP_CS2_BASE 0x08000000
+#define OMAP_CS3_BASE 0x0c000000
+#define OMAP_EMIFF_BASE 0x10000000
+#define OMAP_IMIF_BASE 0x20000000
+#define OMAP_LOCALBUS_BASE 0x30000000
+#define OMAP_MPUI_BASE 0xe1000000
+
+#define OMAP730_SRAM_SIZE 0x00032000
+#define OMAP15XX_SRAM_SIZE 0x00030000
+#define OMAP16XX_SRAM_SIZE 0x00004000
+#define OMAP1611_SRAM_SIZE 0x0003e800
+#define OMAP_CS0_SIZE 0x04000000
+#define OMAP_CS1_SIZE 0x04000000
+#define OMAP_CS2_SIZE 0x04000000
+#define OMAP_CS3_SIZE 0x04000000
/* omap_clk.c */
struct omap_mpu_state_s;
@@ -103,228 +103,228 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
* Common IRQ numbers for level 1 interrupt handler
* See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
*/
-# define OMAP_INT_CAMERA 1
-# define OMAP_INT_FIQ 3
-# define OMAP_INT_RTDX 6
-# define OMAP_INT_DSP_MMU_ABORT 7
-# define OMAP_INT_HOST 8
-# define OMAP_INT_ABORT 9
-# define OMAP_INT_BRIDGE_PRIV 13
-# define OMAP_INT_GPIO_BANK1 14
-# define OMAP_INT_UART3 15
-# define OMAP_INT_TIMER3 16
-# define OMAP_INT_DMA_CH0_6 19
-# define OMAP_INT_DMA_CH1_7 20
-# define OMAP_INT_DMA_CH2_8 21
-# define OMAP_INT_DMA_CH3 22
-# define OMAP_INT_DMA_CH4 23
-# define OMAP_INT_DMA_CH5 24
-# define OMAP_INT_DMA_LCD 25
-# define OMAP_INT_TIMER1 26
-# define OMAP_INT_WD_TIMER 27
-# define OMAP_INT_BRIDGE_PUB 28
-# define OMAP_INT_TIMER2 30
-# define OMAP_INT_LCD_CTRL 31
+#define OMAP_INT_CAMERA 1
+#define OMAP_INT_FIQ 3
+#define OMAP_INT_RTDX 6
+#define OMAP_INT_DSP_MMU_ABORT 7
+#define OMAP_INT_HOST 8
+#define OMAP_INT_ABORT 9
+#define OMAP_INT_BRIDGE_PRIV 13
+#define OMAP_INT_GPIO_BANK1 14
+#define OMAP_INT_UART3 15
+#define OMAP_INT_TIMER3 16
+#define OMAP_INT_DMA_CH0_6 19
+#define OMAP_INT_DMA_CH1_7 20
+#define OMAP_INT_DMA_CH2_8 21
+#define OMAP_INT_DMA_CH3 22
+#define OMAP_INT_DMA_CH4 23
+#define OMAP_INT_DMA_CH5 24
+#define OMAP_INT_DMA_LCD 25
+#define OMAP_INT_TIMER1 26
+#define OMAP_INT_WD_TIMER 27
+#define OMAP_INT_BRIDGE_PUB 28
+#define OMAP_INT_TIMER2 30
+#define OMAP_INT_LCD_CTRL 31
/*
* Common OMAP-15xx IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_15XX_IH2_IRQ 0
-# define OMAP_INT_15XX_LB_MMU 17
-# define OMAP_INT_15XX_LOCAL_BUS 29
+#define OMAP_INT_15XX_IH2_IRQ 0
+#define OMAP_INT_15XX_LB_MMU 17
+#define OMAP_INT_15XX_LOCAL_BUS 29
/*
* OMAP-1510 specific IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_1510_SPI_TX 4
-# define OMAP_INT_1510_SPI_RX 5
-# define OMAP_INT_1510_DSP_MAILBOX1 10
-# define OMAP_INT_1510_DSP_MAILBOX2 11
+#define OMAP_INT_1510_SPI_TX 4
+#define OMAP_INT_1510_SPI_RX 5
+#define OMAP_INT_1510_DSP_MAILBOX1 10
+#define OMAP_INT_1510_DSP_MAILBOX2 11
/*
* OMAP-310 specific IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_310_McBSP2_TX 4
-# define OMAP_INT_310_McBSP2_RX 5
-# define OMAP_INT_310_HSB_MAILBOX1 12
-# define OMAP_INT_310_HSAB_MMU 18
+#define OMAP_INT_310_McBSP2_TX 4
+#define OMAP_INT_310_McBSP2_RX 5
+#define OMAP_INT_310_HSB_MAILBOX1 12
+#define OMAP_INT_310_HSAB_MMU 18
/*
* OMAP-1610 specific IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_1610_IH2_IRQ 0
-# define OMAP_INT_1610_IH2_FIQ 2
-# define OMAP_INT_1610_McBSP2_TX 4
-# define OMAP_INT_1610_McBSP2_RX 5
-# define OMAP_INT_1610_DSP_MAILBOX1 10
-# define OMAP_INT_1610_DSP_MAILBOX2 11
-# define OMAP_INT_1610_LCD_LINE 12
-# define OMAP_INT_1610_GPTIMER1 17
-# define OMAP_INT_1610_GPTIMER2 18
-# define OMAP_INT_1610_SSR_FIFO_0 29
+#define OMAP_INT_1610_IH2_IRQ 0
+#define OMAP_INT_1610_IH2_FIQ 2
+#define OMAP_INT_1610_McBSP2_TX 4
+#define OMAP_INT_1610_McBSP2_RX 5
+#define OMAP_INT_1610_DSP_MAILBOX1 10
+#define OMAP_INT_1610_DSP_MAILBOX2 11
+#define OMAP_INT_1610_LCD_LINE 12
+#define OMAP_INT_1610_GPTIMER1 17
+#define OMAP_INT_1610_GPTIMER2 18
+#define OMAP_INT_1610_SSR_FIFO_0 29
/*
* OMAP-730 specific IRQ numbers for level 1 interrupt handler
*/
-# define OMAP_INT_730_IH2_FIQ 0
-# define OMAP_INT_730_IH2_IRQ 1
-# define OMAP_INT_730_USB_NON_ISO 2
-# define OMAP_INT_730_USB_ISO 3
-# define OMAP_INT_730_ICR 4
-# define OMAP_INT_730_EAC 5
-# define OMAP_INT_730_GPIO_BANK1 6
-# define OMAP_INT_730_GPIO_BANK2 7
-# define OMAP_INT_730_GPIO_BANK3 8
-# define OMAP_INT_730_McBSP2TX 10
-# define OMAP_INT_730_McBSP2RX 11
-# define OMAP_INT_730_McBSP2RX_OVF 12
-# define OMAP_INT_730_LCD_LINE 14
-# define OMAP_INT_730_GSM_PROTECT 15
-# define OMAP_INT_730_TIMER3 16
-# define OMAP_INT_730_GPIO_BANK5 17
-# define OMAP_INT_730_GPIO_BANK6 18
-# define OMAP_INT_730_SPGIO_WR 29
+#define OMAP_INT_730_IH2_FIQ 0
+#define OMAP_INT_730_IH2_IRQ 1
+#define OMAP_INT_730_USB_NON_ISO 2
+#define OMAP_INT_730_USB_ISO 3
+#define OMAP_INT_730_ICR 4
+#define OMAP_INT_730_EAC 5
+#define OMAP_INT_730_GPIO_BANK1 6
+#define OMAP_INT_730_GPIO_BANK2 7
+#define OMAP_INT_730_GPIO_BANK3 8
+#define OMAP_INT_730_McBSP2TX 10
+#define OMAP_INT_730_McBSP2RX 11
+#define OMAP_INT_730_McBSP2RX_OVF 12
+#define OMAP_INT_730_LCD_LINE 14
+#define OMAP_INT_730_GSM_PROTECT 15
+#define OMAP_INT_730_TIMER3 16
+#define OMAP_INT_730_GPIO_BANK5 17
+#define OMAP_INT_730_GPIO_BANK6 18
+#define OMAP_INT_730_SPGIO_WR 29
/*
* Common IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_KEYBOARD 1
-# define OMAP_INT_uWireTX 2
-# define OMAP_INT_uWireRX 3
-# define OMAP_INT_I2C 4
-# define OMAP_INT_MPUIO 5
-# define OMAP_INT_USB_HHC_1 6
-# define OMAP_INT_McBSP3TX 10
-# define OMAP_INT_McBSP3RX 11
-# define OMAP_INT_McBSP1TX 12
-# define OMAP_INT_McBSP1RX 13
-# define OMAP_INT_UART1 14
-# define OMAP_INT_UART2 15
-# define OMAP_INT_USB_W2FC 20
-# define OMAP_INT_1WIRE 21
-# define OMAP_INT_OS_TIMER 22
-# define OMAP_INT_OQN 23
-# define OMAP_INT_GAUGE_32K 24
-# define OMAP_INT_RTC_TIMER 25
-# define OMAP_INT_RTC_ALARM 26
-# define OMAP_INT_DSP_MMU 28
+#define OMAP_INT_KEYBOARD 1
+#define OMAP_INT_uWireTX 2
+#define OMAP_INT_uWireRX 3
+#define OMAP_INT_I2C 4
+#define OMAP_INT_MPUIO 5
+#define OMAP_INT_USB_HHC_1 6
+#define OMAP_INT_McBSP3TX 10
+#define OMAP_INT_McBSP3RX 11
+#define OMAP_INT_McBSP1TX 12
+#define OMAP_INT_McBSP1RX 13
+#define OMAP_INT_UART1 14
+#define OMAP_INT_UART2 15
+#define OMAP_INT_USB_W2FC 20
+#define OMAP_INT_1WIRE 21
+#define OMAP_INT_OS_TIMER 22
+#define OMAP_INT_OQN 23
+#define OMAP_INT_GAUGE_32K 24
+#define OMAP_INT_RTC_TIMER 25
+#define OMAP_INT_RTC_ALARM 26
+#define OMAP_INT_DSP_MMU 28
/*
* OMAP-1510 specific IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_1510_BT_MCSI1TX 16
-# define OMAP_INT_1510_BT_MCSI1RX 17
-# define OMAP_INT_1510_SoSSI_MATCH 19
-# define OMAP_INT_1510_MEM_STICK 27
-# define OMAP_INT_1510_COM_SPI_RO 31
+#define OMAP_INT_1510_BT_MCSI1TX 16
+#define OMAP_INT_1510_BT_MCSI1RX 17
+#define OMAP_INT_1510_SoSSI_MATCH 19
+#define OMAP_INT_1510_MEM_STICK 27
+#define OMAP_INT_1510_COM_SPI_RO 31
/*
* OMAP-310 specific IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_310_FAC 0
-# define OMAP_INT_310_USB_HHC_2 7
-# define OMAP_INT_310_MCSI1_FE 16
-# define OMAP_INT_310_MCSI2_FE 17
-# define OMAP_INT_310_USB_W2FC_ISO 29
-# define OMAP_INT_310_USB_W2FC_NON_ISO 30
-# define OMAP_INT_310_McBSP2RX_OF 31
+#define OMAP_INT_310_FAC 0
+#define OMAP_INT_310_USB_HHC_2 7
+#define OMAP_INT_310_MCSI1_FE 16
+#define OMAP_INT_310_MCSI2_FE 17
+#define OMAP_INT_310_USB_W2FC_ISO 29
+#define OMAP_INT_310_USB_W2FC_NON_ISO 30
+#define OMAP_INT_310_McBSP2RX_OF 31
/*
* OMAP-1610 specific IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_1610_FAC 0
-# define OMAP_INT_1610_USB_HHC_2 7
-# define OMAP_INT_1610_USB_OTG 8
-# define OMAP_INT_1610_SoSSI 9
-# define OMAP_INT_1610_BT_MCSI1TX 16
-# define OMAP_INT_1610_BT_MCSI1RX 17
-# define OMAP_INT_1610_SoSSI_MATCH 19
-# define OMAP_INT_1610_MEM_STICK 27
-# define OMAP_INT_1610_McBSP2RX_OF 31
-# define OMAP_INT_1610_STI 32
-# define OMAP_INT_1610_STI_WAKEUP 33
-# define OMAP_INT_1610_GPTIMER3 34
-# define OMAP_INT_1610_GPTIMER4 35
-# define OMAP_INT_1610_GPTIMER5 36
-# define OMAP_INT_1610_GPTIMER6 37
-# define OMAP_INT_1610_GPTIMER7 38
-# define OMAP_INT_1610_GPTIMER8 39
-# define OMAP_INT_1610_GPIO_BANK2 40
-# define OMAP_INT_1610_GPIO_BANK3 41
-# define OMAP_INT_1610_MMC2 42
-# define OMAP_INT_1610_CF 43
-# define OMAP_INT_1610_WAKE_UP_REQ 46
-# define OMAP_INT_1610_GPIO_BANK4 48
-# define OMAP_INT_1610_SPI 49
-# define OMAP_INT_1610_DMA_CH6 53
-# define OMAP_INT_1610_DMA_CH7 54
-# define OMAP_INT_1610_DMA_CH8 55
-# define OMAP_INT_1610_DMA_CH9 56
-# define OMAP_INT_1610_DMA_CH10 57
-# define OMAP_INT_1610_DMA_CH11 58
-# define OMAP_INT_1610_DMA_CH12 59
-# define OMAP_INT_1610_DMA_CH13 60
-# define OMAP_INT_1610_DMA_CH14 61
-# define OMAP_INT_1610_DMA_CH15 62
-# define OMAP_INT_1610_NAND 63
+#define OMAP_INT_1610_FAC 0
+#define OMAP_INT_1610_USB_HHC_2 7
+#define OMAP_INT_1610_USB_OTG 8
+#define OMAP_INT_1610_SoSSI 9
+#define OMAP_INT_1610_BT_MCSI1TX 16
+#define OMAP_INT_1610_BT_MCSI1RX 17
+#define OMAP_INT_1610_SoSSI_MATCH 19
+#define OMAP_INT_1610_MEM_STICK 27
+#define OMAP_INT_1610_McBSP2RX_OF 31
+#define OMAP_INT_1610_STI 32
+#define OMAP_INT_1610_STI_WAKEUP 33
+#define OMAP_INT_1610_GPTIMER3 34
+#define OMAP_INT_1610_GPTIMER4 35
+#define OMAP_INT_1610_GPTIMER5 36
+#define OMAP_INT_1610_GPTIMER6 37
+#define OMAP_INT_1610_GPTIMER7 38
+#define OMAP_INT_1610_GPTIMER8 39
+#define OMAP_INT_1610_GPIO_BANK2 40
+#define OMAP_INT_1610_GPIO_BANK3 41
+#define OMAP_INT_1610_MMC2 42
+#define OMAP_INT_1610_CF 43
+#define OMAP_INT_1610_WAKE_UP_REQ 46
+#define OMAP_INT_1610_GPIO_BANK4 48
+#define OMAP_INT_1610_SPI 49
+#define OMAP_INT_1610_DMA_CH6 53
+#define OMAP_INT_1610_DMA_CH7 54
+#define OMAP_INT_1610_DMA_CH8 55
+#define OMAP_INT_1610_DMA_CH9 56
+#define OMAP_INT_1610_DMA_CH10 57
+#define OMAP_INT_1610_DMA_CH11 58
+#define OMAP_INT_1610_DMA_CH12 59
+#define OMAP_INT_1610_DMA_CH13 60
+#define OMAP_INT_1610_DMA_CH14 61
+#define OMAP_INT_1610_DMA_CH15 62
+#define OMAP_INT_1610_NAND 63
/*
* OMAP-730 specific IRQ numbers for level 2 interrupt handler
*/
-# define OMAP_INT_730_HW_ERRORS 0
-# define OMAP_INT_730_NFIQ_PWR_FAIL 1
-# define OMAP_INT_730_CFCD 2
-# define OMAP_INT_730_CFIREQ 3
-# define OMAP_INT_730_I2C 4
-# define OMAP_INT_730_PCC 5
-# define OMAP_INT_730_MPU_EXT_NIRQ 6
-# define OMAP_INT_730_SPI_100K_1 7
-# define OMAP_INT_730_SYREN_SPI 8
-# define OMAP_INT_730_VLYNQ 9
-# define OMAP_INT_730_GPIO_BANK4 10
-# define OMAP_INT_730_McBSP1TX 11
-# define OMAP_INT_730_McBSP1RX 12
-# define OMAP_INT_730_McBSP1RX_OF 13
-# define OMAP_INT_730_UART_MODEM_IRDA_2 14
-# define OMAP_INT_730_UART_MODEM_1 15
-# define OMAP_INT_730_MCSI 16
-# define OMAP_INT_730_uWireTX 17
-# define OMAP_INT_730_uWireRX 18
-# define OMAP_INT_730_SMC_CD 19
-# define OMAP_INT_730_SMC_IREQ 20
-# define OMAP_INT_730_HDQ_1WIRE 21
-# define OMAP_INT_730_TIMER32K 22
-# define OMAP_INT_730_MMC_SDIO 23
-# define OMAP_INT_730_UPLD 24
-# define OMAP_INT_730_USB_HHC_1 27
-# define OMAP_INT_730_USB_HHC_2 28
-# define OMAP_INT_730_USB_GENI 29
-# define OMAP_INT_730_USB_OTG 30
-# define OMAP_INT_730_CAMERA_IF 31
-# define OMAP_INT_730_RNG 32
-# define OMAP_INT_730_DUAL_MODE_TIMER 33
-# define OMAP_INT_730_DBB_RF_EN 34
-# define OMAP_INT_730_MPUIO_KEYPAD 35
-# define OMAP_INT_730_SHA1_MD5 36
-# define OMAP_INT_730_SPI_100K_2 37
-# define OMAP_INT_730_RNG_IDLE 38
-# define OMAP_INT_730_MPUIO 39
-# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
-# define OMAP_INT_730_LLPC_OE_FALLING 41
-# define OMAP_INT_730_LLPC_OE_RISING 42
-# define OMAP_INT_730_LLPC_VSYNC 43
-# define OMAP_INT_730_WAKE_UP_REQ 46
-# define OMAP_INT_730_DMA_CH6 53
-# define OMAP_INT_730_DMA_CH7 54
-# define OMAP_INT_730_DMA_CH8 55
-# define OMAP_INT_730_DMA_CH9 56
-# define OMAP_INT_730_DMA_CH10 57
-# define OMAP_INT_730_DMA_CH11 58
-# define OMAP_INT_730_DMA_CH12 59
-# define OMAP_INT_730_DMA_CH13 60
-# define OMAP_INT_730_DMA_CH14 61
-# define OMAP_INT_730_DMA_CH15 62
-# define OMAP_INT_730_NAND 63
+#define OMAP_INT_730_HW_ERRORS 0
+#define OMAP_INT_730_NFIQ_PWR_FAIL 1
+#define OMAP_INT_730_CFCD 2
+#define OMAP_INT_730_CFIREQ 3
+#define OMAP_INT_730_I2C 4
+#define OMAP_INT_730_PCC 5
+#define OMAP_INT_730_MPU_EXT_NIRQ 6
+#define OMAP_INT_730_SPI_100K_1 7
+#define OMAP_INT_730_SYREN_SPI 8
+#define OMAP_INT_730_VLYNQ 9
+#define OMAP_INT_730_GPIO_BANK4 10
+#define OMAP_INT_730_McBSP1TX 11
+#define OMAP_INT_730_McBSP1RX 12
+#define OMAP_INT_730_McBSP1RX_OF 13
+#define OMAP_INT_730_UART_MODEM_IRDA_2 14
+#define OMAP_INT_730_UART_MODEM_1 15
+#define OMAP_INT_730_MCSI 16
+#define OMAP_INT_730_uWireTX 17
+#define OMAP_INT_730_uWireRX 18
+#define OMAP_INT_730_SMC_CD 19
+#define OMAP_INT_730_SMC_IREQ 20
+#define OMAP_INT_730_HDQ_1WIRE 21
+#define OMAP_INT_730_TIMER32K 22
+#define OMAP_INT_730_MMC_SDIO 23
+#define OMAP_INT_730_UPLD 24
+#define OMAP_INT_730_USB_HHC_1 27
+#define OMAP_INT_730_USB_HHC_2 28
+#define OMAP_INT_730_USB_GENI 29
+#define OMAP_INT_730_USB_OTG 30
+#define OMAP_INT_730_CAMERA_IF 31
+#define OMAP_INT_730_RNG 32
+#define OMAP_INT_730_DUAL_MODE_TIMER 33
+#define OMAP_INT_730_DBB_RF_EN 34
+#define OMAP_INT_730_MPUIO_KEYPAD 35
+#define OMAP_INT_730_SHA1_MD5 36
+#define OMAP_INT_730_SPI_100K_2 37
+#define OMAP_INT_730_RNG_IDLE 38
+#define OMAP_INT_730_MPUIO 39
+#define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
+#define OMAP_INT_730_LLPC_OE_FALLING 41
+#define OMAP_INT_730_LLPC_OE_RISING 42
+#define OMAP_INT_730_LLPC_VSYNC 43
+#define OMAP_INT_730_WAKE_UP_REQ 46
+#define OMAP_INT_730_DMA_CH6 53
+#define OMAP_INT_730_DMA_CH7 54
+#define OMAP_INT_730_DMA_CH8 55
+#define OMAP_INT_730_DMA_CH9 56
+#define OMAP_INT_730_DMA_CH10 57
+#define OMAP_INT_730_DMA_CH11 58
+#define OMAP_INT_730_DMA_CH12 59
+#define OMAP_INT_730_DMA_CH13 60
+#define OMAP_INT_730_DMA_CH14 61
+#define OMAP_INT_730_DMA_CH15 62
+#define OMAP_INT_730_NAND 63
/* omap_dma.c */
enum omap_dma_model {
@@ -353,9 +353,9 @@ struct dma_irq_map {
enum omap_dma_port {
emiff = 0,
emifs,
- imif, /* omap16xx: ocp_t1 */
+ imif, /* omap16xx: ocp_t1 */
tipb,
- local, /* omap16xx: ocp_t2 */
+ local, /* omap16xx: ocp_t2 */
tipb_mpui,
__omap_dma_port_last,
};
@@ -418,65 +418,65 @@ struct omap_dma_lcd_channel_s {
* DMA request numbers for OMAP1
* See /usr/include/asm-arm/arch-omap/dma.h in Linux.
*/
-# define OMAP_DMA_NO_DEVICE 0
-# define OMAP_DMA_MCSI1_TX 1
-# define OMAP_DMA_MCSI1_RX 2
-# define OMAP_DMA_I2C_RX 3
-# define OMAP_DMA_I2C_TX 4
-# define OMAP_DMA_EXT_NDMA_REQ0 5
-# define OMAP_DMA_EXT_NDMA_REQ1 6
-# define OMAP_DMA_UWIRE_TX 7
-# define OMAP_DMA_MCBSP1_TX 8
-# define OMAP_DMA_MCBSP1_RX 9
-# define OMAP_DMA_MCBSP3_TX 10
-# define OMAP_DMA_MCBSP3_RX 11
-# define OMAP_DMA_UART1_TX 12
-# define OMAP_DMA_UART1_RX 13
-# define OMAP_DMA_UART2_TX 14
-# define OMAP_DMA_UART2_RX 15
-# define OMAP_DMA_MCBSP2_TX 16
-# define OMAP_DMA_MCBSP2_RX 17
-# define OMAP_DMA_UART3_TX 18
-# define OMAP_DMA_UART3_RX 19
-# define OMAP_DMA_CAMERA_IF_RX 20
-# define OMAP_DMA_MMC_TX 21
-# define OMAP_DMA_MMC_RX 22
-# define OMAP_DMA_NAND 23 /* Not in OMAP310 */
-# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
-# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
-# define OMAP_DMA_USB_W2FC_RX0 26
-# define OMAP_DMA_USB_W2FC_RX1 27
-# define OMAP_DMA_USB_W2FC_RX2 28
-# define OMAP_DMA_USB_W2FC_TX0 29
-# define OMAP_DMA_USB_W2FC_TX1 30
-# define OMAP_DMA_USB_W2FC_TX2 31
+#define OMAP_DMA_NO_DEVICE 0
+#define OMAP_DMA_MCSI1_TX 1
+#define OMAP_DMA_MCSI1_RX 2
+#define OMAP_DMA_I2C_RX 3
+#define OMAP_DMA_I2C_TX 4
+#define OMAP_DMA_EXT_NDMA_REQ0 5
+#define OMAP_DMA_EXT_NDMA_REQ1 6
+#define OMAP_DMA_UWIRE_TX 7
+#define OMAP_DMA_MCBSP1_TX 8
+#define OMAP_DMA_MCBSP1_RX 9
+#define OMAP_DMA_MCBSP3_TX 10
+#define OMAP_DMA_MCBSP3_RX 11
+#define OMAP_DMA_UART1_TX 12
+#define OMAP_DMA_UART1_RX 13
+#define OMAP_DMA_UART2_TX 14
+#define OMAP_DMA_UART2_RX 15
+#define OMAP_DMA_MCBSP2_TX 16
+#define OMAP_DMA_MCBSP2_RX 17
+#define OMAP_DMA_UART3_TX 18
+#define OMAP_DMA_UART3_RX 19
+#define OMAP_DMA_CAMERA_IF_RX 20
+#define OMAP_DMA_MMC_TX 21
+#define OMAP_DMA_MMC_RX 22
+#define OMAP_DMA_NAND 23 /* Not in OMAP310 */
+#define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
+#define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
+#define OMAP_DMA_USB_W2FC_RX0 26
+#define OMAP_DMA_USB_W2FC_RX1 27
+#define OMAP_DMA_USB_W2FC_RX2 28
+#define OMAP_DMA_USB_W2FC_TX0 29
+#define OMAP_DMA_USB_W2FC_TX1 30
+#define OMAP_DMA_USB_W2FC_TX2 31
/* These are only for 1610 */
-# define OMAP_DMA_CRYPTO_DES_IN 32
-# define OMAP_DMA_SPI_TX 33
-# define OMAP_DMA_SPI_RX 34
-# define OMAP_DMA_CRYPTO_HASH 35
-# define OMAP_DMA_CCP_ATTN 36
-# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
-# define OMAP_DMA_CMT_APE_TX_CHAN_0 38
-# define OMAP_DMA_CMT_APE_RV_CHAN_0 39
-# define OMAP_DMA_CMT_APE_TX_CHAN_1 40
-# define OMAP_DMA_CMT_APE_RV_CHAN_1 41
-# define OMAP_DMA_CMT_APE_TX_CHAN_2 42
-# define OMAP_DMA_CMT_APE_RV_CHAN_2 43
-# define OMAP_DMA_CMT_APE_TX_CHAN_3 44
-# define OMAP_DMA_CMT_APE_RV_CHAN_3 45
-# define OMAP_DMA_CMT_APE_TX_CHAN_4 46
-# define OMAP_DMA_CMT_APE_RV_CHAN_4 47
-# define OMAP_DMA_CMT_APE_TX_CHAN_5 48
-# define OMAP_DMA_CMT_APE_RV_CHAN_5 49
-# define OMAP_DMA_CMT_APE_TX_CHAN_6 50
-# define OMAP_DMA_CMT_APE_RV_CHAN_6 51
-# define OMAP_DMA_CMT_APE_TX_CHAN_7 52
-# define OMAP_DMA_CMT_APE_RV_CHAN_7 53
-# define OMAP_DMA_MMC2_TX 54
-# define OMAP_DMA_MMC2_RX 55
-# define OMAP_DMA_CRYPTO_DES_OUT 56
+#define OMAP_DMA_CRYPTO_DES_IN 32
+#define OMAP_DMA_SPI_TX 33
+#define OMAP_DMA_SPI_RX 34
+#define OMAP_DMA_CRYPTO_HASH 35
+#define OMAP_DMA_CCP_ATTN 36
+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
+#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
+#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
+#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
+#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
+#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
+#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
+#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
+#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
+#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
+#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
+#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
+#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
+#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
+#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
+#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
+#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
+#define OMAP_DMA_MMC2_TX 54
+#define OMAP_DMA_MMC2_RX 55
+#define OMAP_DMA_CRYPTO_DES_OUT 56
struct omap_uart_s;
struct omap_uart_s *omap_uart_init(hwaddr base,
@@ -542,14 +542,14 @@ void omap_mmc_set_clk(DeviceState *dev, omap_clk clk);
/* omap_i2c.c */
I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
-# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
-# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
-# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
-# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
+#define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
+#define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
+#define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
+#define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
-# define cpu_is_omap15xx(cpu) \
+#define cpu_is_omap15xx(cpu) \
(cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
-# define cpu_is_omap16xx(cpu) \
+#define cpu_is_omap16xx(cpu) \
(cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
struct omap_mpu_state_s {
@@ -685,14 +685,14 @@ void omap_badwidth_write32(void *opaque, hwaddr addr,
void omap_mpu_wakeup(void *opaque, int irq, int req);
-# define OMAP_BAD_REG(paddr) \
+#define OMAP_BAD_REG(paddr) \
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
__func__, paddr)
-# define OMAP_RO_REG(paddr) \
+#define OMAP_RO_REG(paddr) \
qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
HWADDR_PRIx "\n", \
__func__, paddr)
-# define OMAP_MPUI_REG_MASK 0x000007ff
+#define OMAP_MPUI_REG_MASK 0x000007ff
#endif
diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h
index e986b28..1e3992f 100644
--- a/include/hw/arm/sharpsl.h
+++ b/include/hw/arm/sharpsl.h
@@ -11,7 +11,7 @@
/* zaurus.c */
-#define SL_PXA_PARAM_BASE 0xa0000a00
+#define SL_PXA_PARAM_BASE 0xa0000a00
void sl_bootparam_write(hwaddr ptr);
#endif
diff --git a/include/hw/arm/soc_dma.h b/include/hw/arm/soc_dma.h
index e93a749..bcdb914 100644
--- a/include/hw/arm/soc_dma.h
+++ b/include/hw/arm/soc_dma.h
@@ -54,7 +54,7 @@ struct soc_dma_ch_s {
int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2];
- hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
+ hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */
void *paddr[2];
soc_dma_io_t io_fn[2];
@@ -70,7 +70,7 @@ struct soc_dma_ch_s {
struct soc_dma_s {
/* Following fields are set by the SoC DMA module and can be used
* by anybody. */
- uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
+ uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
qemu_irq *drq;
void *opaque;
int64_t freq;
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 4f4c8bb..46eda34 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -59,7 +59,7 @@ struct STM32F205State {
STM32F2XXADCState adc[STM_NUM_ADCS];
STM32F2XXSPIState spi[STM_NUM_SPIS];
- OrIRQState *adc_irqs;
+ OrIRQState adc_irqs;
MemoryRegion sram;
MemoryRegion flash;
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 9a1b0f5..365a28b 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -36,6 +36,7 @@
#include "hw/arm/boot.h"
#include "hw/arm/bsa.h"
#include "hw/block/flash.h"
+#include "hw/cxl/cxl.h"
#include "system/kvm.h"
#include "hw/intc/arm_gicv3_common.h"
#include "qom/object.h"
@@ -79,12 +80,14 @@ enum {
VIRT_ACPI_GED,
VIRT_NVDIMM_ACPI,
VIRT_PVTIME,
+ VIRT_ACPI_PCIHP,
VIRT_LOWMEMMAP_LAST,
};
/* indices of IO regions located after the RAM */
enum {
VIRT_HIGH_GIC_REDIST2 = VIRT_LOWMEMMAP_LAST,
+ VIRT_CXL_HOST,
VIRT_HIGH_PCIE_ECAM,
VIRT_HIGH_PCIE_MMIO,
};
@@ -140,6 +143,7 @@ struct VirtMachineState {
bool secure;
bool highmem;
bool highmem_compact;
+ bool highmem_cxl;
bool highmem_ecam;
bool highmem_mmio;
bool highmem_redists;
@@ -174,6 +178,7 @@ struct VirtMachineState {
char *oem_id;
char *oem_table_id;
bool ns_el2_virt_timer_irq;
+ CXLState cxl_devices_state;
};
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
diff --git a/include/hw/arm/xen_arch_hvm.h b/include/hw/arm/xen_arch_hvm.h
deleted file mode 100644
index 8fd645e..0000000
--- a/include/hw/arm/xen_arch_hvm.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef HW_XEN_ARCH_ARM_HVM_H
-#define HW_XEN_ARCH_ARM_HVM_H
-
-#include <xen/hvm/ioreq.h>
-void arch_handle_ioreq(XenIOState *state, ioreq_t *req);
-void arch_xen_set_memory(XenIOState *state,
- MemoryRegionSection *section,
- bool add);
-#endif
generated by cgit v1.1 at 2025-09-03 21:24:59 +0000