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-rw-r--r--include/accel/tcg/cpu-ops.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index f60e530..0e43525 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -16,9 +16,25 @@
#include "exec/memop.h"
#include "exec/mmu-access-type.h"
#include "exec/vaddr.h"
+#include "tcg/tcg-mo.h"
struct TCGCPUOps {
/**
+ * mttcg_supported: multi-threaded TCG is supported
+ *
+ * Target (TCG frontend) supports:
+ * - atomic instructions
+ * - memory ordering primitives (barriers)
+ */
+ bool mttcg_supported;
+
+ /**
+ * @guest_default_memory_order: default barrier that is required
+ * for the guest memory ordering.
+ */
+ TCGBar guest_default_memory_order;
+
+ /**
* @initialize: Initialize TCG state
*
* Called when the first CPU is realized.
@@ -67,6 +83,9 @@ struct TCGCPUOps {
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
+ /** @mmu_index: Callback for choosing softmmu mmu index */
+ int (*mmu_index)(CPUState *cpu, bool ifetch);
+
#ifdef CONFIG_USER_ONLY
/**
* @fake_user_interrupt: Callback for 'fake exception' handling.